ICE25P05 512K bit, Low Voltage, Serial Flash Memory FEATURES SUMMARY *512 Kbit of Flash Memory *Page Program (up to 128 Bytes) in 3 ms (typical) *Sector Erase (256 Kbit) in 1S (typical) *Bulk Erase (512 Kbit) in 2S (typical) *2.7 v to 3.6 v Single Supply Voltage *SPI Bus Compatible Serial Interface *20 MHz Clock Rate (maximum) *Standby current 1 μA (typical) *More than 10,000 Erase/Program Cycles per Sector *More than 20 Year Data Retention ICE25P05 /S 1 8 Vcc Q 2 7 /HOLD /W 3 6 C Vss 4 5 D 1 ICE semiconductor, inc. Rev.1.6 2003/4/15 ICE25P05 SUMMARY DESCRIPTION THE ICE25P05 is a 512 Kbit (64k x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI compatible bus. THE memory can be programmed 128 byes at a time, using the Page Program instruction. The memory is organized as 2 sectors, each containing 256 pages. Each page is 128 bytes wide Thus, the whole memory can be viewed as consisting of 512 pages, or 65536 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Table 1. Signal Name C Serial Clock D Serial Data Input Q Serial Data Output Chip Select S Write Protect W Hold HOLD Vcc Supply Voltage Vss Ground SINAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C) Serial Data input(D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock ( C ) Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock ( C ). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock ( C ). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode After Power-up, a falling edge on Chip Select(S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device . During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock © are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Write Protect (W). The main purpose of the input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). SPI MODES These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes: -CPOL=0, CPHA=0 -CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock ( C ), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown In Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data: - C remains at 0 for (CPOL=0, CPHA=0) - C remains at 1 for (CPOL=1, CPHA=1) Figure 4.Bus Master and Memory Devices on the SPI Bus SPI INTERFACE WITH (CPOL, CPHA)= (0,0) or (1,1) DO DI CK C QD C Q D Bus Master (D2,D4,D6, ,Others) CS3 CS2 CS1 /S /W /HOLD /S /W C Q D /HOLD /S /W /HOLD NOTE: 1.The Write Protect (/W) and Hold (/HOLD) signals should be driven, High or low as appropriate Figure 5. SPI Modes Supported 3 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 CPOL CPHA 0 0 C 1 1 C D or Q LSB OPERATING FEATURES Page Programming To program one data byte , two instructions are required: Write Enable (WREN),which is one byte, and a Page Program (PP)sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tpp). To spread this overhead, the Page Program (PP) instruction allows up to 128 bytes to be programmed at a time (changing bits from 1 to0), pro-vided that they lie in consecutive addresses on the same page of memory. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. Polling During a Program Cycle or Erase Cycle A further improvement in the programming time or erase time can be achieved by not waiting for the worst case delay(tw, tpp, tse, or tBe). The Write in progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Pro- gram cycle or Erase cycle is complete. Status Register The Status Register contains a number of status and control bits, as shown in Table 5, that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. BP1, BP0 bits. The Block Protect (BP1,BP0) bits are volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) Signal allow the device to be put in the Hardware Protected mode. In this mode, the volatile bits Of the Status Register (SRWD,BP1,BP0) become read-only bits. 4 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Table 2. Protected Area Sizes Status Register content BP1 bit 0 0 1 1 BP0 bit 0 1 0 1 Memory Content Protect Area Unprotected Area none All sectors(Sector 0 and 1) All sectors(Sector 0 and 1) none Protection Modes The environments where non-volatile memory devices are used can be very nosy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the ICE25P05 boasts the *Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. *All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events; -Power-up -Write Disable(WRDI)instruction completion -Write Status Register (WRSR) instruction completion -Page Erase (PP) instruction completion -Sector Erase (SE) instruction completion -Bulk Erase (BE) instruction completion *The Block Protect (BP1,BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). *The Write Protect(W) signal allows the Block Protect(BP1,BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is Hardware Protected Mode (HPM). Figure 6.Hold Condition Activation C /HOLD Hold Active 5 Active Hold Active ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 VCC STATUS REGISTER GND MEMORY ARRAY 65,536 x 8 ADDRESS DECODER DATA REGISTER D /S /W C OUTPUT BUFFER MODE DECODE LOGIC CLOCK GENERATOR Q /HOLD Hold Condition The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be Selected, with Chip Select (/S) Low. The Hold condition starts on the falling edge of the hold (/HOLD) signal, provided that this coincides with Serial Clock ( C ) being Low (as shown in Figure 6) The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock ( C ) being Low, the Hold condition starts when Serial Clock (C) next goes Low, Similarly. If the rising edge does not coincide with Serial Clock ( C ) being Low, the Hold condition ends when Serial Clock ( C ) next goes Low. (This is shown in Figure6). During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. Normally, the device is kept selected, with Chip Select (/S) driven Low, for the whole duration of the Hold condition. If Chip Select (/S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. The memory remains in the Hold condition as long as Hold (/HOLD) is Low. To restart communication with the device, it is necessary both to drive Hold (/HOLD) High, and to drive Chip Select (S) Low. 6 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 MEMORY ORGANIZATION The memory is organized as: *65536 bytes (8 bits each) *2 sectors (256 kbits, 32768 bytes each) *512 pages (128 bytes each). Each page can be individually programmed (bits Are programmed from 1 to 0 ). The device is sector Or Bulk Erasable (bits are erased from 0 to 1 ) but Not Page Erasable. Table 3. Memory Organization Sector Address Range 1 08000h 0FFFFh 0 00000h 07FFFh INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. The, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock ( C ). The instruction set is listed in Table 4. Depending on the instruction, the one-byte instruction code is followed by address bytes, or by must be driven High after the last bit of the instruction sequence has been shifted in. At the end of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE) or Write Status Register (WRSR) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 4.Instruction Set Instruction Description One bit Instruction code WREN WRDI RDSR WRSR READ PP SE BE RDID Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes Page Program Sector Erase Bulk Erase Read Device ID 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 1101 1000 1100 0111 0001 0101 7 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Figure 8. Write Enable (WREN) sequence /S C 0 1 2 3 4 5 6 7 Instruction D HIGH Impednce Q Write Enable (WREN) The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 9. Write Disable (WRDI) Sequence /S 0 1 2 3 4 5 6 7 C Instruction D Q High Impednce 8 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions: -Power-up -Write Disable (WRDI) instruction completion -Write Status Register (WRSR) instruction completion -Sector Erase (SE) instruction completion -Bulk Erase (BE) instruction completion Figure 10. Read Status Register (RDSR) Sequence /S 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out High Impedance Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Read Status Register (RDSR) The read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new instruction to the device. it is also possible to read the Status Register continuously, as shown in Figure 10. Table 5.Status Register Format b7 SRWD 0 0 0 b0 BP1 BP0 WEL WIP Note:1.SRWD, BP1 and BP0 are volatile read and write bits 2.WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device). The status and control bits of the Status Register are as follows: 9 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 WIP bit. The Write In Process (WIP) bit indicated whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. BP1,BP0 bits. The block Protect(BP1,BP0) bits are volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When both of the block Protect (BP1,BP0) bits are set to 1, the whole memory is protected against Page Program (PP) and Sector Erase (SE) instruction. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1,BP0) bits are reset to 0, the summarized in Table 2. The Block Protect (BP1.BP0) bits can be written provided that the Hard-ware Protected mode has not been set. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the volatile bits of the Status Register (SRWD,BP1,BP0) be come read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register(WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data input (D) The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b4, b1 and b0 of the Status Register. B6, b5, and b4 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. lf not, the Write Status Register (WRSR) instruction is not executed. AS soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tw) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in Progress (WIP) bit. The Write in Progress Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1,BP0)bits, to define the size of the area that is to be treated as readonly, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the cordance with the Write Protect (W) signal. The 10 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. Read Product ID (RDID) The RDID instruction allows the user to read the manufacturer and product ID of the device(32bits) . The first and second byte after instruction is continue code 7F,7F, the third byte and fourth byte is Manufacturer code(5E) and ID code(01) . Figure 11. Write Status Register (WRSR)Sequence /S 0 C 1 2 3 4 5 6 7 9 8 10 7 High Impedance 14 15 Status Register In Instruction D 11 12 13 6 5 4 3 2 1 0 MSB Q A102282C Table 6. Protection Modes W SRWD singal Bit 1 0 0 0 1 1 0 1 Mode Write Protection of the Status Register Status Register is Writable (if the WREN Instruction has set the Software Protected(SPM) WEL bit) The values in the BP1 and BP0 bits can be changed Status Register is Hardware Write protected Hardware Protected(HPM) The values in the BP1 and BP0 bits cannot be changed Memory Content Protected Unprotected Area1 Area1 Protected against page Program and Sector Erase Ready to accept page Program and Sector Erase instructions Protected against Ready to accept Page Page Program and Program and Sector Sector Erase instructions Erase Note:1. As defined by the values in the Block Protect (BP1,BP0)bits of the Status Register, as in Table 2. 11 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 The protection features of the device are summarized in Tabe 6. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (/W) is driven High or Low. -If Write Protect (/W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. -If Write Protect (/W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously Been set by a Write Enable (WREN) instruction.(Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1,BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: -by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low -or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be aivated, and only the Software Protected Mode (SPM), using the Block Protect (BP1,BP0) bits of the Status Register, can be used. Figure 12. Read Data Bytes (READ) Sequence /S 0 1 2 3 4 5 6 8 7 9 29 28 10 30 31 32 33 35 34 36 37 38 3 9 C Instruction D 24-Bit Address 23 22 21 3 2 1 0 Data out 1 High Impedance 7 Q 6 5 4 Data Out 2 3 2 1 0 7 MSB 12 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Byte (READ) instruction is followed by a 3-byte address (A23-A0), of which the most significant byte (A23-A16) is 00h, each bit being latched-in during the rising edge of Serial Clock ( C ) . Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction There is no address roll-over, when the highest address (0FFFFh) is reached, the instruction should be terminated. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write Status Register cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Page Program (PP) Sequence /S 1 0 2 3 5 4 6 7 8 9 23 22 28 10 30 29 31 32 33 34 7 6 5 36 35 38 39 1 0 37 C Instruction 24-Bit Address 21 3 Data Byle 1 1 2 0 46 47 48 49 51 50 52 53 54 55 1055 45 1054 44 1052 43 2 1053 42 3 1051 41 1050 /S 1049 MSB 40 4 MSB 1048 D C Data Bte 3 Data Byte 2 D 7 MSB 6 5 4 3 2 1 0 7 6 5 MSB 4 3 Data Byte 128 2 1 0 7 6 5 4 3 2 1 0 MSB 13 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Page Program (PP) The page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by Driving Chip Select (/S) Low, followed by the instruction code, three address bits (of which the most significant byte, A23-A16, must be 00h) and at least one data byte on Serial Data input (D). if the 7 least significant address bits (A6-A0)are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page (the one whose 7 least significant address bits (A6-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. If more than 128 bytes are sent to the device, previously latched data are data are discarded and the last 128 data bytes are guaranteed to be programmed correctly within the same page. If less than 128 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self. timed Page Program cycle (whose duration is tpp) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Program (WIP) bit. The Write in Progress (WIP) bit is 1 during the self timed Page Program cycle, and is 0 when it is compeleted. When the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP0,BP1) bits (see Table 2) is not executed. Figure 14.Sector Erase (SE) Sequence /s 0 1 2 3 4 5 6 7 8 9 29 30 31 2 1 0 c 24 Bit Address Instruction D 23 22 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) The Sector Erase (SE) instruction is entered by driving Chip Select (/S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Sector Erase 14 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Table3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. AS soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE ) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP1,BP0) bits (see Table 2) is not executed. Figure 15. Bulk Erase (BE) Sequence /S 0 1 2 3 4 5 6 7 C D Bulk Erase (BE) The bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write En-able Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (/S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (/S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self- timed Bulk Erase cycle,, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1,BP0) bit are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected 15 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 POWER-UP, POER-DOWN DELIVERY STATE Power-up At Power-up, the device must not be selected (that is Chip Select (S) must follow the voltage supplied on Vcc) until the supply voltage supplied Vcc(min), and a further tvs L delay has elapsed. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while Vcc is less than the POR threshold value, VwI –all operations are disabled, and the device will not respond to any instruction. Similarly, when Vcc drops from the operating voltage, to below the POR threshold value, VwI, all operations are disabled and the device will not respond to any instruction. No instructions (including Read, Write Status Register, Program or Erase instructions) should be sent to the device until a time delay of tVSL after Vcc has risen above the Vcc(min) level. Moreover, the device ignores all Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that Vcc rises above the VwI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No Write Status Register, Program or Erase instructions should be sent until the later of: -tPUW after Vcc passed the VwI threshold -tVSL afterVcc passed the Vcc(min) level These values are specified in Table 7. -The Write Enable Latch (WEL) bit is reset. Power-down At Power-up and Power-down, the device must not be selected (tat is Chip Select (S) must follow the voltage applied on Vcc) until Vcc reaches the correct value; -Vcc(min) at Power-up -Vss at Poweer-down A simple pull-up resistor on Chip Select (S) can be used to insure safe and proper Powerup and Power-down. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Table 8. Initial Status Register Format b7 b0 0 0 0 0 0 16 0 0 0 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10. Operating Conditions Symbol Parameter Vcc Supply Voltage TA Ambient operating Temperature Table 11.AC Measurement Conditions Symbol Parameter Load Capacitance CL Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Min 2.7 -4.0 Max 36. 85 Min 30 Max PF 0.2Vcc to 0.8Vcc 0.3Vcc to 0.7Vcc Unit V ℃ Unit CL 5 V V Note: 1. Output HI-Z is defined as the point where data out is no longer driven. Figure 20. AC Measurement I/0 Wave form 0.8Vcc 0.7Vcc 0.3Vcc 0.2Vcc Table 12. Capacitance Symbol Parameter Test Condition Min. Max. Unit Output Capacitance CouT Vout=OV 8 pF (Q) Input Capacitance CIN VIN=OV 6 pF (other pins) Note: Sampled only, not 100% tested, at TA=25℃ and a frequency of 20MHz 17 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Table 13. DC Characteristics Symbol IL1 IL0 Icc1 Icc2 Icc3 Icc4 Icc5 Icc6 VIL VIH VOL VOH Parameter Test Condition (in addition those in Table 10) Min Max Unit ±2 μA ±2 μA S=Vcc,Vin=Vss or Vcc 1 μA Operating Current(READ) C=0.1Vcc/0.9.Vcc at 20 MHZ, Q=open 15 mA Operating Current (PP) S=Vcc 15 mA Operating Current (WRSR) S=Vcc 15 mA Operating Current (SE) S=Vcc 15 mA Operating Current (BE) S=Vcc 15 mA Input Low Voltage -0.5 0.3Vcc V Input High Voltage 0.7Vcc Vcc+1 V Output Low Voltage IOL=1.6mA 0.4 V Output High Voltage IOH=100μA VccV 0.2 Input Leakage Current Output Leakage Current Standby Current Table 14. Characteristics Test conditions specified in Table 10 and Tabel 11 Symbol Alt Parameter Min. Max. fc fc Clock Frequency D.C 20 tcss S Active Setup Time (relative to C) 10 tSLCH S Not Active Hold Time (relative to C) 10 tCHSL 22 tch1 tCLH Clock High Time 22 tCL1 tCLL Clock High Time 5 tDVCH tDSU Data In Setup Time 5 tCHDX tDH Data In Hold Time S Active Hold Time (relative to C) 10 tCHSH S Not Active Setup Time (relative to C) 10 tSHCH 10 tSHSL tCSH S Deselect Time 20 tSHQZ2 tDIS Output Disable Time Clock Low to Output Vaild 20 tCLQV tV 0 tCLQX tHO Output Hold Time HOLD Setup time (relative to C) 10 tHLCH HOLD Hold Time (relative to C) 10 tCHHH HOLD Setup time (relative to C) 10 tHHCH HOLD Hold Time (relative to C) 10 tCHHL 20 tHHQX tLZ HOLD to Output Low-z 20 tHLQZ tHZ HOLD to Output High-z Write Status Register Cycle Time 5 tw Page Program Cycle Time 5 tPP Sector Erase Cycle Time 2 tSE 18 unit MHz ns ns ns ns ns ns ns ns us ns ns ns ns ns ns ns ns ns ms ms s ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 tBE Endurance Bulk Erase Cycle Time 4 10k (2) s Program cycles(3) Note: 1.tCH+tCL must be greater than or equal to 1/fc 2.This parameter is characterized at 3.3v,55oC and is not 100% tested. 3.One program cycle consists of Bulk erase,write,verify. Figure 21. Serial Input Timing tSHSL /S t SLCH tCHSL t CHSH t SHCH C tCHCL t DVCH tCHDX tCLCH D MSB IN LSB IN Q High Impedance Figure 23. output Timing /S t CH C t CLQV tCL tCLQX Q tSHQZ LSB OUT t QLQH t QHQL ADDR LSB IN D 19 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 Figure 24 . Program Flow Power On No “RDSR” Bit 0 = 0 ? “WREN” “WRSR” Bit 3, 2 = 0 ,0 (Unprotect) Yes “ WREN” No “BE” (Bulk Erase) Or “SE” (Sector Erasr) Compare One Page (128Byte) To Original Data Y No Pass “RDSR” Bit0 = 0 ? Yes Read “FF” No All Address or One Sector Complete ? Fail Yes “WREN” “PP” (Page Program) 20 ICE semiconductor, inc. Rev 1.6 2003/4/15 ICE25P05 S08 narrow –8 lead Plastic Small Outline, 150 mils body width Symbol A A1 B C D E e H h L α N CP Type 1.27 mm Min. 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0° 8 Max. 1.75 0.25 0.51 0.25 5.00 4.00 3.20 0.50 0.90 8° 0.10 21 Type 0.050 inches Min. 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.010 0.016 0° Max. 0.069 0.010 0.020 0.010 0.197 0.157 0.244 0.020 0.035 8° 0.004 ICE semiconductor, inc. Rev 1.6 2003/4/15