INTERSIL ICL3222ECV

ICL3221E, ICL3222E, ICL3223E,
ICL3232E, ICL3241E, ICL3243E
®
Data Sheet
March 8, 2005
±15kV ESD Protected, +3V to +5.5V,
1Microamp, 250kbps, RS-232
Transmitters/Receivers
FN4910.18
Features
• Pb-free Available (RoHS Compliant) (See Ordering Info)
The Intersil ICL32XXE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Additionally,
they provide ±15kV ESD protection (IEC61000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and automatic powerdown functions
(except for the ICL3232E), reduce the standby supply
current to a 1µA trickle. Small footprint packaging, and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 250kbps are
guaranteed at worst case load conditions. This family is fully
compatible with 3.3V-only systems, mixed 3.3V and 5.0V
systems, and 5.0V-only systems.
• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)
• Drop in Replacements for MAX3221E, MAX3222E,
MAX3223E, MAX3232E, MAX3241E, MAX3243E,
SP3243E
• ICL3221E is a Low Power, Pin Compatible Upgrade for 5V
MAX221E
• ICL3222E is a Low Power, Pin Compatible Upgrade for 5V
MAX242E, and SP312E
• ICL3232E is a Low Power Upgrade for HIN232E, ICL232
and Pin Compatible Competitor Devices
• RS-232 Compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Manual and Automatic Powerdown Features
The ICL324XE are 3-driver, 5-receiver devices that provide a
complete serial port suitable for laptop or notebook
computers. Both devices also include noninverting alwaysactive receivers for “wake-up” capability.
• Guaranteed Mouse Driveability (ICL324XE Only)
The ICL3221E, ICL3223E and ICL3243E, feature an
automatic powerdown function which powers down the onchip power-supply and driver circuits. This occurs when an
attached peripheral device is shut off or the RS-232 cable is
removed, conserving system power automatically without
changes to the hardware or operating system. These
devices power up again when a valid RS-232 voltage is
applied to any receiver input.
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XXE 3V family.
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
TABLE 1. SUMMARY OF FEATURES
NO. OF NO. OF
PART NUMBER
Tx.
Rx.
NO. OF
MONITOR Rx.
(ROUTB)
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWERDOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3221E
1
1
0
250
Yes
No
Yes
Yes
ICL3222E
2
2
0
250
Yes
No
Yes
No
ICL3223E
2
2
0
250
Yes
No
Yes
Yes
ICL3232E
2
2
0
250
No
No
No
No
ICL3241E
3
5
2
250
Yes
No
Yes
No
ICL3243E
3
5
1
250
No
No
Yes
Yes
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000-2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information
(NOTE 1)
PART NO.
ICL3221ECA
TEMP.
(°C)
Ordering Information
PACKAGE
0 to 70 16 Ld SSOP
PKG.
DWG. #
(NOTE 1)
PART NO.
M16.209
ICL3232ECV-20Z
(Note 2)
ICL3221ECAZ (Note 2) 0 to 70 16 Ld SSOP (Pb-free)
M16.209
ICL3221ECAZA
(Note 2)
0 to 70 16 Ld SSOP (Pb-free)
M16.209
ICL3221ECV
0 to 70 16 Ld TSSOP
TEMP.
(°C)
(Continued)
PACKAGE
0 to 70 20 Ld TSSOP (Pb-free)
PKG.
DWG. #
M20.173
ICL3232EIA
-40 to 85 16 Ld SSOP
M16.209
ICL3232EIAZ (Note 2)
-40 to 85 16 Ld SSOP (Pb-free)
M16.209
M16.173
ICL3232EIB
-40 to 85 16 Ld SOIC
M16.3
ICL3221ECVZ (Note 2) 0 to 70 16 Ld TSSOP (Pb-free)
M16.173
ICL3232EIBZ (Note 2)
-40 to 85 16 Ld SOIC (Pb-free)
M16.3
ICL3221EIA
-40 to 85 16 Ld SSOP
M16.209
ICL3232EIBNZ (Note 2) -40 to 85 16 Ld SOIC (N) (Pb-free) M16.15
ICL3221EIAZ (Note 2)
-40 to 85 16 Ld SSOP (Pb-free)
M16.209
ICL3232EIV-16
-40 to 85 16 Ld TSSOP
M16.173
ICL3221EIV
-40 to 85 16 Ld TSSOP
M16.173
-40 to 85 16 Ld TSSOP (Pb-free)
M16.173
ICL3221EIVZ (Note 2)
-40 to 85 16 Ld TSSOP (Pb-free)
M16.173
ICL3232EIV-16Z
(Note 2)
ICL3232EIV-20
-40 to 85 20 Ld TSSOP
M20.173
ICL3232EIV-20Z
(Note 2)
-40 to 85 20 Ld TSSOP (Pb-free)
M20.173
ICL3222ECA
0 to 70 20 Ld SSOP
M20.209
ICL3222ECAZ (Note 2) 0 to 70 20 Ld SSOP (Pb-free)
M20.209
ICL3222ECP
0 to 70 18 Ld PDIP
E18.3
ICL3222ECV
0 to 70 20 Ld TSSOP
M20.173
ICL3222ECVZ (Note 2) 0 to 70 20 Ld TSSOP (Pb-free)
M20.173
ICL3222EIA
-40 to 85 20 Ld SSOP
M20.209
ICL3222EIAZ (Note 2)
-40 to 85 20 Ld SSOP (Pb-free)
M20.209
ICL3222EIB
-40 to 85 18 Ld SOIC
M18.3
ICL3222EIBZ (Note 2)
-40 to 85 18 Ld SOIC (Pb-free)
M18.3
ICL3222EIV
-40 to 85 20 Ld TSSOP
M20.173
ICL3222EIVZ (Note 2)
-40 to 85 20 Ld TSSOP (Pb-free)
M20.173
ICL3223ECA
0 to 70 20 Ld SSOP
M20.209
ICL3223ECAZ (Note 2) 0 to 70 20 Ld SSOP (Pb-free)
M20.209
ICL3223ECV
M20.173
0 to 70 20 Ld TSSOP
ICL3223ECVZ (Note 2) 0 to 70 20 Ld TSSOP (Pb-free)
M20.173
ICL3223EIA
-40 to 85 20 Ld SSOP
M20.209
ICL3223EIAZ (Note 2)
-40 to 85 20 Ld SSOP (Pb-free)
M20.209
ICL3223EIV
-40 to 85 20 Ld TSSOP
M20.173
ICL3223EIVZ (Note 2)
-40 to 85 20 Ld TSSOP (Pb-free)
M20.173
ICL3232ECA
0 to 70 16 Ld SSOP
M16.209
ICL3241ECA
0 to 70 28 Ld SSOP
M28.209
ICL3241ECAZ (Note 2)
0 to 70 28 Ld SSOP (Pb-free)
M28.209
ICL3241ECB
0 to 70 28 Ld SOIC
M28.3
ICL3241ECBZ (Note 2)
0 to 70 28 Ld SOIC (Pb-free)
M28.3
ICL3241ECV
0 to 70 28 Ld TSSOP
M28.173
ICL3241ECVZ (Note 2)
0 to 70 28 Ld TSSOP (Pb-free)
M28.173
ICL3241EIA
-40 to 85 28 Ld SSOP
M28.209
ICL3241EIAZ (Note 2)
-40 to 85 28 Ld SSOP (Pb-free)
M28.209
ICL3241EIB
-40 to 85 28 Ld SOIC
M28.3
ICL3241EIBZ (Note 2)
-40 to 85 28 Ld SOIC (Pb-free)
M28.3
ICL3241EIV
-40 to 85 28 Ld TSSOP
M28.173
ICL3241EIVZ (Note 2)
-40 to 85 28 Ld TSSOP (Pb-free)
M28.173
ICL3243ECA
0 to 70 28 Ld SSOP
M28.209
ICL3243ECAZ (Note 2)
0 to 70 28 Ld SSOP (Pb-free)
M28.209
ICL3243ECB
0 to 70 28 Ld SOIC
M28.3
ICL3243ECBZ (Note 2)
0 to 70 28 Ld SOIC (Pb-free)
M28.3
ICL3243ECV
0 to 70 28 Ld TSSOP
M28.173
M28.173
M16.209
ICL3243ECVZA
(Note 2)
0 to 70 28 Ld TSSOP (Pb-free)
ICL3232ECAZ (Note 2) 0 to 70 16 Ld SSOP (Pb-free)
ICL3232ECB
M16.3
ICL3243ECVZ (Note 2)
0 to 70 28 Ld TSSOP (Pb-free)
M28.173
ICL3232ECBZ (Note 2) 0 to 70 16 Ld SOIC (Pb-free)
M16.3
ICL3243EIA
-40 to 85 28 Ld SSOP
M28.209
ICL3232ECBN
0 to 70 16 Ld SOIC (N)
M16.15
ICL3243EIAZ (Note 2)
-40 to 85 28 Ld SSOP (Pb-free)
M28.209
ICL3232ECBNZ
(Note 2)
0 to 70 16 Ld SOIC (N) (Pb-free) M16.15
ICL3243EIV
-40 to 85 28 Ld TSSOP
M28.173
ICL3243EIVZ (Note 2)
-40 to 85 28 Ld TSSOP (Pb-free)
M28.173
ICL3232ECV-16
0 to 70 16 Ld TSSOP
M16.173
ICL3232ECV-16Z
(Note 2)
0 to 70 16 Ld TSSOP (Pb-free)
M16.173
ICL3232ECV-20
0 to 70 20 Ld TSSOP
M20.173
0 to 70 16 Ld SOIC
2
NOTES:
1. Most surface mount devices are available on tape and reel; add “-T” to suffix.
2. Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pinouts
ICL3221E (SSOP, TSSOP)
TOP VIEW
16 FORCEOFF
EN 1
ICL3222E (PDIP, SOIC)
TOP VIEW
EN 1
18 SHDN
C1+ 2
15 VCC
C1+ 2
17 VCC
V+ 3
14 GND
V+ 3
16 GND
C1- 4
13 T1OUT
C1- 4
15 T1OUT
C2+ 5
12 FORCEON
C2+ 5
14 R1IN
C2- 6
11 T1IN
C2- 6
13 R1OUT
10 INVALID
V- 7
9 R1OUT
R1IN 8
V- 7
12 T1IN
T2OUT 8
11 T2IN
R2IN 9
ICL3222E (SSOP, TSSOP)
TOP VIEW
20 SHDN
EN 1
C1+ 2
19 VCC
V+ 3
18 GND
10 R2OUT
ICL3223E (SSOP, TSSOP)
TOP VIEW
EN 1
20 FORCEOFF
C1+ 2
19 VCC
V+ 3
18 GND
C1- 4
17 T1OUT
C1- 4
17 T1OUT
C2+ 5
16 R1IN
C2+ 5
16 R1IN
C2- 6
15 R1OUT
C2- 6
15 R1OUT
14 NC
V- 7
V- 7
14 FORCEON
T2OUT 8
13 T1IN
T2OUT 8
13 T1IN
R2IN 9
12 T2IN
R2IN 9
12 T2IN
11 NC
R2OUT 10
ICL3232E (SOIC, SSOP, TSSOP-16)
TOP VIEW
R2OUT 10
11 INVALID
ICL3232E (TSSOP-20)
TOP VIEW
C1+ 1
16 VCC
NC 1
20 NC
V+ 2
15 GND
C1+ 2
19 VCC
V+ 3
18 GND
C1- 3
14 T1OUT
C2+ 4
13 R1IN
C1- 4
17 T1OUT
C2- 5
12 R1OUT
C2+ 5
16 R1IN
V- 6
11 T1IN
C2- 6
15 R1OUT
T2OUT 7
10 T2IN
9 R2OUT
R2IN 8
V- 7
T2OUT 8
R2IN 9
NC 10
3
14 T1IN
13 T2IN
12 R2OUT
11 NC
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pinouts
(Continued)
ICL3241E (SOIC, SSOP, TSSOP)
TOP VIEW
ICL3243E (SOIC, SSOP, TSSOP)
TOP VIEW
C2+ 1
28 C1+
C2+ 1
28 C1+
C2- 2
27 V+
C2- 2
27 V+
V- 3
26 VCC
V- 3
26 VCC
R1IN 4
25 GND
R1IN 4
25 GND
R2IN 5
24 C1-
R2IN 5
24 C1-
R3IN 6
23 EN
R3IN 6
23 FORCEON
R4IN 7
22 SHDN
R4IN 7
22 FORCEOFF
R5IN 8
21 R1OUTB
R5IN 8
21 INVALID
T1OUT 9
20 R2OUTB
T1OUT 9
20 R2OUTB
T2OUT 10
19 R1OUT
19 R1OUT
18 R2OUT
T2OUT 10
T3OUT 11
T3OUT 11
18 R2OUT
T3IN 12
17 R3OUT
T3IN 12
17 R3OUT
T2IN 13
16 R4OUT
T2IN 13
16 R4OUT
T1IN 14
15 R5OUT
T1IN 14
15 R5OUT
Pin Descriptions
PIN
VCC
FUNCTION
System power supply input (3.0V to 5.5V).
V+
Internally generated positive transmitter supply (+5.5V).
V-
Internally generated negative transmitter supply (-5.5V).
GND
Ground connection.
C1+
External capacitor (voltage doubler) is connected to this lead.
C1-
External capacitor (voltage doubler) is connected to this lead.
C2+
External capacitor (voltage inverter) is connected to this lead.
C2-
External capacitor (voltage inverter) is connected to this lead.
TIN
TTL/CMOS compatible transmitter Inputs.
TOUT
RIN
ROUT
ROUTB
INVALID
EN
SHDN
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-232 compatible receiver inputs.
TTL/CMOS level receiver outputs.
TTL/CMOS level, noninverting, always enabled receiver outputs.
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active low receiver enable control; doesn’t disable ROUTB outputs.
Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON
Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
4
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits
ICL3221E
C3 (OPTIONAL CONNECTION, NOTE)
+
15
2
+ C1+
4
C15
+ C2+
6
C2-
C1
0.1µF
C2
0.1µF
T1IN
TTL/CMOS
LOGIC LEVELS
0.1µF
+
+3.3V
R1OUT
VCC
V+
+ C3
0.1µF
V- 7
T1
11
3
C4
+ 0.1µF
13
9
8
T1OUT
R1IN
RS-232
LEVELS
5kΩ
R1
1 EN
FORCEOFF
12
FORCEON
GND
INVALID
16
10
VCC
TO POWER
CONTROL LOGIC
14
NOTE: The negative terminal of C3 can be connected to either VCC or GND
ICL3222E
C3 (OPTIONAL CONNECTION, NOTE)
C1
0.1µF
+
C2
0.1µF
+
T1IN
T2IN
TTL/CMOS
LOGIC LEVELS
+
0.1µF
R1OUT
2
4
5
6
+
+3.3V
17
C1+
VCC
C1C2+
V-
C2-
12
11
7
15
T2
8
14
13
5kΩ
C4
0.1µF
T1OUT
T2OUT
R1IN
RS-232
LEVELS
9
10
1 EN
+ C3
0.1µF
+
T1
R1
R2OUT
3
V+
R2IN
5kΩ
R2
GND
SHDN
18
VCC
16
NOTE: The negative terminal of C3 can be connected to either VCC or GND
5
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits
(Continued)
ICL3223E
+3.3V
+
C1
0.1µF
C2
0.1µF
5
+
6
T1IN
T2IN
TTL/CMOS
LOGIC LEVELS
0.1µF
2
+
4
R1OUT
R2OUT
19
C1+
VCC
C1C2+
C2-
3
+ C3
0.1µF
V- 7
C4
0.1µF
+
V+
T1
13
17
T2
12
8
15
5kΩ
R2
5kΩ
10
1
9
EN
FORCEOFF
14
T2OUT
16
R1
INVALID
FORCEON
T1OUT
R1IN
RS-232
LEVELS
R2IN
20
11
VCC
TO POWER
CONTROL LOGIC
GND
18
ICL3232E
+
C2
0.1µF
+
T2IN
R1OUT
0.1µF
1
C1
0.1µF
T1IN
TTL/CMOS
LOGIC LEVELS
+
3
4
5
11
10
C1+
+
C3 (OPTIONAL CONNECTION, NOTE)
+3.3V
16
VCC
C1C2+
V-
C2T1
2
+ C3
0.1µF
6
C4
0.1µF
+
14
T2
7
13
12
R1
R2OUT
V+
T1OUT
T2OUT
R1IN
RS-232
LEVELS
5kΩ
9
8
R2
R2IN
5kΩ
GND
15
NOTE: The negative terminal of C3 can be connected to either VCC or GND
6
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits
(Continued)
ICL3241E
+3.3V
+
+3.3V
0.1µF
C1
0.1µF
28
+
24
C2
0.1µF
+
T1IN
T2IN
ICL3243E
1
2
C1+
VCC
V+
C1C2+
V-
C2-
T1
14
13
T2
12
T3
27
3
R2OUTB
TTL/CMOS
LOGIC
LEVELS
R1OUT
C2
0.1µF
C4
0.1µF
+
10
11
T2OUT
T1IN
RS-232
LEVELS
T2IN
0.1µF
28
+
24
C1+
26
27
VCC
V+
C11
C2+
+
2
C2-
VT1
14
13
3
C3
0.1µF
C4
0.1µF
+
T1OUT
10
T2OUT
T3
RS-232
LEVELS
11
T3IN
20
+
9
T2
12
T3OUT
T3OUT
20
R2OUTB
19
4
18
R2OUT
16
7
R4OUT
R4
15
RS-232
LEVELS
17
R3IN
EN
5kΩ
R5
R5IN
R5OUT
25
VCC
TO POWER
CONTROL
LOGIC
22
21
RS-232
LEVELS
R4IN
5kΩ
15
GND
7
7
R4
23
SHDN
5kΩ
16
8
R5OUT
6
R3OUT
R4OUT
R2IN
5kΩ
R3
R4IN
5kΩ
5
R2
R3IN
5kΩ
R3
5kΩ
18
6
R3OUT
22
R1IN
R1
TTL/CMOS
LOGIC
LEVELS
R2IN
5kΩ
4
R1OUT
5
17
23
19
R1IN
5kΩ
R2
VCC
C1
0.1µF
T1OUT
21
R1
R2OUT
+ C3
0.1µF
9
T3IN
R1OUTB
+
26
8
5kΩ
R5
R5IN
FORCEON
FORCEOFF
INVALID
GND
25
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Absolute Maximum Ratings
Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT, INVALID. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 3)
Operating Conditions
θJA (°C/W)
18 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
80
16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . .
100
16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . .
115
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
135
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
122
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
145
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
140
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . .
100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC, SSOP, TSSOP - Lead Tips Only)
Temperature Range
ICL32XXECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXEIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C
TEMP
(°C)
MIN
TYP
MAX
UNITS
All RIN Open, FORCEON = GND, FORCEOFF = VCC
(ICL3221E, ICL3223E, ICL3243E Only)
25
-
1.0
10
µA
Supply Current, Powerdown
FORCEOFF = SHDN = GND (Except ICL3232E)
25
-
1.0
10
µA
Supply Current,
Automatic Powerdown Disabled
VCC = 3.0V, ICL3241,
All Outputs Unloaded,
FORCEON = FORCEOFF = ICL3243
SHDN = VCC
VCC = 3.15V, ICL3221,
ICL3222, ICL3223, ICL3232
25
-
0.3
1.0
mA
25
-
0.3
1.0
mA
PARAMETER
TEST CONDITIONS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low
TIN, FORCEON, FORCEOFF, EN, SHDN
Full
-
-
0.8
V
Input Logic Threshold High
TIN, FORCEON,
FORCEOFF, EN, SHDN
VCC = 3.3V
Full
2.0
-
-
V
VCC = 5.0V
Full
2.4
-
-
V
Input Leakage Current
TIN, FORCEON, FORCEOFF, EN, SHDN
Full
-
±0.01
±1.0
µA
Output Leakage Current
(Except ICL3232E)
FORCEOFF = GND or EN = VCC
Full
-
±0.05
±10
µA
Output Voltage Low
IOUT = 1.6mA
Full
-
-
0.4
V
Output Voltage High
IOUT = -1.0mA
Full
-
V
VCC -0.6 VCC -0.1
AUTOMATIC POWERDOWN (ICL3221E, ICL3223E, ICL3243E Only, FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
Enable Transmitters
ICL32XXE Powers Up (See Figure 6)
Full
-2.7
-
2.7
V
Receiver Input Thresholds to
Disable Transmitters
ICL32XXE Powers Down (See Figure 6)
Full
-0.3
-
0.3
V
INVALID Output Voltage Low
IOUT = 1.6mA
Full
-
-
0.4
V
INVALID Output Voltage High
IOUT = -1.0mA
Full
VCC-0.6
-
-
V
8
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Electrical Specifications
Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C (Continued)
TEMP
(°C)
MIN
TYP
MAX
UNITS
Receiver Threshold to Transmitters
Enabled Delay (tWU)
25
-
100
-
µs
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25
-
1
-
µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25
-
30
-
µs
PARAMETER
TEST CONDITIONS
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
Input Threshold High
25
-25
-
25
V
VCC = 3.3V
25
0.6
1.2
-
V
VCC = 5.0V
25
0.8
1.5
-
V
VCC = 3.3V
25
-
1.5
2.4
V
VCC = 5.0V
25
-
1.8
2.4
V
Input Hysteresis
25
-
0.5
-
V
Input Resistance
25
3
5
7
kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing
All Transmitter Outputs Loaded with 3kΩ to Ground
Full
±5.0
±5.4
-
V
Output Resistance
VCC = V+ = V- = 0V, Transmitter Output = ±2V
Full
300
10M
-
Ω
Full
-
±35
±60
mA
Full
-
-
±25
µA
T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kΩ
to GND, T1OUT and T2OUT Loaded with 2.5mA Each
Full
±5
-
-
V
Maximum Data Rate
RL = 3kΩ, CL = 1000pF, One Transmitter Switching
Full
250
500
-
kbps
Receiver Propagation Delay
Receiver Input to Receiver
Output, CL = 150pF
tPHL
25
-
0.15
-
µs
tPLH
25
-
0.15
-
µs
Output Short-Circuit Current
VOUT = ±12V, VCC = 0V or 3V to 5.5V,
Automatic Powerdown or FORCEOFF = SHDN = GND
Output Leakage Current
MOUSE DRIVEABILITY (ICL324XE Only)
Transmitter Output Voltage
(See Figure 9)
TIMING CHARACTERISTICS
Receiver Output Enable Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
Receiver Output Disable Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
Transmitter Skew
tPHL - tPLH (Note 4)
25
-
100
-
ns
Receiver Skew
tPHL - tPLH
25
-
50
-
ns
Transition Region Slew Rate
CL = 150pF to 2500pF
VCC = 3.3V,
RL = 3kΩ to 7kΩ,
CL = 150pF to 1000pF
Measured from 3V to -3V or
-3V to 3V
25
4
-
30
V/µs
25
6
-
30
V/µs
Human Body Model
25
-
±15
-
kV
IEC61000-4-2 Contact Discharge
25
-
±8
-
kV
IEC61000-4-2 Air Gap Discharge
25
-
±15
-
kV
Human Body Model
25
-
±2
-
kV
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN)
All Other Pins
NOTE:
4. Transmitter skew is measured at the transmitter zero crossing points.
9
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Detailed Description
ICL32XXE interface ICs operate from a single +3V to +5.5V
supply, guarantee a 250kbps minimum data rate, require
only four small external 0.1µF capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections:
charge pump, transmitters and receivers.
Charge-Pump
Intersil’s new ICL32XXE family utilizes regulated on-chip
dual charge pumps as voltage doublers, and voltage
inverters to generate ±5.5V transmitter supplies from a VCC
supply as low as 3.0V. This allows these devices to maintain
RS-232 compliant output levels over the ±10% tolerance
range of 3.3V powered systems. The efficient on-chip power
supplies require only four small, external 0.1µF capacitors
for the voltage doubler and inverter functions at VCC = 3.3V.
See the “Capacitor Selection” section, and Table 3 for
capacitor recommendations for other operating conditions.
The charge pumps operate discontinuously (i.e., they turn off
as soon as the V+ and V- supplies are pumped up to the
nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Except for the ICL3232E, all transmitter outputs disable and
assume a high impedance state when the device enters the
powerdown mode (see Table 2). These outputs may be
driven to ±12V when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 900kbps.
Transmitter inputs float if left unconnected, and may cause
ICC increases. Connect unused inputs to GND for the best
performance.
Receivers
All the ICL32XXE devices contain standard inverting
receivers that three-state (except for the ICL3232E) via the
EN or FORCEOFF control lines. Additionally, the two
ICL324XE products include noninverting (monitor) receivers
(denoted by the ROUTB label) that are always active,
regardless of the state of any control lines. All the receivers
convert RS-232 signals to CMOS output levels and accept
inputs up to ±25V while presenting the required 3kΩ to 7kΩ
input impedance (see Figure 1) even if the power is off
(VCC = 0V). The receivers’ Schmitt trigger input stage uses
hysteresis to increase noise immunity and decrease errors
due to slow input signal transitions.
10
The ICL3221E, ICL3222E, ICL3223E, ICL3241E inverting
receivers disable only when EN is driven high. ICL3243E
receivers disable during forced (manual) powerdown, but not
during automatic powerdown (see Table 2).
ICL3241E and ICL3243E monitor receivers remain active
even during manual powerdown and forced receiver disable,
making them extremely useful for Ring Indicator monitoring.
Standard receivers driving powered down peripherals must be
disabled to prevent current flow through the peripheral’s
protection diodes (see Figures 2 and 3). This renders them
useless for wake up functions, but the corresponding monitor
receiver can be dedicated to this task as shown in Figure 3.
VCC
RXIN
-25V ≤ VRIN ≤ +25V
RXOUT
5kΩ
GND ≤ VROUT ≤ VCC
GND
FIGURE 1. INVERTING RECEIVER CONNECTIONS
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at VCC = 5.5V, during normal operation (not in
powerdown mode). This is considerably less than the 5mA
to 11mA current required by comparable 5V RS-232 devices,
allowing users to reduce system power simply by switching
to this new family.
Pin Compatible Replacements for 5V Devices
The ICL3221E, ICL3222E, ICL3232E are pin compatible
with existing 5V RS-232 transceivers - see the Features
section on the front page for details.
This pin compatibility coupled with the low ICC and wide
operating supply range, make the ICL32XXE potential lower
power, higher performance drop-in replacements for existing
5V applications. As long as the ±5V RS-232 output swings
are acceptable, and transmitter input pull-up resistors aren’t
required, the IICL32XXE should work in most 5V
applications.
When replacing a device in an existing 5V application, it is
acceptable to terminate C3 to VCC as shown on the Typical
Operating Circuit. Nevertheless, terminate C3 to GND if
possible, as slightly better performance results from this
configuration.
Powerdown Functionality
(Except ICL3232E)
The already low current requirement drops significantly
when the device enters powerdown mode. In powerdown,
supply current drops to 1µA, because the on-chip charge
pump turns off (V+ collapses to VCC, V- collapses to GND),
and the transmitter outputs three-state. Inverting receiver
outputs may or may not disable in powerdown; refer to
Table 2 for details. This micro-power mode makes these
devices ideal for battery powered and portable applications.
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Software Controlled (Manual) Powerdown
The ICL3221E, ICL3223E, and ICL3243E utilize a two pin
approach where the FORCEON and FORCEOFF inputs
determine the IC’s mode. For always enabled operation,
FORCEON and FORCEOFF are both strapped high. To
switch between active and powerdown modes, under logic
or software control, only the FORCEOFF input need be
driven. The FORCEON state isn’t critical, as FORCEOFF
dominates over FORCEON. Nevertheless, if strictly manual
control over powerdown is desired, the user must strap
FORCEON high to disable the automatic powerdown
circuitry. ICL3243E inverting (standard) receiver outputs also
disable when the device is in manual powerdown, thereby
eliminating the possible current path through a shutdown
peripheral’s input protection diode (see Figures 2 and 3).
Most devices in the ICL32XXE family provide pins that allow
the user to force the IC into the low power, standby state.
On the ICL3222E and ICL3241E, the powerdown control is
via a simple shutdown (SHDN) pin. Driving this pin high
enables normal operation, while driving it low forces the IC
into its powerdown state. Connect SHDN to VCC if the
powerdown function isn’t needed. Note that all the receiver
outputs remain enabled during shutdown (see Table 2). For
the lowest power consumption during powerdown, the
receivers should also be disabled by driving the EN input
high (see next section, and Figures 2 and 3).
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
RECEIVER
INPUT?
FORCEOFF
(NOTE 5)
ROUTB
OR SHDN FORCEON
EN
TRANSMITTER RECEIVER
INVALID
INPUT
INPUT
INPUT
OUTPUTS
OUTPUTS OUTPUTS OUTPUT
MODE OF OPERATION
ICL3222E, ICL3241E
N/A
L
N/A
L
High-Z
Active
Active
N/A
Manual Powerdown
N/A
L
N/A
H
High-Z
High-Z
Active
N/A
Manual Powerdown w/Rcvr. Disabled
N/A
H
N/A
L
Active
Active
Active
N/A
Normal Operation
N/A
H
N/A
H
Active
High-Z
Active
N/A
Normal Operation w/Rcvr. Disabled
ICL3221E, ICL3223E
No
H
H
L
Active
Active
N/A
L
Normal Operation
(Auto Powerdown Disabled)
No
H
H
H
Active
High-Z
N/A
L
Yes
H
L
L
Active
Active
N/A
H
Yes
H
L
H
Active
High-Z
N/A
H
No
H
L
L
High-Z
Active
N/A
L
No
H
L
H
High-Z
High-Z
N/A
L
Yes
L
X
L
High-Z
Active
N/A
H
Manual Powerdown
Yes
L
X
H
High-Z
High-Z
N/A
H
Manual Powerdown w/Rcvr. Disabled
No
L
X
L
High-Z
Active
N/A
L
Manual Powerdown
No
L
X
H
High-Z
High-Z
N/A
L
Manual Powerdown w/Rcvr. Disabled
No
H
H
N/A
Active
Active
Active
L
Normal Operation
(Auto Powerdown Disabled)
Yes
H
L
N/A
Active
Active
Active
H
Normal Operation
(Auto Powerdown Enabled)
No
H
L
N/A
High-Z
Active
Active
L
Powerdown Due to Auto Powerdown
Logic
Yes
L
X
N/A
High-Z
High-Z
Active
H
Manual Powerdown
No
L
X
N/A
High-Z
High-Z
Active
L
Manual Powerdown
Normal Operation
(Auto Powerdown Enabled)
Powerdown Due to Auto Powerdown
Logic
ICL3243E
NOTE:
5. Applies only to the ICL3241E and ICL3243E.
11
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
The INVALID output always indicates whether or not a valid
RS-232 signal is present at any of the receiver inputs (see
Table 2), giving the user an easy way to determine when the
interface block should power down. In the case of a
disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic
then uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID switches high, and the power management
logic wakes up the interface block. INVALID can also be
used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to
GND (as in the case of a powered down driver). Connecting
FORCEOFF and FORCEON together disables the
automatic powerdown feature, enabling them to function as
a manual SHUTDOWN input (see Figure 4).
VCC
CURRENT
FLOW
VOUT = VCC
Rx
POWERED
DOWN
UART
Tx
SHDN = GND
GND
FORCEON
INVALID
ICL3221E,
ICL3223E,
ICL3243E
I/O
UART
CPU
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs. A
mouse, or other application, may need more time to wake up
from shutdown. If automatic powerdown is being utilized, the
RS-232 device will reenter powerdown if valid receiver levels
aren’t reestablished within 30µs of the ICL32XXE powering
up. Figure 5 illustrates a circuit that keeps the ICL32XXE
from initiating automatic powerdown for 100ms after
powering up. This gives the slow-to-wake peripheral circuit
time to reestablish valid RS-232 output levels.
VCC
VCC
FORCEOFF
PWR
MGT
LOGIC
OLD
RS-232 CHIP
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
POWER
MANAGEMENT
UNIT
MASTER POWERDOWN LINE
0.1µF
FORCEOFF
VCC
FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR
100ms AFTER FORCED POWERUP
ICL324XE
Automatic Powerdown
(ICL3221E, ICL3223E, ICL3243E Only)
VCC
R2OUTB
RX
POWERED
DOWN
UART
VOUT = HI-Z
R2OUT
TX
R2IN
T1IN
T1OUT
FORCEOFF = GND
OR SHDN = GND, EN = VCC
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
12
FORCEON
ICL3221E, ICL3223E, ICL3243E
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
1MΩ
Even greater power savings is available by using the
devices which feature an automatic powerdown function.
When no valid RS-232 voltages (see Figure 6) are sensed
on any receiver input for 30µs, the charge pump and
transmitters powerdown, thereby reducing supply current to
1µA. Invalid receiver levels occur whenever the driving
peripheral’s outputs are shut off (powered down) or when the
RS-232 interface cable is disconnected. The ICL32XXE
powers back up whenever it detects a valid RS-232 voltage
level on any receiver input. This automatic powerdown
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
feature provides additional system power savings without
changes to the existing operating system.
2.7V
VALID RS-232 LEVEL - ICL32XXE IS ACTIVE
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
0.3V
INVALID LEVEL - POWERDOWN OCCURS AFTER 30µs
-0.3V
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
Several devices also feature an EN input to control the
receiver outputs. Driving EN high disables all the inverting
(standard) receiver outputs placing them in a high
impedance state. This is useful to eliminate supply current,
due to a receiver output forward biasing the protection diode,
when driving the input of a powered down (VCC = GND)
peripheral (see Figure 2). The enable input has no effect on
transmitter nor monitor (ROUTB) outputs.
Capacitor Selection
-2.7V
VALID RS-232 LEVEL - ICL32XXE IS ACTIVE
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
Automatic powerdown operates when the FORCEON input
is low, and the FORCEOFF input is high. Tying FORCEON
high disables automatic powerdown, but manual powerdown
is always available via the overriding FORCEOFF input.
Table 2 summarizes the automatic powerdown functionality.
Devices with the automatic powerdown feature include an
INVALID output signal, which switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (see Figure 7). INVALID switches high 1µs
after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
powerdown, or forced on), so it is also useful for systems
employing manual powerdown circuitry. When automatic
powerdown is utilized, INVALID = 0 indicates that the
ICL32XXE is in powerdown mode.
INVALID
} REGION
RECEIVER
INPUTS
Receiver ENABLE Control
(ICL3221E, ICL3222E, ICL3223E, ICL3241E Only)
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C2, C3, and C4 can be
increased without increasing C1’s value, however, do not
increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
VCC
(V)
C1
(µF)
C2, C3, C4
(µF)
3.0 to 3.6
0.1
0.1
4.5 to 5.5
0.047
0.33
3.0 to 5.5
0.1
0.47
Power Supply Decoupling
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
VCC
0
tINVL
tINVH
PWR UP
AUTOPWDN
V+
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
VCC
ICL32XXE transmitter outputs meet RS-562 levels (±3.7V),
at full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure interoperability with RS-232 devices.
0
V-
FIGURE 7. AUTOMATIC POWERDOWN AND INVALID
TIMING DIAGRAMS
The time to recover from automatic powerdown mode is
typically 100µs.
13
Transmitter Outputs when Exiting
Powerdown
Figure 8 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
5V/DIV
FORCEOFF
loads in parallel with 1000pF, at 120kbps. Figure 12 shows
the loopback results for a single transmitter driving 1000pF
and an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
VCC
T1
+
0.1µF
+
C1
2V/DIV
+
C2
C1+
VCC
C1-
ICL32XXE
V+
+
C3
V-
C2+
C4
+
C2-
T2
TIN
VCC = +3.3V
C1 - C4 = 0.1µF
TOUT
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
EN
VCC
Mouse Driveability
The ICL3241E and ICL3243E have been specifically
designed to power a serial mouse while operating from low
voltage supplies. Figure 9 shows the transmitter output
voltages under increasing load current. The on-chip
switching regulator ensures the transmitters will supply at
least ±5V during worst case conditions (15mA for paralleled
V+ transmitters, 7.3mA for single V- transmitter). The
Automatic Powerdown feature does not work with a mouse,
so FORCEOFF and FORCEON should be connected to VCC.
1000pF
RIN
ROUT
TIME (20µs/DIV)
5K
SHDN OR
FORCEOFF
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
5V/DIV
T1IN
T1OUT
TRANSMITTER OUTPUT VOLTAGE (V)
6
5
VOUT+
4
3
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
VCC = 3.0V
2
1
T1
0
5µs/DIV
VOUT+
-1
FIGURE 11. LOOPBACK TEST AT 120kbps
T2
-2
ICL3241E, ICL3243E
-3
VCC
-4
VOUT -
T3
5V/DIV
VOUT -
-5
-6
T1IN
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT PER TRANSMITTER (mA)
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL VOUT+ CURRENT)
T1OUT
High Data Rates
The ICL32XXE maintain the RS-232 ±5V minimum
transmitter output voltages even at high data rates.
Figure 10 details a transmitter loopback test circuit, and
Figure 11 illustrates the loopback test result at 120kbps. For
this test, all transmitters were simultaneously driving RS-232
14
R1OUT
VCC = +3.3V
C1 - C4 = 0.1µF
2µs/DIV
FIGURE 12. LOOPBACK TEST AT 250kbps
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX
inputs, but ICL32XX outputs do not reach the minimum VIH for
these logic families. See Table 4 for more information.
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM POWERSUPPLY VOLTAGE VCC SUPPLY
(V)
VOLTAGE (V)
3.3
3.3
5
5
5
3.3
COMPATIBILITY
Compatible with all CMOS
families.
Compatible with all TTL and
CMOS logic families.
Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with
AC, HC, and CD4000 CMOS
inputs.
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32XXE family incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
Typical Performance Curves
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an IC’s ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
VCC = 3.3V, TA = 25°C
25
VOUT+
4
2
SLEW RATE (V/ms)
TRANSMITTER OUTPUT VOLTAGE (V)
6
1 TRANSMITTER AT 250kbps
1 OR 2 TRANSMITTERS AT 30kbps
0
-2
20
15
-SLEW
+SLEW
10
VOUT -
-4
-6
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
15
5
0
1000
2000
3000
LOAD CAPACITANCE (pF)
4000
5000
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Performance Curves
VCC = 3.3V, TA = 25°C (Continued)
45
45
ICL3221E
35
250kbps
30
25
20
120kbps
15
10
20kbps
250kbps
35
30
25
120kbps
20
15
20kbps
10
5
5
0
ICL3222E, ICL3223E, ICL3232E
40
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
40
0
1000
2000
3000
4000
0
5000
0
1000
2000
3000
5000
FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
45
3.5
NO LOAD
ALL OUTPUTS STATIC
ICL324XE
40
3.0
250kbps
ICL3221E, ICL3222E, ICL3223E, ICL3232E
35
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
4000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
30
120kbps
25
20
20kbps
15
2.5
2.0
1.5
1.0
ICL324XE
0.5
ICL324XE
10
0
2000
1000
3000
4000
LOAD CAPACITANCE (pF)
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
5000
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221E: 286
ICL3222E: 338
ICL3223E: 357
ICL3232E: 296
ICL324XE: 464
PROCESS:
Si Gate CMOS
16
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Dual-In-Line Plastic Packages (PDIP)
E18.3 (JEDEC MS-001-BC ISSUE D)
N
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.845
0.880
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.355
22.35
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
L
0.115
N
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
0.204
21.47
18
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
18
6
10.92
7
3.81
4
9
Rev. 2 11/03
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3
may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
17
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INCHES
INDEX
AREA
H
0.25(0.010) M
B M
SYMBOL
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
B
0.014
0.019
0.35
0.49
9
C
0.007
0.010
0.19
0.25
-
D
0.386
0.394
9.80
10.00
3
E
0.150
0.157
3.80
4.00
4
e
µα
A1
MIN
0.050 BSC
1.27 BSC
-
H
0.228
0.244
5.80
6.20
-
h
0.010
0.020
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
16
0o
16
7
8o
Rev. 1 02/02
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
18
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
B M
0.05(0.002)
-A-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.043
-
1.10
-
A1
3
L
A
D
-C-
e
α
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
c
0.10(0.004)
C A M
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
D
0.193
0.201
4.90
5.10
3
E1
0.169
0.177
4.30
4.50
4
e
A2
B S
0.002
0.246
L
0.020
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
0.006
0.026 BSC
E
N
NOTES:
MILLIMETERS
0.65 BSC
0.256
6.25
0.028
0.50
16
0o
6.50
0.70
16
8o
0o
6
7
8o
Rev. 1 2/02
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
19
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
N
INDEX
AREA
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
2
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
INCHES
E
-B-
1
B M
A
D
-C-
µα
e
A1
B
0.25(0.010) M
L
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.233
0.255
5.90
6.50
3
E
0.197
0.220
5.00
5.60
4
e
A2
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.026 BSC
H
0.292
L
0.022
N
α
NOTES:
MILLIMETERS
0.65 BSC
0.322
7.40
0.037
0.55
16
0o
-
8.20
6
0.95
16
8o
0o
7
8o
Rev. 2
3/95
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
20
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
INDEX
AREA
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
µα
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
N
α
NOTES:
MILLIMETERS
16
0o
1.27
16
8o
0o
6
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
21
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M18.3 (JEDEC MS-013-AB ISSUE C)
N
INDEX
AREA
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
0.25(0.010) M
H
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4469
0.4625
11.35
11.75
3
E
0.2914
0.2992
7.40
7.60
4
e
µα
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
N
α
NOTES:
MILLIMETERS
18
0o
1.27
18
8o
0o
6
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
22
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
M20.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
L
A
D
-C-
α
e
A1
b
0.10(0.004) M
0.25
0.010
SEATING PLANE
A2
c
0.10(0.004)
C A M
B S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.252
0.260
6.40
6.60
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
E
0.246
L
0.0177
N
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
α
0.65 BSC
0.256
6.25
0.0295
0.45
20
0o
6.50
0.75
20
8o
0o
6
7
8o
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
23
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
M20.209 (JEDEC MO-150-AE ISSUE B)
N
INDEX
AREA
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
E
2
3
0.25
0.010
SEATING PLANE
-A-
INCHES
GAUGE
PLANE
-B1
B M
A
D
-C-
α
e
A1
B
0.25(0.010) M
L
MIN
MAX
A2
C
B S
MAX
NOTES
A
0.068
0.078
1.73
1.99
0.002
0.008’
0.05
0.21
A2
0.066
0.070’
1.68
1.78
B
0.010’
0.015
0.25
0.38
C
0.004
0.008
0.09
0.20’
D
0.278
0.289
7.07
7.33
3
E
0.205
0.212
5.20’
5.38
4
0.026 BSC
0.301
0.311
7.65
7.90’
L
0.025
0.037
0.63
0.95
8 deg.
0 deg.
N
20
0 deg.
9
0.65 BSC
H
α
NOTES:
MILLIMETERS
MIN
A1
e
0.10(0.004)
C A M
SYMBOL
6
20
7
8 deg.
Rev. 3 11/02
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
24
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
M28.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
SEATING PLANE
L
A
D
-C-
α
e
A1
b
0.10(0.004) M
0.25
0.010
A2
c
0.10(0.004)
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
28
0o
28
7
8o
Rev. 0 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
25
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
N
INDEX
AREA
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
H
0.25(0.010) M
2
GAUGE
PLANE
3
0.25
0.010
SEATING PLANE
-A-
INCHES
E
-B-
1
B M
A
D
-C-
µα
e
A1
B
0.25(0.010) M
L
C
0.10(0.004)
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.390
0.413
9.90
10.50
3
E
0.197
0.220
5.00
5.60
4
e
A2
B S
NOTES:
0.026 BSC
H
0.292
L
0.022
N
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MILLIMETERS
0.65 BSC
0.322
7.40
0.037
0.55
28
0o
8.20
0.95
28
8o
0o
6
7
8o
Rev. 1 3/95
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.20mm (0.0078 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
26
FN4910.18
March 8, 2005
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
1.27 BSC
H
0.394
h
0.01
0.029
L
0.016
0.050
8o
0o
N
α
NOTES:
MAX
A1
e
µα
MIN
0.419
-
0.25
0.75
5
0.40
1.27
6
28
0o
-
10.65
10.00
28
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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27
FN4910.18
March 8, 2005