ICS650-27 Networking Clock Source Description Features The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-27 outputs all have zero ppm synthesis error. • Packaged in 20-pin (150 mil) SSOP (QSOP) • Available in Pb (lead) free package • 12.5 MHz or 25 MHz fundamental crystal or clock The ICS650-27 is pin compatible and functionally equivalent to the ICS650-07. It is a performance upgrade and is recommended for all new 3.3V designs. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. • • • • • • • • • input Six output clocks with selectable frequencies SDRAM frequencies of 67, 83, 100, and 133 MHz Buffered crystal reference output Zero ppm synthesis error in all clocks Ideal for PMC-Sierra’s ATM switch chips Full CMOS output swing with 25 mA output drive capability at TTL levels Advanced, low-power, sub-micron CMOS process Operating voltage of 3.3 V Industrial temperature only See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks. Block Diagram VDD 2 CLKA1 ACS1:0 BCS1:0 2 CLKA2 /2 2 CLKB1 Clock Synthesis and Control Circuitry CCS CLKB2 /2 CLKC1 CLKC2 X1/ICLK Clock Buffer/ Crystal Oscillator 25 or 12.5 MHz cyrstal or clock X2 REFOUT 2 OE (all outputs) GND 1 MDS 650-27 D Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 070505 ● tel (408) 297-1201 ● www.icst.com ICS650-27 Networking Clock Source Pin Assignment ASC0 1 20 BCS1 X2 2 19 BCS0 X1/ICLK 3 18 REFOUT VDD 4 17 CLKA1 ASC1 5 16 VDD GND 6 15 OE CLKC1 7 14 GND CLKC2 8 13 CLKA2 CLKB2 9 12 DC CLKB1 10 11 CCS 20-pin (150 mil) SSOP Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 ACS0 Input A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3. 2 X2 Input Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock input. 3 X1/ICLK Input Crystal connection. Connect to a fundamental crystal or clock input. 4 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 16. 5 ACS1 Input A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal pull-up. 6 GND Power Connect to ground. 7 CLKC1 Output Output Clock C1. Depends on setting of CCS per table on page 3. 8 CLKC2 Output Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1. 9 CLKB2 Output Output Clock B2. Depends on setting of BCS1, 0 per table on page 3. 10 CLKB1 Output Output Clock B1. Depends on setting of BCS1, 0 per table on page 3. 11 CCS Input Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3. 12 DC - 13 CLKA2 Output Output Clock A2. Depends on setting of ACS1, 0 per table on page 3. Don’t connect. Do not connect anything to this pin. 14 GND Power Connect to ground. 15 OE Input Output enable. Tri-states all outputs when low. Internal pull-up. 16 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 4. 17 CLKA1 Output Output Clock A1. Depends on setting of ACS1, 0 per table on page 3. 18 REFOUT Output Buffered reference clock output. Same frequency as crystal or clock input. 19 BCS0 Input B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3. 20 BCS1 Input B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal pull-up. 2 MDS 650-27 D Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 070505 ● tel (408) 297-1201 ● www.icst.com ICS650-27 Networking Clock Source For a 25 MHz fundamental crystal or clock input, the following four tables apply: A Clocks Select Table (outputs in MHz) B Clocks Select Table (outputs in MHz) ASC1 ASC0 CLKA1 CLKA2 BSC1 BSC0 CLKB1 CLKB2 0 0 100 off (low) 0 0 Test Test 0 M Test Test 0 M 66.6667 33.3333 0 1 75 off (low) 0 1 100 50 1 0 33.3333 16.6667 1 0 83.3333 41.6667 1 M Test Test 1 M Test Test 1 1 66.6667 33.3333 1 1 133.3333 66.6667 C Clocks Select Table (outputs in MHz) Reference Output Clock Frequency (in MHz) CCS CLKC1 CLKC2 REFOUT 0 125 125 25 M Test Test 1 75 75 For a 12.5 MHz fundamental crystal or clock input, the following four tables apply: A Clocks Select Table (outputs in MHz) B Clocks Select Table (outputs in MHz) ASC1 ASC0 CLKA1 CLKA2 BSC1 BSC0 CLKB1 CLKB2 0 0 50 off (low) 0 0 Test Test 0 M Test Test 0 M 33.3333 16.6667 0 1 37.5 off (low) 0 1 50 25 1 0 16.6667 8.3333 1 0 41.6667 20.8333 1 M Test Test 1 M Test Test 1 1 33.3333 16.6667 1 1 66.6667 33.3333 C Clocks Select Table (outputs in MHz) Reference Output Clock Frequency (in MHz) CCS CLKC1 CLKC2 REFOUT 0 62.5 62.5 12.5 M Test Test 1 37.5 37.5 0 = connect directly to GND M = leave unconnected (automatically self biases to VDD/2) 1 = connect directly to VDD 3 MDS 650-27 D Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 070505 ● tel (408) 297-1201 ● www.icst.com ICS650-27 Networking Clock Source External Components Crystal Information The ICS650-27 requires a minimum number of external components for proper operation. Decoupling Capacitor Decoupling capacitors of 0.01µF must be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 In the equation, CL is the crystal load capacitance. So, for a crystal with a 16pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-27. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 175°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature -40 Power Supply Voltage (measured in respect to GND) +3.0 Max. Units +85 °C +3.3 +3.6 V 4 MDS 650-27 D Integrated Circuit Systems, Inc. Typ. ● 525 Race Street, San Jose, CA 95126 Revision 070505 ● tel (408) 297-1201 ● www.icst.com ICS650-27 Networking Clock Source DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Operating Voltage VDD Input High Voltage VIH X1 pin only, CLK input Input Low Voltage VIL X1 pin only, CLK input Input High Voltage VIH all tri-level type inputs Input Low Voltage VIL all tri-level type inputs Input High Voltage VIH all other inputs Input Low Voltage VIL all other inputs Output High Voltage VOH IOH = -25 mA Output Low Voltage VOL IOL = 25mA Output High Voltage, CMOS level VOH IOH = -8 mA Min. Typ. Max. Units 3.0 3.3 3.6 V VDD/2+1 VDD/2 VDD/2 V VDD/2-1 VDD-0.5 V V 0.5 2 V V 0.8 2.4 V V 0.8 VDD-0.4 V V Operating Supply Current IDD No Load 50 mA Short Circuit Current IOS Each output ±50 mA Internal pull-up resistor RPU BCS1, OE pins 510 kΩ ACSI pin 120 kΩ 20 Ω Nominal output impedance ZOUT AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V±10%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Input Frequency Min. Typ. Max. Units 10 12.5 or 25 27 MHz Output Rise Time tOR 0.8 to 2.0 V, Note 1 1.5 ns Output Fall Time tOF 2.0 to 0.8 V, Note 1 1.5 ns 60 % 0 ppm Output Clock Duty Cycle At VDD/2, Note 1 40 Frequency Error All clocks Absolute Jitter, short term Variation from mean, Note 1 50 ±150 ps Note 1: Measured with 15 pF load Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient θJA Still air 135 °C/W θJA 1 m/s air flow 93 °C/W θJA 3 m/s air flow 78 °C/W 60 °C/W Thermal Resistance Junction to Case θJC Min. Typ. Max. Units 5 MDS 650-27 D Integrated Circuit Systems, Inc. Conditions ● 525 Race Street, San Jose, CA 95126 Revision 070505 ● tel (408) 297-1201 ● www.icst.com ICS650-27 Networking Clock Source Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Symbol E1 Min A A1 A2 b C D E E1 e L α E INDEX AREA 1 2 D Inches Max Min 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° Max .053 .069 .0040 .010 -.059 0.008 0.012 .007 .010 .337 .344 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° A A2 A1 c -Ce SEATING PLANE b L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS650R-27I ICS650R-27IT ICS650R-27ILF ICS650R-27ILFT ICS650R-27I ICS650R-27I 650R-27ILF 650R-27ILF Tubes Tape and Reel Tubes Tape and Reel 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP -40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 650-27 D Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 070505 ● tel (408) 297-1201 ● www.icst.com