PRELIMINARY Integrated Circuit Systems, Inc. ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS844051I is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from ICS. The ICS844051I can synthesize 10 Gigabit Ethernet, SONET, or Serial ATA reference clock frequencies with the appropriate choice of crystal and output divider. The ICS844051I has excellent phase jitter performance and is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One Differential LVDS output ICS • Crystal oscillator interface designed for 18pF parallel resonant crystals (18.125MHz - 23.4375MHz) • Output frequency range: 145MHz - 187.5MHz and 72.5MHz - 93.75MHz • VCO range: 580MHz - 750MHz • RMS phase jitter @156.25MHz (1.875MHz - 20MHz): 0.45ps (typical) • 3.3V or 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages FREQUENCY TABLE Inputs Crystal Frequency (MHz) FREQ_SEL Output Frequency (MHz) 20.141601 0 161.132812 20.141601 1 80.566406 19.53125 0 156.25 19.53125 1 78.125 19.44 0 155.52 19.44 1 77.76 18.75 0 15 0 18.75 1 75 BLOCK DIAGRAM FREQ_SEL PIN ASSIGNMENT Pulldown XTAL_IN OSC XTAL_OUT Phase Detector 0 ÷4 (default) 1 ÷8 VCO Q nQ VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ FREQ_SEL ICS844051I ÷32 (fixed) 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844051CGI www.icst.com/products/hiperclocks.html REV. A NOVEMBER 23, 2005 1 PRELIMINARY ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR Integrated Circuit Systems, Inc. TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Analog supply pin. 2 Power 5 GND XTAL_OUT, XTAL_IN FREQ_SEL Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Frequency select pin. 6, 7 nQ, Q Output Differential clock outputs. LVDS interface levels. 8 VDD Power Power supply pin. 3, 4 Type Description Input Input Pullup NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ 844051CGI www.icst.com/products/hiperclocks.html 2 REV. A NOVEMBER 23, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V NOTE: Stresses beyond those listed under Absolute Inputs, VI -0.5V to VDD + 0.5 V Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 8 mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 2.375 2.5 2.625 V 2.375 2.5 2.625 VDDA Analog Supply Voltage IDD Power Supply Current 95 mA V IDDA Analog Supply Current 8 mA TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Maximum Units VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5 1.7 VDD + 0.3 V VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.465V or 2.625V IIL Input Low Current VDD = 3.465V or 2.625V, VIN = 0V 844051CGI Typical VDD = 3.3V -0.3 0.8 V VDD = 2.5 -0.3 0.7 V 5 µA www.icst.com/products/hiperclocks.html 3 -150 µA REV. A NOVEMBER 23, 2005 PRELIMINARY ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR Integrated Circuit Systems, Inc. TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV Δ VOD VOD Magnitude Change 400 mV VOS Offset Voltage 1.4 V Δ VOS VOS Magnitude Change 50 mV TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV Δ VOD VOD Magnitude Change 400 mV VOS Offset Voltage 1.15 V Δ VOS VOS Magnitude Change 40 mV TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 23.4375 MHz Fundamental Frequency 18.125 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time t jit(Ø) t R / tF Test Conditions Minimum 156.25MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. Typical 156.25 MHz 0.45 ps 300 ps 50 % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time t jit(Ø) t R / tF Test Conditions Minimum 156.25MHz @ Integration Range: 1.875MHz - 20MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. 844051CGI www.icst.com/products/hiperclocks.html 4 Typical Maximum Units 156.25 MHz 0.45 ps 300 ps 50 % REV. A NOVEMBER 23, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V 0 ➤ -10 -20 Gb Ethernet Filter -40 156.25MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 ➤ -160 -170 Phase Noise Result by adding Gb Ethernet Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 156.25MHZ @ 2.5V ➤ 0 -10 Gb Ethernet Filter -20 -40 156.25MHz -50 RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 -150 -160 -170 ➤ -180 Phase Noise Result by adding Gb Ethernet Filter to raw data -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 844051CGI www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 23, 2005 PRELIMINARY ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR Integrated Circuit Systems, Inc. PARAMETER MEASUREMENT INFORMATION SCOPE Qx Qx Power Supply + Float GND 2.5V±5% POWER SUPPLY LVDS - + Float GND - SCOPE LVDS nQx nQx LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nQ Q t PW t Phase Noise Mask odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VVDD DD out 80% DC Input VSW I N G Clock Outputs LVDS ➤ 80% ➤ 20% 20% tR out tF VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP OUTPUT RISE/FALL TIME VDD V DD ➤ out ➤ LVDS 100 VOD/Δ VOD out ➤ DC Input DIFFERENTIAL OUTPUT VOLTAGE SETUP 844051CGI www.icst.com/products/hiperclocks.html 6 REV. A NOVEMBER 23, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844051I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V or 2.5V VDD .01μF 10Ω V DDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS844051I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel XTAL_IN C1 X1 Crystal XTAL_OUT C2 Figure 2. CRYSTAL INPUt INTERFACE 844051CGI www.icst.com/products/hiperclocks.html 7 REV. A NOVEMBER 23, 2005 PRELIMINARY ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR Integrated Circuit Systems, Inc. 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844051CGI www.icst.com/products/hiperclocks.html 8 REV. A NOVEMBER 23, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS844051I is: 2395 844051CGI www.icst.com/products/hiperclocks.html 9 REV. A NOVEMBER 23, 2005 PRELIMINARY ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 844051CGI www.icst.com/products/hiperclocks.html 10 REV. A NOVEMBER 23, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS844051I FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844051CGI 451CI 8 Lead TSSOP tube -40°C to 85°C ICS844051CGIT 451CI 8 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS844051CGILF TBD 8 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS844051CGILFT TBD 8 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts thar are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844051CGI www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 23, 2005