PRELIMINARY ICS8725 Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS8725 is a high performance LVHSTL zero delay buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clocks Solutions from ICS. The VCO operates at a frequency range of 250MHz to 500MHz. Utilizing one of the outputs as feedback to the PLL output frequencies up to 500MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications. • Fully integrated PLL ,&6 • 5 LVHSTL outputs each with the ability to drive 50Ω to ground • Voh (max) = 1.2V • 31.25MHz to 500MHz output frequency range • Spread Smart™ for regenerating spread spectrum clocks • Differential reference clock inputs accept any differential input signal •· Differential reference clock inputs will accept single ended input signal with one of the inputs biased with a resistor network • 31.25MHz to 622MHz input frequency range • LVCMOS / LVTTL control inputs • 3.3V core, 1.8V output operating supply voltage • 32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.8mm package lead pitch • 0°C to 70°C ambient operating temperature • Industrial temperature version available upon request BLOCK DIAGRAM PIN ASSIGNMENT VDDO nQ4 Q4 VEE VEE VDDA VDDi PLL_SEL DIV_SEL0 32 31 30 29 28 27 26 25 DIV_SEL1 REF_CLK1 nREF_CLK1 0 REF_CLK2 nREF_CLK2 1 0 0 ÷8 1 PLL 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 ÷1 ÷2 ÷4 ÷8 REF_SEL DIV_SEL0 1 24 VDDO DIV_SEL1 2 23 Q3 REF_CLK1 3 22 nQ3 nREF_CLK1 4 21 Q2 REF_CLK2 5 20 nQ2 nREF_CLK2 6 19 Q1 REF_SEL 7 18 nQ1 MR 8 17 VDDO REF_DIV FB_IN nFB_IN ICS8725 9 10 11 12 13 14 15 16 VDDO Q0 nQ0 VEE REF_DIV FB_IN MR nFB_IN VDDI PLL_SEL 32-Lead LQFP Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8725 www.icst.com/products/hiperclocks.html 1 REV. A MARCH 5, 2001 PRELIMINARY ICS8725 Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 DIV_SEL0 Input 2 DIV_SEL1 Input 3 REF_CLK1 Input 4 nREF_CLK1 Input 5 REF_CLK2 Input 6 nRE2_CLK2 Input 7 REF_SEL Input 8 MR Input Description Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Differential clock select input. When Low selects REF_CLK2 or Pulldown nREF_CLK2. When HIGH selects REF_CLK1 or nREF_CLK1. Resets dividers and determine state of the outputs. Pulldown LVCMOS / LVTTL interface levels. Input and core power supply pin. Connect to 3.3V. 9 VDDI Power 10 nFB_IN Input 11 FB_IN Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". 12 13, 28, 29 REF_DIV Input Pulldown VEE Power Ground pins. Connect to ground. 14, 15 nQ0, Q0 Output Differential clock outputs. 50Ω typical output impedance. LVHSTL interface levels. 16. 17, 24, 25 VDDO Power Output power supply pins. Connect to 1.8V. 30 nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 VDDA 31 PLL_SEL Input 32 VDDI Power 18, 19 20, 21 22, 23 26, 27 8725 Pullup Output Output Output Output Power Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Differential clock outputs. 50Ω typical output impedance. LVHSTL interface levels. Differential clock outputs. 50Ω typical output impedance. LVHSTL interface levels. Differential clock outputs. 50Ω typical output impedance. LVHSTL interface levels. Differential clock outputs. 50Ω typical output impedance. LVHSTL interface levels. PLL power supply pin. Connect to 3.3V. Selects between the PLL and the reference clock as the input to the dividers. When HIGH select PLL. When LOW selects reference clock. LVCMOS / LVTTL interface levels. Output power supply pin. Connect to 3.3V. www.icst.com/products/hiperclocks.html 2 REV. A MARCH 5, 2001 PRELIMINARY ICS8725 Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER TABLE 2. PIN CHARACTERISTICS Symbol Parameter Input Capacitance CIN Test Conditions Minimum REF_CLK1, nREF_CLK1, REF_CLK2, nREF_CLK2, FB_IN, nFB_IN DIV_SEL0, DIV_SEL1, REF_SEL, REF_DIV PLL_SEL, MR Input Pullup Resistor Input Pulldown Resistor RPULLUP RPULLDOWN Typical Maximum Units TBD pF TBD pF 51 KΩ 51 KΩ TABLE 3. CONTROL INPUTS FUNCTION TABLE DIV_SEL1 DIV_SEL0 0 0 FREQUENCY (MHz) MINIMUM MAXIMUM 250 250 0 1 125 250 1 0 62.5 125 1 1 31.25 62.5 TABLE 4. PLL INPUT REFERENCE CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C Symbol Parameter fREF Input Reference Frequency Test Conditions Minimum 20 Typical Maximum Units 250 MHz tR Input Rise Time Measured at 20% to 80% points TBD ns tF Input Fall Time Measured at 20% to 80% point TBD ns tDC Input Reference Duty Cycle TBD % 8725 TBD www.icst.com/products/hiperclocks.html 3 REV. A MARCH 5, 2001 PRELIMINARY ICS8725 Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage 4.6V Inputs -0.5V to VDD+0.5 V Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0°C to 70°C Storage Temperature -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C Symbol Parameter VDDI VDDA Test Conditions Minimum Typical Maximum Units Input Power Supply Voltage 3.135 3.3 3.465 V Analog Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Power Supply Voltage IEE Power Supply Current 1.8 V mA TABLE 5B. DIFFERENTIAL DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units REF_CLK1, REF_CLK2, VIN = 3.465V 150 µA FB_IN IIH Input High Current nREF_CLK1, nREF_CLK2, VIN = 3.465V 5 µA nFB_IN REF_CLK1, REF_CLK2, VIN = 0V -5 µA IIL Input Low Current FB_IN nREF1, nREF2, nFB_IN VIN = 0V -150 µA NOTE: For REF_CLK1, nREF_CLK1 and REF_CLK2, nREF_CLK2 input levels, see VPP and VCMR in AC Characteristics table. TABLE 5C. LVCMOS DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions DIV_SEL0, DIV_SEL1, REF_SEL, PLL_SEL, REF_DIV, MR DIV_SEL0, DIV_SEL1, REF_SEL, PLL_SEL, REF_DIV, MR DIV_SEL0, DIV_ SEL1, REF_DIV, REF_SEL, MR PLL_SEL IIL 8725 Input Low Current Minimum Typical Maximum Units 2 3.765 V -0.3 0.8 V VIN = 3.465V 150 µA VIN = 3.465V 5 µA DIV_SEL0, DIV_ SEL1, REF_DIV, REF_SEL, MR VIN = 0V -5 µA PLL_SEL VIN = 0V -150 µA www.icst.com/products/hiperclocks.html 4 REV. A MARCH 5, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8725 1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER TABLE 5D. LVHSTL DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Test Conditions Minimum Typical Maximum Units 1.2 V 1.0 0 0.4 40% x (VOH-VOL) 60% x (VOH-VOL) VOX Output Crossover Voltage + VOL + VOL NOTE 1: Outputs terminated with 50Ω to ground. The power dissipation of a terminated output pair is 32mW. V V TABLE 6. AC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units 500 MHz fMAX Maximum Output Frequency VPP Peak-to-Peak Input Voltage f = 500MHz Common Mode Input Voltage f = 500MHz Propagation Delay, Low-to-High Propagation Delay, High-to-Low REF_CLK1, PLL Reference nREF_CLK1 Zero Delay; REF_CLK2, NOTE 2 nREF_CLK2 PLL_SEL=0V, 0MHz ≤ f ≤ 500MHz TBD TBD ns PLL_SEL=0V, 0MHz ≤ f ≤ 500MHz TBD TBD ns PLL_SEL=3.3V, fREF=TBD, fVCO=TBD -100 100 ps 100 ps VCMR tpLH tpHL t(Ø) Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 TBD tsk(o) Output Skew; NOTE 3 tjit(cc) Cycle-to-Cycle Jitter tL PLL Lock Time tR Output Rise Time TBD TBD ps tF Output Fall Time TBD TBD ps tPW Output Pulse Width ±100 ps TBD 0MHz ≤ f ≤ 500MHz tCYCLE/2 -TBD tCYCLE/2 tCYCLE/2 +TBD ns f = 500MHz TBD 2.08 TBD ns tEN Output Enable Time TBD ns tDIS Output Disable Time TBD ns NOTE 1: All parameters measured at fMAX unless noted otherwise. All outputs terminated with 50Ω to VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent pairs of cycles. 8725 www.icst.com/products/hiperclocks.html 5 REV. A MARCH 5, 2001 PRELIMINARY ICS8725 Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX D D2 θ E 25 24 32 1 2 3 L E1 E2 N 8 17 16 9 e A D1 A2 -Cccc C b A1 SEATING PLANE c TABLE 7. PACKAGE DIMENISIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL 32 N 1.60 A A1 MAXIMUM 0.05 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 E 9.00 BASIC E1 7.00 BASIC E2 5.60 e 0.80 BASIC L 0.45 q 0° 0.60 0.75 7° 0.10 ccc Reference Document: JEDEC Publication 95, MS-026 8725 www.icst.com/products/hiperclocks.html 6 REV. A MARCH 5, 2001 PRELIMINARY ICS8725 Integrated Circuit Systems, Inc. 1-TO-5 DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8725Y ICS87251 32 Lead LQFP 250 per tray 0°C to 70°C ICS8725YT ICS8725 32 Lead LQFP on Tape and Reel 2000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8725 www.icst.com/products/hiperclocks.html 7 REV. A MARCH 5, 2001