ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8735-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL clock generator and a HiPerClockS™ member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The ICS8735-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • 1 differential 3.3V LVPECL output pair, 1 differential feedback output pair ICS • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency range: 31.25MHz to 700MHz • Input frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: 25ps (maximum) • Static phase offset: 50ps ± 100ps • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT PLL_SEL ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 CLK nCLK 0 Q nQ 1 QFB nQFB CLK nCLK MR VCC nFB_IN FB_IN SEL2 VEE nQFB QFB PLL FB_IN nFB_IN 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCCO Q nQ ICS8735-21 20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View SEL0 SEL1 SEL2 SEL3 MR 8735AM-21 www.icst.com/products/hiperclocks.html 1 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 CLK Input Pulldown Non-inver ting differential clock input. 2 nCLK Input 3 MR Input 4, 17 VCC Power 5 nFB_IN Input 6 FB_IN Input 7 SEL2 Input Inver ting differential clock input. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outpus Q to go low and the inver ted outputs nQ to go high. Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Feedback input to phase detector for regenerating clocks with "zero delay". Pullup Connect to pin 9. Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Connect to pin 10. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 8 Power Negative supply pin. Output Differential feedback outputs. LVPECL interface levels. 11, 12 VEE nQFB, QFB nQ, Q Output Differential clock outputs. LVPECL interface levels. 13 VCCO Power Output supply pin. 14 SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 15 VCCA Power 16 PLL_SEL Input 18 S E L0 Input Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. Pullup When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 19 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 20 nc Unused 9, 10 Type Description Pullup No connect. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ICS8735AM-21 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR TABLE 3A. CONTROL INPUT FUNCTION TABLE SEL3 SEL2 S E L1 SEL0 Reference Frequency Range (MHz)* Outputs PLL_SEL = 1 PLL Enable Mode Q, nQ; QFB, nQFB 0 0 0 0 250 - 700 ÷1 0 0 0 1 125 - 350 ÷1 0 0 1 0 62.5 - 175 ÷1 0 0 1 1 31.25 - 87.5 ÷1 0 1 0 0 250 - 700 ÷2 0 1 0 1 125 - 350 ÷2 0 1 1 0 62.5 - 175 ÷2 Inputs 0 1 1 1 250 - 700 ÷4 1 0 0 0 125 - 350 ÷4 1 0 0 1 250 - 700 ÷8 1 0 1 0 125 - 350 x2 1 0 1 1 62.5 - 175 x2 1 1 0 0 31.25 - 87.5 x2 1 1 0 1 62.5 - 175 x4 1 1 1 0 31.25 - 87.5 x4 1 1 1 1 31.25 - 87.5 x8 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. TABLE 3B. PLL BYPASS FUNCTION TABLE SEL3 SEL2 S E L1 SEL0 Outputs PLL_SEL = 0 PLL Bypass Mode Q, nQ; QFB, nQFB 0 0 0 0 ÷4 0 0 0 1 ÷4 0 0 1 0 ÷4 0 0 1 1 ÷8 0 1 0 0 ÷8 0 1 0 1 ÷8 0 1 1 0 ÷ 16 0 1 1 1 ÷ 16 1 0 0 0 ÷ 32 1 0 0 1 ÷ 64 1 0 1 0 ÷2 1 0 1 1 ÷2 1 1 0 0 ÷4 1 1 0 1 ÷1 1 1 1 0 ÷2 1 1 1 1 ÷1 Inputs 8735AM-21 www.icst.com/products/hiperclocks.html 3 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 150 mA ICCA Analog Supply Current 15 mA Maximum Units TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA IIL Input Low Current SEL0, SEL1, SEL2, SEL3, MR PLL_SEL SEL0, SEL1, SEL2, SEL3, MR PLL_SEL VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions CLK, FB_IN nCLK, nFB_IN Minimum Typical VCC = VIN = 3.465V VCC = VIN = 3.465V Units 150 µA 5 µA CLK, FB_IN VCC = 3.465V, VIN = 0V -5 µA nCLK, nFB_IN VCC = 3.465V, VIN = 0V -150 µA IIL Input Low Current V PP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. ICS8735AM-21 Maximum www.icst.com/products/hiperclocks.html 4 1.3 V VCC - 0.85 V REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 1.0 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 0.9 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fIN Input Frequency CLK, nCLK Test Conditions Minimum PLL_SEL = 1 31.25 Typical PLL_SEL = 0 700 MHz 700 MHz Maximum Units 700 MHz 4.2 ns 20 150 25 ±50 ps ps ps ps 1 ms TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency Test Conditions tPD Propagation Delay; NOTE 1 tsk(o) t(Ø) t jit(cc) t jit(θ) Output Skew; NOTE 4, 5 Static Phase Offset; NOTE 2, 5 Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 3, 5, 6 tL PLL Lock Time tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps PLL_SEL = 0V, f ≤ 700MHz PLL_SEL = 0V PLL_SEL = 3.3V Minimum Typical 3.0 -50 50 odc Output Duty Cycle 47 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Phase jitter is dependent on the input source used. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crosspoints. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. 8735AM-21 www.icst.com/products/hiperclocks.html 5 % REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V VCC VCC, VCCA, VCCO Qx SCOPE nCLK LVPECL V V Cross Points PP nQx CMR CLK V EE V EE -1.3V ± 0.165V DIFFERENTIAL INPUT LEVEL nQx nQ, nQFB Qx Q, QFB ➤ nQy tCycle n ➤ 3.3V OUTPUT LOAD AC TEST CIRCUIT ➤ tCycle n + 1 ➤ tJIT(cc) = tCycle n - tCycle n+1 Qy t sk(o) OUTPUT SKEW CYCLE-TO-CYCLE JITTER nCLK VOH CLK VOL nCLK nFB_IN VOH nFB_IN VOL CLK ➤ ➤ t (Ø) nQ, nQFB tjit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter Q, QFB t (Ø) mean = Static Phase Offset tPD (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) PHASE JITTER AND STATIC PHASE OFFSET PROPAGATION DELAY nQ, nQFB 80% Q, QFB 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ICS8735AM-21 www.icst.com/products/hiperclocks.html 6 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8735-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01µF 10Ω VCCA .01µF 10 µF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8735AM-21 www.icst.com/products/hiperclocks.html 7 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. TERMINATION FOR 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = FIN 50Ω Zo = 50Ω VCC - 2V 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION SCHEMATIC EXAMPLE Figure 4 shows a schematic example of the ICS8735-21. In this example, the input is driven by an HCSL driver. The zero delay buffer is configured to operate at 155.52MHz input and 77.75MHz output. The logic control pins are configured as follows: SEL [3:0] = 0101; PLL_SEL = 1 The decoupling capacitors should be physically located near the power pin. For ICS8735-21. R7 3.3V VCC VCCA U1 Zo = 50 Ohm 10 (155.5 MHz) 1 2 3 4 5 6 7 8 9 10 VCC Zo = 50 Ohm SEL2 HCSL R8 50 R9 50 CLK nCLK MR VCCI nFB_IN FB_IN SEL2 VEE nQFB QFB nc SEL1 SEL0 VCCI PLL_SEL VCCA SEL3 VCCO Q nQ 20 19 18 17 16 15 14 13 12 11 C11 0.01u SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCC C16 10u Zo = 50 Ohm + Zo = 50 Ohm R1 50 VCC RU3 1K RU4 1K RU5 SP RU6 1K R2 50 ICS8735-21 - (77.75 MHz) RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3 R4 50 R3 50 Bypass capacitors located near the power pins (U1-4) VCC RD3 SP RD4 SP RD5 1K RD6 SP LVPECL_input RD7 1K SP = Space (i.e. not intstalled) (U1-17) R5 50 R6 50 (U1-13) VCC=3.3V C1 0.1uF C2 0.1uF C3 0.1uF SEL[3:0] = 0101, Divide by 2 FIGURE 4. ICS8735-21 LVPECL BUFFER SCHEMATIC EXAMPLE ICS8735AM-21 www.icst.com/products/hiperclocks.html 8 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 5A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 5B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 5C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER 8735AM-21 nCLK Zo = 50 Ohm FIGURE 5D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY www.icst.com/products/hiperclocks.html 9 BY REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8735-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8735-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.465V, with all outputs switching) = 519.8mW + 60.4mW = 580.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.580W * 39.7°C/W = 93°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W 200 500 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS8735AM-21 www.icst.com/products/hiperclocks.html 10 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX – 1.0V ) = 1.0V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 1V)/50Ω] * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8735AM-21 www.icst.com/products/hiperclocks.html 11 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 83.2°C/W 46.2°C/W 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8735-21 is: 2969 ICS8735AM-21 www.icst.com/products/hiperclocks.html 12 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX FOR 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR 20 LEAD SOIC TABLE 9. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 BASIC H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 8735AM-21 www.icst.com/products/hiperclocks.html 13 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8735AM-21 ICS8735AM-21 20 Lead SOIC 38 per tube 0°C to 70°C ICS8735AM-21T ICS8735AM-21 20 Lead SOIC on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8735AM-21 www.icst.com/products/hiperclocks.html 14 REV. D OCTOBER 27, 2003 ICS8735-21 Integrated Circuit Systems, Inc. 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR REVISION HISTORY SHEET Rev Table B T6 T6 B T3A T6 B T2 B 8 8-9 B B Page 1 5 5 7 3 5 10 2 6 T1 T4A 2 4 9 T2 C D 8735AM-21 T6 2 4 7 8 8 9 5 Description of Change Revised Block Diagram. Added Output Skew row at 20ps Max. Relabled PLL Reference Zero Delay to Static Phase Offset. Added Output Skew Diagram. Added note at bottom of the table. Added Note 6. Added Termination for LVPECL Outputs section Pin Description Table - revised MR description. 3.3V Output Load Test Circuit Diagram, revised VEE equation from "-1.3V ± 0.135V" to " -1.3V ± 0.165V". Revised Output Rise/Fall Time Diagram. Added Schematic Example section Date 10/31/01 11/20/01 6/3/02 8/19/02 10/17/02 Pin Description table - revised MR and VCC descriptions. Power Supply table - revised VCC Parameter to correspond with pin description. Deleted Figure 8, "Clock Input Driven by LVPECL Driver w/AC Couple". AC Couple is not recommended for Zero Delay Buffers. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Absolute Maximum Ratings - revised Output rating. Updated Single Ended Signal Driving Differential Input Diagram. Updated LVPECL Output Termination Diagrams. Updated Schematic Example. Updated Differential Clock Input Interface drawings. AC Characteristics Table - modifed tPD min. limit from 3.6ns to 3.0ns and deleted the typical value. www.icst.com/products/hiperclocks.html 15 2/03/03 10/13/03 10/27/03 REV. D OCTOBER 27, 2003