ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR GENERAL DESCRIPTION FEATURES The ICS874005 is a high performance Differential-to-LVDS Jitter Attenuator designed for HiPerClockS™ use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874005 has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the 874005 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins. • Five differential LVDS output pairs ICS • One differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 30ps (maximum) • 3.3V operating supply • 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages PLL BANDWIDTH The ICS874005 uses ICS 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~400kHz (Default) 1 = PLL Bandwidth: ~800kHz PIN ASSIGNMENT BLOCK DIAGRAM OEA Pulldown F_SELA Pulldown QA0 BW_SEL Float 0 = ~200kHz Float = ~400kHz 1 = ~800kHz F_SELA 0 ÷5 (default) 1 ÷4 QA1 CLK Pulldown nCLK Pullup nQA0 Phase Detector VCO nQA1 490 - 640MHz QB0 F_SELB 0 ÷5 (default) 1 ÷4 nQB0 QB1 M = ÷5 (fixed) nQB1 nQB2 nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL VDDA F_SELA VDD OEA 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 QB2 VDDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK ICS874005 24-Lead TSSOP QB2 4.40mm x 7.8mm x 0.92mm package body nQB2 G Package Top View F_SELB Pulldown MR Pulldown OEB Pullup 874005AG www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 24 nQB2, QB2 Output Differential output pair. LVDS interface levels. 2, 3 nQA1, QA1 Output Differential output pair. LVDS interface levels. 4, 23 VDDO Power Output supply pins. 5, 6 QA0, nQA0 Output 6 nFB_OUT Output 7 MR Input 8 BW_SEL Input 9 VDDA Power 10 F_SELA Input 11 VDD Power 12 OEA Input 13 CLK Input 14 nCLK Input 15, 16 GND Power 17 OEB Input 18 F_SELB Input 19, 20 nQB0, QB0 Output 21, 22 nQB1, QB1 Output Description Differential output pair. LVDS interface levels. Inver ting differential feedback output. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ PLL Bandwidth input. See Table 3B. Pulldown Analog supply pin. Frequency select pin for QAx/nQAx outputs. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high impedance Pullup state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Frequency select pin for QBx/nQBx outputs. Pulldown LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Inputs TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Inputs Outputs OEA/OEB QAx/nQAx QBx/nQBx PLL_BW PLL Bandwidth 0 HiZ HiZ 0 ~200kHz 1 Enabled Enabled 1 ~800kHz Float ~400kHz 874005AG www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V VDDA Analog Supply Voltage 3.135 3. 3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 85 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 115 mA Maximum Units VDD + 0.3 V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage Test Conditions Minimum OEA, OEB, MR, F_SELA, F_SELB 2 BW_SEL VIL Input Low Voltage VDD - 0.4 OEA, OEB, MR, F_SELA, F_SELB -0.3 BW_SEL VIM Input Mid Voltage IIH Input High Current IIL Input Low Current 874005AG Typical BW_SEL VDD/2 - 0.1 OEA, OEB F_SELA, F_SELB MR, BW_SEL BW_SEL, OEA, OEB MR, F_SELA, F_SELB V 0.8 V 0.4 V VDD/2 + 0.1 V VDD = VIN = 3.465V 5 µA VDD = VIN = 3.465V 150 µA VDD = 3.465V, VIN = 0V -150 µA VDD = 3.465V, VIN = 0V -5 µA www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V Minimum Typical Maximum Units 15 0 µA 15 0 µA 5 -150 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. 1.3 V VDD - 0.85 V TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.2 1.35 1.5 V 50 mV Maximum Units 160 MHz 30 ps TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter, NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time Test Conditions Minimum Typical 98 15 20% to 80% 300 odc Output Duty Cycle 48 NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. 874005AG www.icst.com/products/hiperclocks.html 4 90 ps 550 ps 52 % REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION VDD, VDDO VDDA VDD Qx 3.3V±5% POWER SUPPLY Float GND + – nCLK SCOPE V V Cross Points PP LVDS CMR CLK nQx GND 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQA0, nQA1 nQB0:nQB2 nQx QA0, QA1 QB0:QB2 Qx tcycle ➤ ➤ tcycle n ➤ ➤ n+1 nQy t jit(cc) = tcycle n –tcycle n+1 Qy 1000 Cycles tsk(o) CYCLE-TO-CYCLE JITTER OUTPUT SKEW nQA0, nQA1 nQB0:nQB2 80% 80% QA0, QA1 QB0:QB2 VSW I N G Clock Outputs 20% 20% tR t PW t PERIOD tF odc = t PW x 100% t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD VDD out ➤ ➤ LVDS 100 DC Input LVDS VOD/Δ VOD out ➤ out ➤ DC Input ➤ out VOS/Δ VOS ➤ DIFFERENTIAL OUTPUT VOLTAGE SETUP 874005AG OFFSET VOLTAGE SETUP www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874005 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 874005AG www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 874005AG LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION SCHEMATIC EXAMPLE Figure 5 shows an example of ICS874005 application schematic. In this example, the device is operated at VDD=3.3V. The VDD = 3.3V decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. VDDO = 3.3V Zo = 50 Ohm + U1 R1 10 C3 10uF C4 0.01u MR BW_SEL F_SELA OEA 1 2 3 4 5 6 7 8 9 10 11 12 R2 100 nQB2 nQA1 QA1 VDDO QA0 nQAO MR BW_SEL VDDA F_SELA VDD OEA QB2 VDDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK 24 23 22 21 20 19 18 17 16 15 14 13 - Zo = 50 Ohm F_SELB OEB Zo = 50 Ohm + 874005_tssop24 R3 100 Zo = 50 Ohm Zo = 50 Ohm - nCLK Zo = 50 Ohm CLK LVPECL Driv er (U1:11) C5 10uf (U1:4) C6 .1uf R4 50 R5 50 (U1:23) C7 .1uf C8 .1uf R6 50 FIGURE 5. ICS874005 SCHEMATIC EXAMPLE 874005AG www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS874005. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874005 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (85mA + 15mA) = 346.5mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 115mA = 398.48mW Total Power_MAX = 346.5mW + 398.48mW = 745mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.745W * 63°C/W = 117°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 200 63°C/W 500 60°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 874005AG www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 70°C/W 63°C/W 60°C/W TRANSISTOR COUNT The transistor count for ICS874005 is: 1206 874005AG www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX PCI EXPRESS™ JITTER ATTENUATOR FOR 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 874005AG www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 25, 2006 ICS874005 Integrated Circuit Systems, Inc. PCI EXPRESS™ JITTER ATTENUATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS874005AG ICS874005AG 24 Lead TSSOP tube 0°C to 70°C ICS874005AGT ICS874005AG 24 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS874005AGLF TB D 24 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS874005AGLFT TBD 24 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint. The aforementioned trademarks, HiPerClockS and FemtoClock are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 874005AG www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 25, 2006