ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR General Description Features The ICS874003-05 is a high performance Differential-to-LVDS Jitter Attenuator designed for HiPerClockS™ use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-05 has a bandwidth of 6.2MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL requirements. • • • Three differential LVDS output pairs • • • • • • • • • Input frequency range: 98MHz to 128MHz ICS The ICS874003-05 uses IDT’s 3rd Generation FemtoClock™ PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. One differential clock input CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 98MHz to 320MHz VCO range: 490MHz - 640MHz Supports PCI-Express Spread-Spectrum Clocking High PLL bandwidth allows for better input tracking PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant 0°C to 70°C ambient operating temperature Full 3.3V operating supply Available in lead-free (RoHS 6) packages Pin Assignment F_SEL[2:0] Function Table Inputs Outputs F_SEL2 F_SEL1 F_SEL0 QA[0:1], nQA[0:1] QB0, nQB0 0 (default) 0 (default) 0 (default) ÷2 ÷2 1 0 0 ÷5 ÷2 0 1 0 ÷4 ÷2 1 1 0 ÷2 ÷4 0 0 1 ÷2 ÷5 1 0 1 ÷5 ÷4 0 1 1 ÷4 ÷5 1 1 1 ÷4 ÷4 IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 1 QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003-05 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Block Diagram OEA Pullup F_SEL2:0 Pulldown 3 QA0 ÷5 ÷4 ÷2 (default) nQA0 QA1 CLK Pulldown nCLK Pullup Phase Detector VCO nQA1 490 - 640MHz 3 ÷5 ÷4 ÷2 (default) M = ÷5 (fixed) QB0 nQB0 MR Pulldown OEB Pullup IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 2 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Table 1. Pin Descriptions Number Name Type Description 1, 20 QA1, nQA1 Output Bank A differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output Bank A differential output pair. LVDS interface levels. 5 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inverted outputs (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6, 9, 16 F_SEL0, F_SEL1, F_SEL2 Input Pulldown Frequency select pin for QAx/nQAx and QB0/nQB0 outputs. LVCMOS/LVTTL interface levels. 7 nc Unused 8 VDDA Power Analog supply pin. 10 VDD Power Core supply pin. 11 OEA Input Pullup 12 CLK Input Pulldown 13 nCLK Input Pullup 14 GND Power 15 OEB Input 17, 18 nQB0, QB0 Output No connect. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Pullup Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are active. When LOW, the QB0/nQB0 outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. Bank B differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ Table 3. Output Enable Function Table Inputs Outputs OEA OEB QA[0:1], nQA[0:1] QB0, nQB0 0 0 High Impedance High Impedance 1 (default) 1 (default) Enabled Enabled IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 3 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics,VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.16 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 75 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical OEA, OEB VDD = VIN = 3.465V 5 µA F_SEL0, F_SEL1, F_SEL2, MR VDD = VIN = 3.465V 150 µA OEA, OEB VDD = 3.465V, VIN = 0V -150 µA F_SEL0, F_SEL1, F_SEL2, MR VDD = 3.465V, VIN = 0V -5 µA IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 4 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK VDD = VIN = 3.465V 150 µA nCLK VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.50 V 50 mV 1.20 5 1.35 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fMAX Output Frequency tjit(cc) Maximum Units 320 MHz Cycle-to-Cycle Jitter; NOTE 4 35 ps tsk(o) Output Skew; NOTE 4, 5 145 ps tsk(b) Bank Skew; NOTE 4, 6 55 ps tR / tF Output Rise/Fall Time 200 600 ps odc Output Duty Cycle 47 53 % tj tREFCLK_HF_RMS tREFCLK_LF_RMS Phase Jitter Peak-to-Peak; NOTE 1, 3 Phase Jitter RMS; NOTE 2, 3 Phase Jitter RMS; NOTE 2, 3 Test Conditions Minimum Typical 98 Bank A 20% to 80% 100MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.54 ps 125MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.13 ps 250MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 12.87 ps 100MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.22 ps 125MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.17 ps 250MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.11 ps 100MHz output, Low Band: 10kHz - 1.5MHz 0.25 ps 125MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps 250MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Peak-to-peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. See IDT Application Note PCI Express Reference Clock Requirements, and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 6 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information VDD SCOPE 3.3V±5% POWER SUPPLY + Float GND – VDD, VDDO nCLK Qx V V Cross Points PP VDDA CMR CLK LVDS nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nQA0 nQAx, nQB0 QA0 QAx, QB0 ➤ ➤ nQA1 ➤ tcycle n tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles QA1 tsk(b) Bank Skew Cycle-to-Cycle Jitter nQx nQAx, nQB0 Qx QAx, QB0 t PW t nQy Qy odc = tsk(o) t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Skew IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR PERIOD 7 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information, continued VDD nQAx, nQB0 out 80% VOD QAx, QB0 DC Input 20% 20% LVDS tF tR ➤ 80% out ➤ VOS/∆ VOS ➤ Output Rise/Fall Time Offset Voltage Setup VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out Differential Output Voltage Setup IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 8 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS874003-05 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 9 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver HiPerClockS Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK HiPerClockS Input LVPECL R1 84 R2 84 Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V nCLK Zo = 50Ω Receiver LVDS Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 10 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 11 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Schematic Example Figure 5 shows an example of ICS874003-05 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. Two examples of LVDS terminations are shown in this schematic. The input is driven either by a 3.3V LVPECL driver or a 3.3V LVCMOS. ICS874003-05 Figure 5. ICS874003-05 Schematic Example IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 12 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz Nyquist (High Band). The below plots show the individual transfer functions as well as the overall transfer function Ht. The respective -3 dB pole frequencies for each transfer function are labeled as F1 for transfer function H1, F2 for H2, and F3 for H3. For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. Ht ( s ) = H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y ( s ) = X ( s ) × H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 13 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Magnitude of Transfer Functions - PCIe Gen 1 0 F1: 2.2e+007 F2: 1.5e+006 F3: 1.5e+006 -10 Mag (dB) -20 -30 -40 H1 H2 H3 Ht=(H1-H2)*H3 -50 -60 3 10 4 10 5 6 7 10 10 Frequency (Hz) 10 PCIe Gen 1 Magnitude of Transfer Function Magnitude of Transfer Functions - PCIe Gen 2B Magnitude of Transfer Functions - PCIe Gen 2A 0 F1: 1.6e+007 F2: 5.0e+006 F3: 1.0e+006 -10 -10 -20 -20 Mag (dB) Mag (dB) 0 -30 -30 -40 -40 H1 H2 H3 Ht=(H1-H2)*H3 -50 -60 3 10 F1: 1.6e+007 F2: 8.0e+006 F3: 1.0e+006 4 10 5 6 10 10 Frequency (Hz) -60 3 10 7 10 PCIe Gen 2A Magnitude of Transfer Function IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR H1 H2 H3 Ht=(H1-H2)*H3 -50 4 10 5 6 10 10 Frequency (Hz) 7 10 PCIe Gen 2B Magnitude of Transfer Function 14 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS874003-05. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS74003-05 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 16mA) = 315.315mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.875mW Total Power_MAX = 315.3mW + 259.9mW = 575.2mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.575W * 86.7°C/W = 119.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W 15 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W Transistor Count The transistor count for ICS874003-05 is: 1418 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 16 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 874003BG-05LF 874003BG-05LFT Marking 874003BG-05LF 874003BG-05LF Package “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 17 ICS874003BG-05 REV. A APRIL 15, 2009 ICS874003-05 PCI EXPRESS™ JITTER ATTENUATOR Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA