ICS951403 Integrated Circuit Systems, Inc. AMD-K7TM System Clock Chip Recommended Application: ATI chipset with K7 systems Output Features: • 3 differential pair open drain CPU clocks (1.5V external pull-up; up to 150MHz achieviable through I2C) • 2 - AGPCLK @ 3.3V • 8 - PCI @3.3V, including 1 free running • 1 - 48MHz @ 3.3V • 1 - 24/48MHz @ 3.3V • 2- REF @3.3V, 14.318MHz. Features: • Programmable ouput frequency • Programmable ouput rise/fall time • Programmable group skew • Real time system reset output • Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage • Watchdog timer technology to reset system if over-clocking causes malfunction • Uses external 14.318MHz crystal • Asyncronous CPU and SDRAM clocks • CPU and PCI outputs are aligned • CPU - AGP skew <500ps Block Diagram 48MHz 24_48MHz /2 XTAL OSC PLL1 Spread Spectrum REF (1:0) CPU DIVDER Stop 3 3 SDRAM DIVDER CPUCLKT (2:0) CPUCLKC (2:0) SDRAM_OUT SEL24_48# SDATA Control SCLK PD# PCI_STOP# PCI DIVDER Stop 7 AGP DIVDER Config. Reg. PCICLK (6:0) PCICLK_F Logic FS (2:0) 48-Pin SSOP & TSSOP * Internal 120K pullup resistor on indicated inputs ** Internal 240K pullup resistor on indicated inputs Functionality PLL2 X1 X2 Pin Configuration 2 AGP (1:0) Bit 7 FS2 FS1 FS0 CPU SDRAM PCICLK 0 0 0 0 100.00 100.00 33.33 66.67 50.00 0 0 0 1 100.00 133.33 33.33 66.67 50.00 0 0 1 0 100.00 150.00 30.00 60.00 50.00 0 0 1 1 100.00 66.67 33.33 66.67 50.00 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 133.33 125.00 124.00 133.33 133.33 100.00 124.00 100.00 33.33 31.25 31.00 33.33 66.67 62.50 62.00 66.67 50.00 50.00 46.50 50.00 1 0 0 0 112.00 112.00 33.60 67.20 56.00 1 0 0 1 150.00 150.00 30.00 60.00 50.00 1 0 1 0 111.11 166.67 33.33 66.67 55.56 1 0 1 1 110.00 165.00 33.00 66.00 55.00 1 1 0 0 166.67 166.67 33.33 66.67 55.56 1 1 0 1 90.00 90.00 30.00 60.00 45.00 1 1 1 0 48.00 48.00 32.00 64.00 48.00 1 1 1 1 45.00 60.00 30.00 60.00 45.00 CPU_STOP# SPREAD# Power Groups VDD48, GND48 = 48MHz, PLL2 VDDREF, GNDREF= REF, X1, X2 VDD, GND = PLL Core 0486B—02/23/04 AGP SEL = AGP SEL = 0 1 ICS951403 General Description The ICS951403 is a main clock synthesizer chip for AMD-K7 based systems with ATI chipset. This provides all clocks required for such a system. The ICS951403 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. Pin Descriptions PIN NUMBER PIN NAME FS (1:0) REF (1:0) TYPE IN OUT DESCRIPTION Frequency Select pins, has pull-up to VDD 14.318MHz clock output 3, 6, 21, 25, 33, 38, 41, 47 GND PWR Ground 4 X1 IN 5 X2 OUT 7 PCICLK_F OUT PCICLK (6:0) OUT PCI clock outputs. TTL compatible 3.3V VDDPCI VDDAGP PWR PWR Power for PCICLK outputs, nominally 3.3V Power for AGP outputs, nominally 3.3V AGP outputs defined as 2X PCI. These may not be stopped. Isolated power for core, nominally 3.3V Power for 48MHz and 24MHz outputs nominally 3.3V 48MHz output Selects 24 or 48MHz output for pin 24 Low = 48MHz High = 24MHz Fixed clock out selectable through SEL24-48# Clock pin of I2C circuitr y 5V tolerant Data pin for I2C circuitr y 5V tolerant Frequency Select pin, has pull-up to VDD Enables Spread Spectrum feature when LOW. Down Spread 0.5% modulation frequency =50KHz Powers down chip, active low. Internal PLL & all outputs are disabled. Halts CPUCLKs. CPUCLKT is driven LOW wheras CPUCLKC is driven HIGH when this pin is asser ted (Active LOW). Halts PCI Bus at logic "0" level when driven low. PCICLK_F is not affected by this pin 2,1 17, 16, 14, 13, 11, 10, 8 9, 15 18 20, 19 AGP (1:0) OUT 34 22 23 VDD VDD48 48MHz PWR PWR OUT SEL24-48# IN 26 27 28 24-48MHz SCLK SDATA FS2 OUT IN I/O IN 29 SPREAD# IN 30 PD# IN 31 CPU_STOP# IN 32 PCI_STOP# IN 35 RESET# OUT 46 44 SDRAM_OUT RESERVED OUT N/C 42, 39, 36 CPUCLKT (2:0) OUT 43, 40, 37 CPUCLKC (2:0) OUT 45 48 VDDSD VDDREF PWR PWR 24 XTAL_IN 14.318MHz Cr ystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Cr ystal output, has internal load cap 33pF Free Running PCI output. Not affected by the PCI_STOP# input. Real time system reset signal for watchdog tmer timeout. This signal is active low. Reference clock for SDRAM zero delay buffer Future CPU power rail "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementar y" clocks of differental pair CPU output. These open drain outputs need an external 1.5V pull_up. Power for SDRAM_OUT pin. Norminally 3.3V Power for REF, X1, X2, nominally 3.3V 0486B—02/23/04 2 ICS951403 Bit Bit 6 Bit 5 Bit 4 Bit 2 Bit 7 CPU SDRAM FS2 FS1 FS0 0 0 0 0 0 100.00 100.00 0 0 0 0 1 100.00 133.33 0 0 0 1 0 100.00 150.00 0 0 0 1 1 100.00 66.67 0 0 1 0 0 133.33 133.33 0 0 1 0 1 125.00 100.00 0 0 1 1 0 124.00 124.00 0 0 1 1 1 133.33 100.00 0 1 0 0 0 112.00 112.00 0 1 0 0 1 150.00 150.00 0 1 0 1 0 111.11 166.67 0 1 0 1 1 110.00 165.00 0 1 1 0 0 166.67 166.67 0 1 1 0 1 90.00 90.00 0 1 1 1 0 48.00 48.00 Bit 2 Bit 7:4 0 1 1 1 1 45.00 60.00 1 0 0 0 0 100.30 100.30 1 0 0 0 1 100.30 133.73 1 0 0 1 0 105.00 157.50 1 0 0 1 1 100.30 66.87 1 0 1 0 0 110.00 110.00 1 0 1 0 1 103.00 103.00 1 0 1 1 0 103.00 137.33 1 0 1 1 1 133.73 100.30 1 1 0 0 0 133.73 133.73 1 1 0 0 1 140.00 140.00 1 1 0 1 0 137.33 103.00 1 1 0 1 1 137.33 137.33 1 1 1 0 0 105.00 105.00 1 1 1 0 1 138.33 138.33 1 1 1 1 0 200.00 200.00 1 1 1 1 1 104.25 139.00 0 - Frequency is selected by hardware select, Latched Bit 3 1 - Frequency is selected by Bit , 2 7:4 Normal Bit 1 10 -- S pread Spectrum Enabled 0 R unning Bit 0 1- Tristate all outputs Description AGP PC I SEL = 0 33.33 66.67 33.33 66.67 30.00 60.00 33.33 66.67 33.33 67.67 31.25 62.50 31.00 62.00 33.33 66.67 33.60 67.20 30.00 60.00 33.33 66.67 33.00 66.00 33.33 66.67 30.00 60.00 32.00 64.00 30.00 60.00 33.43 66.87 33.43 66.87 31.50 63.00 33.43 66.87 33.00 66.00 34.33 68.67 34.33 68.67 33.43 66.87 33.43 66.87 35.00 70.00 34.33 68.67 34.33 68.67 35.00 70.00 34.58 69.17 33.33 66.67 34.75 69.50 Inputs PWD AGP SEL = 1 50.00 50.00 50.00 50.00 50.00 50.00 46.50 50.00 56.00 50.00 55.56 55.00 55.56 45.00 48.00 45.00 50.15 50.15 52.50 50.15 55.00 51.50 51.50 50.15 50.15 52.50 51.50 51.50 52.50 51.88 50.00 52.13 Spread Precentage 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 00000 Note1 0 0 0 Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. Note: PWD = Power-Up Default 0486B—02/23/04 3 ICS951403 Byte 1: Output Control Register (1= enable, 0 = disable) BIT PIN# PWD DESCRIPTION Bit 6 37 1 SEL 24/48 0 = 24MHz 1= 48MHz CPUCLKC0 Bit 5 36 1 CPUCLKT0 Bit 4 40 1 CPUCLKC1 Bit 3 39 1 CPUCLKT1 Bit 2 43 1 CPUCLKC2 Bit 1 42 1 CPUCLKT2 Bit 0 46 1 SDRAM_OUT Bit 7 24 1 Byte 2: PCI Stop Register (1= enable, 0 = disable) BIT Byte 3: CPU Free Running Control Register (1= enable, 0 = disable) PIN# PWD DESCRIPTION Bit 7 7 1 PCICLK_F Bit 6 17 1 PCICLK6 Bit 5 16 1 PCICLK5 Bit 4 14 1 PCICLK4 Bit 3 13 1 PCICLK3 Bit 2 11 1 PCICLK2 Bit 1 10 1 PCICLK1 Bit 0 8 1 PCICLK0 Byte 4: 24/48MHz Control Register (1= enable, 0 = disable) BIT PIN# PWD DESCRIPTION Bit 7 - X Reserved 7 - 1 Reserved Bit 6 - X Reserved 6 24 1 24-48MHz Bit 5 - X Reserved 5 - 1 48MHz Bit 4 - X Reserved 4 - 1 Reserved Bit 3 - 0 Reserved 3 - 1 Reserved Bit 2 - 0 CPU T/C 0 2 - 1 Bit 1 - 0 CPU T/C 1 1 - 0 Bit 0 - 0 CPU T/C 2 0 - 1 Reserved AGP frequency select 0 = 66.6MHz 1 = 50.0MHz Reserved BIT Byte 5: Clock Enable Control Register (1= enable, 0 = disable) BIT PIN# PWD BIT DESCRIPTION X Reserved 6 X FS2 Read-back 6 5 X FS1 Read-back 4 X FS0 Read-back - 3 1 1 REF1 2 2 1 REF0 1 20 1 AGP1 0 19 1 AGP0 DESCRIPTION Byte 6: Control Register (1= enable, 0 = disable) 7 7 PIN# PWD Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 0486B—02/23/04 4 PIN# PWD - 0 - 0 DESCRIPTION 5 - 0 REF strength 0 = 1X 1 = 2X 0 = CPU C1:2, T1:2 stop 1 = CPU C1:2, T1:2 free running Reserved 4 - X SPREAD# read-back 3 - X CPU_STOP# read-back 2 - X PCI_STOP# read-back 1 - X Reserved 0 - 0 AGP speed toggle Notes: 3. Bytes 7:14 not defined. ICS951403 Byte 15: CPU_SDRAM Skew Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 0 0 1 1 1 1 0 Byte 16: Slew Rate Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description SDRAM (pdel canned) Reserved CPUC0 & T0 (pdel canned) CPUC 1:2 & T 1:2 (pdel canned) Byte 17: Slew Rate Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD 1 0 1 0 1 0 1 0 Description Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCI (3:0) Slew Control PCI_F Slew Control CPUCLKC0 Slew Control CPUCLKT0 Slew Control PWD 1 0 1 0 1 0 1 0 - Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 18: Slew Rate Control Register PWD 1 0 1 0 1 0 1 0 Description PCI (4:7) Slew Control AGP1 Slew Control AGP0 Slew Control Reserved Byte 20: Slew Rate Control Register Byte 19: Slew Rate Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWD Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description 48MHz Slew Control 24, 48MHz Slew Control REF0 Slew Control REF1 Slew Control SDRAM Slew Control Notes: 1. PWD = Power on Default 0486B—02/23/04 5 PWD 1 0 1 0 1 0 1 0 Description CPUCLKC1 Slew Control CPUCLKT1 Slew Control CPUCLKC2 Slew Control CPUCLKT2 Slew Control ICS951403 VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20). 3. Read back byte 11-20 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values. 6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate. 7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See Application note for software support. 0486B—02/23/04 6 ICS951403 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN=0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN=0 V; Inputs with pull-up resistors CL = Full load IDD3.3OP Supply Current Power Down PD Input frequency Fi VDD = 3.3 V; CIN Logic Inputs Input Capacitance1 CIN Logic Inputs CINX X1 & X2 pins 1 Clk Stabilization TSTAB From VDD= 3.3 V to 1% target Freq. 1 Skew tCPU-SDRAM CPU Xover to SDRAM 1.5V 1 Skew tCPU-PCI CPU Xover to PCI 1.5V 1 Skew tCPU-AGP CPU Xover to AGP 1.5V 1 Guaranteed by design, not 100% tested in production. 0486B—02/23/04 7 MIN 2 VSS - 0.3 TYP -5 -200 12 213 0.07 14.318 27 68 186 138 MAX UNITS VDD + 0.3 V 0.8 V 5 A uA uA 240 mA 0.6 mA 16 MHz 5 pF 5 pF 45 pF 3 ms 250 ps 250 ps 500 ps ICS951403 Electrical Characteristics - REF TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output High IOH = -18mA VOH5 Voltage MIN TYP MAX 2.4 UNITS V Output Low Voltage VOL5 IOL = 18mA 0.4 V Output High Current IOH5 V OH = 2.0 V, -19 mA Output Low Current IOL5 VOL = 0.8V Rise Time Fall Time Duty Cycle tr5 tf5 dt1 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% Jitter tjcyc-cyc5 1 1 19 45 VT = 1.5 V mA 0.85 1.03 54 4 4 55 ns ns % 521 1000 ps TYP MAX UNITS Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU (Open Drain) TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 2pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output High Voltage Output Low Voltage Output Low Current Fall Time Differential voltage_AC Zo VO = Vx VOH2B Termination to Vpull_up (external) VOL2B Termination to Vpull_up (external) IOL2B VOL = 0.3V tf2B VOH = 1.2V VOL = 0.3V VDIF Note 2 VDIF Note 2 Differential voltage_DC Differential Crossover Voltage Duty Cycle Skew VX True rise to compl. Fall dt2B tsk2B VT = 50% VT = 50% Jitter, Cycle to cycle tjcyc-cyc 1 1 VT = Vx MIN Ω 1 1.2 V 0.4 18 mA 0.8 0.9 Vtpullup (external)+0 .6 Vtpullup (external)+0 .6 45 ps ps ps 1.37 1.5 V 49.3 48 55 200 % ps 130 250 ps Guaranteed by design, not 100% tested in production. 2 VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 0486B—02/23/04 8 ICS951403 Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output High 1 IOH = -11mA VOH Voltage V V 1 V OH = 2.0 V, -19 mA 1 VOL = 0.8V 1 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V IOH Output Low Current IOL Jitter 2.6 UNITS 0.4 Output High Current 1 MAX IOL = 9.4mA VOL Skew TYP 1 Output Low Voltage Rise Time Fall Time Duty Cycle MIN tr1 1 tf1 1 dt1 tsk1 tjcyc-cyc 1 mA 1.29 1.02 51.5 2 2 55 ns ns % VT = 50% 54 200 ps VT = 1.5 V 104 250 ps TYP MAX UNITS V V mA mA ns ns % ps VT = 50% 1 19 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 24MHz,48MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -18mA Output High Voltage VOH5 IOL = 18mA Output Low Voltage VOL5 Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 1 Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle dt5 VT = 1.5V VT = 1.5V Jitter, Cycle to cycle tjcyc_cyc2B 1 Guaranteed by design, not 100% tested in production. 0486B—02/23/04 9 MIN 2.4 0.4 -22 16 45 1.2 1.3 50.5 130 4 4 55 500 ICS951403 Electrical Characteristics - AGP [1:0] TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output High 1 IOH = -18mA VOH Voltage V V 1 V OH = 2.0 V, -19 mA 1 VOL = 0.8V 1 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V IOH Output Low Current IOL Jitter 2.4 UNITS 0.4 Output High Current 1 MAX IOL = 18mA VOL Skew TYP 1 Output Low Voltage Rise Time Fall Time Duty Cycle MIN tr1 1 tf1 1 dt1 tsk1 tjcyc-cyc 1 mA 0.98 0.85 48.5 1.6 1.6 55 ns ns % VT = 50% 4 250 ps VT = 1.5 V 235 500 ps TYP MAX UNITS VT = 50% 1 19 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM_OUT TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output High VOH3 IOH = -11mA Voltage MIN 2 V Output Low Voltage VOL3 IOL = 11mA 0.4 V Output High Current IOH3 V OH = 2.0 V, -12 mA Output Low Current IOL3 VOL = 0.8V Rise Time Fall Time Duty Cycle tr3 3 tf3 3 dt3 Jitter 1 3 tjcyc-cyc VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% 3 VT = 1.5 V Guaranteed by design, not 100% tested in production. 0486B—02/23/04 10 12 45 mA 0.96 0.75 49.5 1.6 1.6 55 ns ns % 235 250 ps ICS951403 General I2C serial interface information for the ICS951403 How to Write: How to Read: • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) How to Read: ICS (Slave/Receiver) Controller (Host) Start Bit Address D3(H) ACK ICS (Slave/Receiver) ACK Byte Count Dummy Command Code ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK If 7H has been written to B6 ACK Dummy Byte Count Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 ACK Byte 7 Byte 18 ACK If 12H has been written to B6 ACK If 13H has been written to B6 ACK If 14H has been written to B6 ACK Stop Bit Byte 19 ACK Byte 20 ACK Stop Bit *See notes on the following page. 0486B—02/23/04 11 Byte18 Byte 19 Byte 20 ICS951403 Brief I2C registers description for ICS951403 Programmable System Frequency Generator Register Name Functionality & Frequency Select Register Output Control Registers Byte 0 1-6 Vendor ID & Revision ID Registers 7 Byte Count Read Back Register 8 Watchdog Timer Count Register 9 Watchdog Control Registers 10 Bit [6:0] Description Output frequency, hardware / I2C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00H to this byte. Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. VCO Control Selection Bit 10 Bit [7] VCO Frequency Control Registers 11-12 Spread Spectrum Control Registers 13-14 These registers control the spread percentage amount. Group Skews Control Registers 15-16 Increment or decrement the group skew amount as compared to the initial skew. Output Rise/Fall Time Select Registers 17-20 These registers will control the output rise and fall time. Notes: 1. 2. 3. 4. 5. 6. 7. PWD Default See individual byte description See individual byte description See individual byte description 08H 10H 000,0000 0 Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0486B—02/23/04 12 ICS951403 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Fig. 1 0486B—02/23/04 13 ICS951403 CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS951403. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High) CPUCLKT CPUCLKC Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS951403. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. 0486B—02/23/04 14 ICS951403 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS951403. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS951403 internally. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-runningl) CPU_STOP# PCI_STOP# PWR_DWN# PCICLK (External) Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951403 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS951403. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state. 0486B—02/23/04 15 ICS951403 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# CPUCLKT CPUCLKC PCICLK VCO Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951403 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 0486B—02/23/04 16 ICS951403 c N L E1 INDEX AREA SYMBOL A A1 b c D E E1 e h L N α E 1 2 h x 45° D A A1 -Ce N SEATING PLANE b .10 (.004) C 48 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS951403yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0486B—02/23/04 17 D (inch) MIN .620 MAX .630 ICS951403 c N L E1 INDEX AREA E 1 2 D A A2 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 A1 -Ce VARIATIONS N SEATING PLANE b aaa C 48 D mm. MIN 12.40 D (inch) MAX 12.60 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information ICS951403yGLF-T Example: ICS XXXX y G LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0486B—02/23/04 18 MIN .488 MAX .496