IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE FAST CMOS BUFFER/CLOCK DRIVER FEATURES: • • • • • • • • • • • IDT49FCT805/A DESCRIPTION: 0.5 MICRON CMOS Technology Guaranteed low skew < 700ps (max.) Low duty cycle distortion < 1ns (max.) Low CMOS power levels TTL compatible inputs and outputs Rail-to-rail output voltage swing High drive: -24mA IOH, +64mA IOL Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output Available in SSOP and SOIC packages The 49FCT805 is a non-inverting buffer/clock driver built using advanced dual metal CMOS technology. Each bank consists of two banks of drivers. Each bank drives five output buffers from a standard TTL compatible input. These devices feature a “heart-beat” monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The 49FCT805 offers low capacitance inputs and hysteresis. Rail-to-rail output swing improves noise margin and allows easy interface with CMOS inputs. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 FUNCTIONAL BLOCK DIAGRAM OE A 5 IN A OA 1 -OA 5 5 IN B OB 1 -OB 5 OE B MON The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE SEPT. 2009 1 c 2006 Integrated Device Technology, Inc. DSC-5836/5 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION VCCA 1 ABSOLUTE MAXIMUM RATINGS(1) 20 VCC OA1 2 19 OB1 OA2 3 18 OB2 OA3 4 17 OB3 GNDA 5 16 GNDB OA4 6 15 OB4 OA5 7 14 OB5 8 13 MON OEA 9 12 OEB INA 10 11 INB NC (1) Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +60 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Input and VCC terminals. 3. Output and I/O terminals. CAPACITANCE (TA = +25OC, f = 1.0MHz) Symbol SOIC/ SSOP TOP VIEW Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF C OUT Output Capacitance VOUT = 0V 5.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. NOTE: 1. Pin 8 is not internally connected on devices with a "K" prefix in the date code. On older devices, pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at the board level. PIN DESCRIPTION Pin Names OEA, OEB Description 3-State Output Enable Inputs (Active LOW) INA, INB Clock Inputs OAn, OBn Clock Outputs MON Monitor Output FUNCTION TABLE (1) Inputs OEA, OEB INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H NOTE: 1. H = HIGH L = LOW Z = High-Impedance 2 Outputs IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C, VCC = 5V ± 5% Parameter Test Conditions(1) VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level IIH Input HIGH Current VCC = Max. VI = 5.5V IIL Input LOW Current VCC = Max. Off State (Hi-Z) Output Current VCC = Max. Symbol IOZH IOZL Min. Typ.(2) Max. Unit 2 — — V — — 0.8 V — — ±1 µA VI = GND — — ±1 µA VO = VCC — — ±1 µA VO = GND — — ±1 VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V IOS Short Circuit Current VCC = Max., VO = GND(3) –60 –120 — mA — VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC IOH = –32µA VHC VCC VCC = Min. IOH = –300µA VHC VCC — VIN = VIH or VIL IOH = –15mA 3.6 4.3 — IOH = –24mA 2.4 3.8 — VCC = 3V, VIN = VLC or VHC IOL = 300µA — GND VLC — GND VLC V VOL Output LOW Voltage VCC = Min. IOL = 300mA VIN = VIH or VIL IOL = 64mA — 0.3 0.55 VH Input Hysteresis for all inputs — — 200 — mV ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 3 V IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD Test Conditions(1) Parameter Quiescent Power Supply Current VCC = Max. TTL Inputs HIGH VIN = 3.4V(3) Dynamic Power Supply Current(4) VCC = Max. VIN = VCC Outputs Open VIN = GND Min. Typ.(2) Max. Unit — 1 2.5 mA — 0.15 0.2 mA/MHz — 1.5 2.5 — 2 3.8 — 4.1 6 — 5.1 8.5 OEA = OEB = GND 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. VIN = VCC Outputs Open VIN = GND fO = 10MHz 50% Duty Cycle VIN = 3.4V OEA = OEB = VCC VIN = GND Mon. Output Toggling VCC = Max. VIN = VCC Outputs Open VIN = GND (5) fO = 2.5MHz 50% Duty Cycle VIN = 3.4V OEA = OEB = GND VIN = GND Eleven Outputs Toggling NOTES: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at VCC = 5V, +25°C ambient. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 4 (5) mA IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) FCT805 FCT805A Conditions(2) Min. Max. Min. Max. Unit CL = 50pF RL = 500Ω 1.5 5.6 1.5 5.3 ns Output Rise Time Output Fall Time — — 1.5 1.5 — — 1.5 1.5 ns ns tSK(O) Output skew: skew between outputs of all banks of same package (inputs tied together) — 0.7 — 0.7 ns tSK(P) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) — 1 — 1 ns tSK(PP) Part-to-part skew: skew between outputs of different — 1.5 — 1.5 ns Symbol tPLH tPHL tR tF Parameter Propagation Delay INA to OAn, INB to OBn packages at same power supply voltage, tPZL temperature, package type and speed grade Output Enable Time 1.5 8 1.5 8 ns tPZH tPLZ OEA to OAn, OEB to OBn Output Disable Time 1.5 7 1.5 7 ns tPHZ OEA to OAn, OEB to OBn NOTES: 1. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 2. See test circuits and waveforms. 5 IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION Test Switch Disable LOW Enable LOW Closed Disable HIGH Enable HIGH GND V CC 7V 500 Pulse Generator V IN V OUT D.U.T. 50pF DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500 RT CL Test Circuits for All Outputs 3V 3V 1.5V INPUT 1.5V 0V INPUT t PHL tP LH 0V t PLH 1 t PLH 1 V OH V OH 2.0V 0.8V OUTPUT tR 1.5V 1.5V OUTPUT 1 V OL V OL tSK (o) tSK (o) tF V OH 1.5V Package Delay OUTPUT 2 V OL tPHL2 tPLH2 3V tSK (o) = t PLH2 - tPLH1 or t PHL2 - tPHL1 1.5V INPUT Output Skew 0V tPLH t PHL V OH 1.5V OUTPUT 3V V OL 1.5V tSK (p) = t PHL - t PLH INPUT Pulse Skew - tSK(P) tPLH1 t PHL1 V OH PACKAGE 1 OUTPUT DISABLE ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW t PLZ 3.5V SW ITCH CLO SED OUTPUT NORMALLY HIGH SW ITCH O PEN 1.5V 0V tSK(pp) PACKAGE 2 OUTPUT 0V VO L tSK (pp) = tPLH2 - t PLH1 t PHL2 or t PH L2 - t PHL1 Part-to-Part Skew - tSK(PP) 0.3V V OH 0V NOTE: 1. Package 1 and Package 2 are same device type and speed grade. Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6 V OH 1.5V t PLH 2 t PHZ tP ZH 1.5V VO L tSK (pp) 3V 1.5V 3.5V 0.3V V OL 1.5V 0V IDT49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT49FCT XXXX Device Type X Package X Process Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) SO SOG PY PYG Small Outline IC SOIC - Green Shrink Small Outline Package SSOP - Green 805 805A Fast CMOS Buffer/Clock Driver NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: [email protected]