FAST CMOS OCTAL D REGISTERS (3-STATE) IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT IDT54/74FCT534T/AT/CT IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT Integrated Device Technology, Inc. FEATURES: DESCRIPTION • Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT374T/FCT534T/FCT574T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 48mA IOL) • Features for FCT2374T/FCT2574T: – Std., A, and C speed grades – Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) – Reduced system switching noise The FCT374T/FCT2374T, FCT534T and FCT574T/ FCT2574T are 8-bit registers built using an advanced dual metal CMOS technology. These registers consist of eight Dtype flip-flops with a buffered common clock and buffered 3state output control. When the output enable (OE) input is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the high-impedance state. Input data meeting the set-up and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-toHIGH transition of the clock input. The FCT2374T and FCT2574T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts. FUNCTIONAL BLOCK DIAGRAM FCT374/FCT2374T AND FCT574/FCT2574T D0 D1 CP D Q CP D Q D2 D3 D4 D5 D6 D7 CP CP D CP D CP D CP D CP D CP D Q Q Q Q Q Q Q2 Q3 Q4 Q5 Q6 Q7 OE Q0 Q1 2569 drw 01 FUNCTIONAL BLOCK DIAGRAM FCT534T D0 D1 D2 D3 D4 D5 D6 D7 CP CP D CP D CP D CP D CP D CP D CP D Q Q Q Q Q Q Q Q0 Q1 Q2 Q3 Q4 Q5 Q6 CP D Q OE Q7 2569 drw 02 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 6.13 AUGUST 1995 DSC-4214/5 1 IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS D7 17 D6 16 15 Q6 Q5 14 D5 13 D4 Q4 CP 4 Q1 5 Q2 6 D2 7 D3 8 Q3 GND 9 12 10 11 3 20 19 18 D7 17 D6 16 Q6 7 15 Q5 8 14 9 10 11 12 13 D5 D1 4 Q1 5 Q2 6 D2 D3 2 1 L20-2 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW Q4 18 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 D4 Q7 CP VCC 19 D0 20 2 3 Q3 D0 D1 1 GND OE Q0 Q0 OE INDEX VCC Q7 IDT54/74FCT374T 2569 drw 03 LCC TOP VIEW 7 D6 8 D7 GND 9 12 Q7 10 11 CP D3 5 D4 6 3 2 Q3 Q4 Q5 Q6 D2 4 D3 5 D4 6 D5 D6 7 1 Q0 20 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 L20-2 8 9 10 11 12 13 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW Q7 Q6 D5 4 OE Q0 Q1 Q2 P20-1 18 D20-1 17 SO20-2 16 SO20-7 15 SO20-8 14 & E20-1 13 D1 D2 CP 19 D0 2 3 INDEX VCC GND 20 D1 1 D7 OE D0 VCC IDT54/74FCT574T 2569 drw 04 LCC TOP VIEW Q0 D0 2 3 18 Q7 D7 D1 4 17 D6 Q1 5 Q2 D2 6 D3 8 Q3 GND P20-1 D20-1 SO20-2 SO20-8 & E20-1 16 Q6 15 14 Q5 D5 13 D4 9 12 10 11 Q4 CP 7 3 2 D1 4 Q1 5 Q2 D2 D3 6 1 VCC Q7 20 19 18 17 D7 D6 16 Q6 7 15 8 14 9 10 11 12 13 Q5 D5 L20-2 CP Q4 D4 VCC 19 GND 20 Q3 1 OE D0 INDEX Q0 OE IDT54/74FCT534T 2569 drw 05 LCC TOP VIEW DIP/SOIC/QSOP/CERPACK TOP VIEW 6.13 2 IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Pin Names DN CP Description D flip-flop data inputs Clock Pulse for the register. Enters data on LOW-to-HIGH transition. 3-state outputs, (true) QN QN OE 3-state outputs, (inverted) Active LOW 3-state Output Enable input 2569 tbl 01 FUNCTION TABLE(1) 534 Inputs Function HI-Z LOAD REGISTER OE H H L L H H Outputs Internal 374/574 Outputs Internal CP DN QN QN QN QN L H X X L H L H Z Z H L Z Z NC NC L H L H Z Z L H Z Z NC NC H L H L ↑ ↑ ↑ ↑ NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance NC = No Change ↑ = LOW-to-HIGH transition 2569 tbl 02 ABSOLUTE MAXIMUM RATINGS(1) CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 Military –0.5 to +7.0 Unit V –0.5 to VCC +0.5 V –55 to +125 °C –65 to +135 °C –65 to +150 °C 0.5 W I OUT –60 to +120 mA DC Output Current –60 to +120 Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Typ. 6 VOUT = 0V 8 Max. Unit 10 pF 12 NOTE: 1. This parameter is measured at characterization but not tested. pF 2569 lnk 04 2569 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 6.13 3 IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, V CC = 5.0V ± 10% Symbol VIH VIL Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level Input LOW Level Input HIGH Current (4) II L Input LOW Current (4) I OZH High Impedance Output Current II H I OZL (3-State Output Min. 2.0 Typ.(2) — Max. — Unit V Guaranteed Logic LOW Level — — 0.8 V VCC = Max. — — ±1 µA VI = 2.7V VCC = Max. pins) (4) Current (4) II Input HIGH VIK Clamp Diode Voltage VH Input Hysteresis I CC Quiescent Power Supply Current VI = 0.5V — — ±1 VO = 2.7V — — ±1 VO = 0.5V — — ±1 µA VCC = Max., VI = VCC (Max.) — — ±1 µA VCC = Min., IIN = –18mA — –0.7 –1.2 V — — 200 — mV — 0.01 1 VCC = Max., VIN = GND or VCC mA 2569 lnk 05 OUTPUT DRIVE CHARACTERISTICS FOR FCT374T/534T/574T Symbol VOH Parameter Output HIGH Voltage VOL Output LOW Voltage I OS Short Circuit Current Test Conditions(1) VCC = Min. I OH = –6mA MIL. VIN = VIH or V IL I OH = –8mA COM'L. I OH = –12mA MIL. I OH = –15mA COM'L. VCC = Min. I OL = 32mA MIL. VIN = VIH or V IL I OL = 48mA COM'L. VCC = Max., VO = GND (3) Min. 2.4 Typ.(2) 3.3 Max. — Unit V 2.0 3.0 — V — 0.3 0.5 V –60 –120 –225 mA 2569 lnk 06 OUTPUT DRIVE CHARACTERISTICS FOR FCT2374T/2574T Symbol I ODL Parameter Output LOW Current Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) Min. 16 Typ.(2) 48 Max. — Unit mA I ODH Output HIGH Current VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3) –16 –48 — mA VOH Output HIGH Voltage 2.4 3.3 — V VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or V IL — 0.3 0.50 V I OH = –12mA MIL. I OH = –15mA COM'L. I OL = 12mA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = –55°C. 6.13 2569 lnk 07 4 IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. VIN = VCC VIN = GND Outputs Open OE = GND One Input Toggling 50% Duty Cycle VCC = Max. VIN = VCC VIN = GND Outputs Open fCP = 10MHz 50% Duty Cycle OE = GND VIN = 3.4 fi = 5MHz VIN = GND 50% Duty Cycle One Bit Toggling VCC = Max. VIN = VCC VIN = GND Outputs Open fCP = 10MHz 50% Duty Cycle OE = GND VIN = 3.4 Eight Bits Toggling VIN = GND fi = 2.5MHz 50% Duty Cycle Min. — Typ.(2) 0.5 Max. 2.0 Unit mA FCTxxxT — 0.15 0.25 mA/ MHz FCT2xxxT — 0.06 0.12 FCTxxxT — 1.5 3.5 FCT2xxxT — 0.6 2.2 FCTxxxT — 2.0 5.5 1.1 4.2 FCT2xxxT FCTxxxT — 3.8 7.3 (5) FCT2xxxT — 1.5 4.0 (5) FCTxxxT — 6.0 16.3 (5) FCT2xxxT — 3.8 13.0 (5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6.13 mA 2569 tbl 08 5 IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW FCT374T/534T/574T FCT374AT/534AT/574AT FCT2374T/2574T Com'l. Mil. FCT2374AT/2574AT Com'l. Mil. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. 2.0 10.0 2.0 11.0 2.0 6.5 2.0 7.2 Unit ns 1.5 12.5 1.5 14.0 1.5 6.5 1.5 7.5 ns Output Disable Time 1.5 8.0 1.5 8.0 1.5 5.5 1.5 6.5 ns Set-up Time HIGH or LOW, DN to CP Hold Time HIGH or LOW, DN to CP CP Pulse Width HIGH or LOW 2.0 — 2.0 — 2.0 — 2.0 — ns 1.5 — 1.5 — 1.5 — 1.5 — ns 7.0 — 7.0 — 5.0 — 6.0 — ns Parameter Propagation Delay CP to QN(3) Output Enable Time Conditions(1) CL = 50pF RL = 500Ω 2569 tbl 09 FCT374CT/534CT/574CT FCT2374CT/2574CT Com'l. Mil. Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW FCT374DT/574DT Com'l. Mil. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. 2.0 5.2 2.0 6.2 2.0 4.2 — — Unit ns 1.5 5.5 1.5 6.2 1.5 4.8 — — ns Output Disable Time 1.5 5.0 1.5 5.7 1.5 4.0 — — ns Set-up Time HIGH or LOW, DN to CP Hold Time HIGH or LOW, DN to CP CP Pulse Width HIGH or LOW(4) 2.0 — 2.0 — 2.0 — — — ns 1.5 — 1.5 — 1.0 — — — ns 5.0 — 6.0 — 3.0 — — — ns Parameter Propagation Delay CP to QN(3) Output Enable Time Conditions(1) CL = 50pF RL = 500Ω NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. ON for FCT374/2374T and FCT574/2574T, ON for FCT534T. 4. This parameter is guaranteed but not tested. 2569 tbl 10 6.13 6 IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC 500Ω V OUT VIN Pulse Generator Test Switch Open Drain Disable Low Closed 7.0V Enable Low D.U.T. Open All Other Tests 50pF RT DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2569 drw 06 SET-UP, HOLD AND RELEASE TIMES DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2569 drw 08 2569 drw 07 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPLZ tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 2569 drw 09 SWITCH OPEN 1.5V 0V 3.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2569 drw 10 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6.13 7 IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX X FCT Family Temp. Range XXXX Device Type X Process X Package Blank B Commercial MIL-STD-883, Class B P D SO L E PY Q Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Shrink Small Outline Package Quarter-size Small Outline Package 374T 574T 534T 374AT 574AT 534AT 374CT 574CT 534CT 374DT 574DT Non-Inverting Octal D Register Non-Inverting Octal D Register Inverting Octal D Register Blank 2 High Drive Balanced Drive 54 74 –55°C to +125°C 0°C to +70°C 2569 drw 11 6.13 8