ETC IDT74LVCH32373ABF

IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVCH32373A
3.3V CMOS 32-BIT
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
DESCRIPTION:
FEATURES:
–
–
–
–
–
–
–
–
–
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.8mm pitch LFBGA package, 96 balls
Extended commercial range of -40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
The LVCH32373A 32-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal
for temporary storage of data. The device can be used for implementing
memory address latches, I/O ports, and bus drivers. The Output Enable
and Latch Enable controls are organized to operate each device as four 8bit latches, two 16-bit latches, or one 32-bit latch. Flow-through organization
of signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
All pins of the LVCH32373A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
Drive Features for LVCH32373A:
– Balanced Output Drivers: ±24mA
– Reduced system switching noise
The LVCH32373A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
APPLICATIONS:
The LVCH32373A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1 OE
A3
3 OE
1 LE
A4
3 LE
D1
A5
D
3D 1
J3
J4
J5
D
A2
J2
1Q 1
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
2 OE
2 LE
2D 1
H3
4 OE
H4
4 LE
E5
D
4D 1
T3
T4
N5
D
E2
C
3Q 1
C
N2
2Q 1
C
TO SEVEN OTHER CHANNELS
4Q 1
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
JANUARY 2000
1
c
2000
Integrated Device Technology, Inc.
DSC-4765/-
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
1D 2
1D 4
1D 6
1D 8
2D 2
2D 4
2D 6
2D 7
3D 2
3D 4
3D 6
3D 8
4D 2
4D 4
4D 6
4D 7
5
1D 1
1D 3
1D 5
1D 7
2D 1
2D 3
2D 5
2D 8
3D 1
3D 3
3D 5
3D 7
4D 1
4D 3
4D 5
4D 8
4
1 LE
GND
V CC
GND
GND
V CC
GND
2 LE
3 LE
GND
V CC
GND
GND
V CC
GND
4 LE
3
1O E
GND
V CC
GND
GND
V CC
GND
2O E
3O E
GND
V CC
GND
GND
V CC
GND
4O E
2
1Q 1
1Q 3
1Q 5
1Q 7
2Q 1
2Q 3
2Q 5
2Q 8
3Q 1
3Q 3
3Q 5
3Q 7
4Q 1
4Q 3
4Q 5
4Q 8
1
1Q 2
1Q 4
1Q 6
1Q 8
2Q 2
2Q 4
2Q 6
2Q 7
3Q 2
3Q 4
3Q 6
3Q 8
4Q 2
4Q 4
4Q 6
4Q 7
A
B
C
D
E
F
G
K
L
J
H
N
M
P
R
T
32373
LFBGA
TOP VIEW
96 BALL LFBGA PACKAGE LAYOUT
1.5 mm Max.
1.4 mm Nom.
1.3 mm Min.
0.8mm
6
5
TOP VIEW
4
3
2
1
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
J
J
K
L
M
N
P
R
T
K
L
M
N
P
R
T
1
2
3
5.5mm
4
5
6
13.5mm
c
2
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
PIN DESCRIPTION
(1)
Symbol
VTERM
Description
Terminal Voltage with Respect to GND
Max.
– 0.5 to +6.5
Unit
V
Pin Names
xDx
TSTG
Storage Temperature
– 65 to +150
°C
xLE
IOUT
DC Output Current
– 50 to +50
mA
xOE
Output Enable Inputs (Active LOW)
IIK
IOK
ICC
Continuous Clamp Current,
VI < 0 or VO < 0
Continuous Current through
– 50
mA
xQx
3-State Outputs
±100
mA
ISS
each VCC or GND
Description
Data Inputs(1)
Latch Enable Inputs (Active HIGH)
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
LVC Link
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
FUNCTION TABLE (EACH 9-BIT SECTION)
CAPACITANCE (TA = +25 C, f = 1.0MHz)
o
Symbol
CIN
Parameter(1)
Input Capacitance
Conditions
VIN = 0V
Typ.
4.5
Max.
6
Unit
pF
COUT
Output
Capacitance
I/O Port
Capacitance
VOUT = 0V
6.5
8
pF
VIN = 0V
6.5
8
pF
CI/O
Inputs
xLE
xOE
Outputs
xQx
H
H
L
H
L
H
L
L
X
X
H
Z
X
L
L
Q0
xDx
(1)
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
Q0 = Output level of Q before the indicated steady-state conditions
were established.
LVC Link
NOTE:
1. As applicable to the device type.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Bus-Hold Input Sustain Current
VCC = 3.0V
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHH
IBHL
IBHHO
Bus-Hold Input Overdrive Current
Min.
– 75
Typ.(2)
—
Max.
—
VI = 0.8V
75
—
—
VI = 1.7V
—
—
—
VI = 0.7V
—
—
—
VI = 0 to 3.6V
—
—
± 500
Test Conditions
VI = 2.0V
VCC = 3.6V
Unit
µA
µA
µA
IBHLO
LVC Link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V CC = 3.3V, +25°C ambient.
3
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40OC to +85OC
Symbol
VIH
VIL
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
VCC = 2.3V to 2.7V
Min.
1.7
Typ.(1)
—
Max.
—
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Test Conditions
Unit
V
V
IIH
IIL
IOZH
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
µA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = – 18mA
—
– 0.7
– 1.2
V
VH
Input Hysteresis
VCC = 3.3V
—
100
—
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
—
—
10
µA
3.6 ≤ VIN ≤ 5.5V(2)
—
—
10
∆ICC
Quiescent Power Supply
Current Variation
—
—
500
One input at VCC - 0.6V
other inputs at VCC or GND
µA
LVC Link
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
VOL
Parameter
Output HIGH Voltage
Output LOW Voltage
VCC
Test Conditions(1)
= 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
VCC = 2.3V
IOH = – 12mA
Min.
VCC – 0.2
Max.
—
2
—
1.7
—
VCC = 2.7V
2.2
—
VCC = 3.0V
2.4
—
VCC = 3.0V
IOH = – 24mA
2.2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3.0V
IOL = 24mA
—
0.55
Unit
V
V
LVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
4
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
CPD
Parameter
Power Dissipation Capacitance per Latch Outputs enabled
CPD
Power Dissipation Capacitance per Latch Outputs disabled
SWITCHING CHARACTERISTICS
Test Conditions
CL = 0pF, f = 10Mhz
Unit
pF
12
pF
(1)
VCC = 2.7V
Symbol
Typical
78
Parameter
VCC = 3.3V ± 0.3V
Min.
1.5
Max.
4.9
Min.
1.6
Max.
4.2
Unit
ns
2
5.3
2.1
4.6
ns
1.5
5.7
1.3
4.7
ns
1.5
6.3
2.5
5.9
ns
1.7
—
1.7
—
ns
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
xDx to xQx
Propagation Delay
xLE to xQx
Output Enable Time
xOE to xQx
Output Disable Time
xOE to xQx
Set-up Time HIGH or LOW, xDx to xLE
tH
Hold Time HIGH or LOW, xDx after xLE
1.2
—
1.2
—
ns
tW
xLE Pulse Width HIGH
3.3
—
3.3
—
ns
tSK(o)
Output Skew(2)
—
—
—
500
ns
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
VLOAD
VCC(1)= 3.3V ±0.3V
VCC(1) = 2.7V
VCC(2)= 2.5V ±0.2V Unit
2 x Vcc
V
6
6
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
VCC / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
V IN
V IH
VT
0V
DISABLE
ENABLE
GND
tPZL
OUTPUT
SW ITCH
NOR MALLY
CLO SED
LOW
tPZH
OUTPUT SW ITCH
NOR MALLY
O PEN
HIGH
500 Ω
CL
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
V LOAD/2
V LOAD/2
VT
V OL+ V LZ
V OL
tPHZ
VT
V OH
V OH- V HZ
0V
0V
LVC Link
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
DATA
INPUT
Switch
VLOAD
tSU
tH
tR EM
ASYNCH RONOUS
CON TROL
Open
SYNC HRONOUS
CON TROL
LVC Link
tSU
V IH
VT
0V
tH
LVC Link
V IH
PULSE WIDTH
VT
0V
tPHL1
V IH
VT
0V
V IH
VT
0V
V IH
VT
0V
TIMIN G
INPUT
GND
OUTPUT SKEW - tsk (x)
0V
tPLZ
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
V IH
VT
CON TROL
INPUT
V OUT
tPLH1
tPHL
ENABLE AND DISABLE TIMES
D.U .T.
RT
INPUT
tPLH
V OH
VT
VOL
LVC Link
V LOAD
Open
Pulse (1, 2)
Generator
tPHL
OPPOSITE PHASE
INPUT TRANSITION
TEST CIRCUITS FOR ALL OUTPUTS
500 Ω
tPLH
OUTPUT
LVC Link
V CC
V IH
VT
0V
SAM E PHAS E
INPUT TRANSITION
V OH
OUTPU T 1
tSK (x)
tSK (x)
LOW -HIGH -LOW
PULSE
VT
V OL
tW
V OH
VT
V OL
OUTPU T 2
VT
HIGH -LOW -HIGH
PULSE
VT
LV C Link
tPLH2
tPHL2
tSK (x) = t PLH2 - tPLH1 or tPHL2 - tPHL1
LV C Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74LVCH32373A
3.3V CMOS 32-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
LVC
Temp. Range
X
XX
XXXX
XX
Bus-Hold
Family
Device Type
Package
BF
Low-Profile Fine Pitch Ball Grid Array (BF96-1 )
373A
32-Bit Transparent D-Type Latch
with 5V Tolerant I/O
32
32- Bit Bus Density with Resistors, ±24mA
H
Bus-hold
74
-40°C to +85°C
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