IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH162721 DESCRIPTION: FEATURES: This 20-bit flip-flop is built using advanced dual metal CMOS technology. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. – – – 0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages – Extended commercial range of – 40°C to + 85°C – VCC = 3.3V ± 0.3V, Normal Range – VCC = 2.7V to 3.6V, Extended Range – VCC = 2.5V ± 0.2V – CMOS power levels (0.4µ W typ. static) – Rail-to-Rail output swing for increased noise margin Drive Features for ALVCH162721: – Balanced Output Drivers: ±12mA – Low switching noise A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or a high-impedance state. In the highimpedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH162721 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. APPLICATIONS: • 3.3V High Speed Systems • 3.3V and lower voltage computing systems The ALVCH162721 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. Functional Block Diagram OE CLK CLKEN 1 56 29 CE C1 D1 55 2 Q1 1D To 19 Other Channels EXTENDED COMMERCIAL TEMPERATURE RANGE MARCH 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4566/- IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATING OE 1 56 CLK Q1 2 55 D1 Q2 3 54 D2 GND 4 53 GND Q3 5 52 D3 Q4 6 51 D4 V CC 7 50 V CC Q5 8 49 D5 Q6 9 48 D6 Q7 10 47 D7 GND 11 46 GND Q8 12 45 D8 Q9 13 44 14 Q 11 15 SO56-1 SO56-2 43 SO56-3 42 D9 Q 10 Q 12 16 41 D 12 Q 13 17 40 D 13 GND 18 39 GND Q 14 19 38 D 14 Q 15 20 37 D 15 Q 16 21 36 D 16 V CC 22 35 V CC Q 17 23 34 D 17 Q 18 24 33 D 18 GND Symbol VTERM(2) 25 32 26 31 D 19 Q 20 27 30 D 20 NC 28 29 CLKEN Unit V – 0.5 to VCC + 0.5 – 65 to + 150 V IOUT DC Output Current – 50 to + 50 mA IIK ± 50 mA IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 – 50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA NEW16link CAPACITANCE (TA = +25oC, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 5 Max. 7 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 7 9 pF VIN = 0V 7 9 pF CI/O NEW16link NOTE: 1. As applicable to the device type. FUNCTION TABLE (each flip-flop)(1) Inputs SSOP/ TSSOP/TVSOP TOP VIEW PIN DESCRIPTION OE Pin Names Description 3–State Output Enable Input (Active LOW) Dx Data Inputs Qx 3-State Outputs CLK Clock Input CLKEN Clock Enable Input (Active LOW) NC No Internal Connection °C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. D 11 Q 19 Max. – 0.5 to + 4.6 TSTG Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature VTERM(3) D 10 GND (1) Dx Output Qx X X Q0 ↑ H H L L L or H X Q0 X X Z OE CLKEN CLK L H L L L L ↑ L L H X NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH Transition Q0 = Output level before the indicated steady-state input conditions were established. (1) NOTE: 1. These pins have “Bus-Hold.” All other pins are standard inputs, outputs, or I/Os. 2 IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = – 40° C to +85° C Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 2 — — VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 ±5 IIH Input HIGH Current IIL IOZH IOZL (3-State Output pins) VIK Clamp Diode Voltage VH Input Hysteresis ICCL ICCH ICCZ ∆ICC Test Conditions Min. 1.7 Typ.(1) — Symbol VIH Max. — Unit V V VCC = 3.6V VI = VCC — — µA Input LOW Current VCC = 3.6V VI = GND — — ±5 High Impedance Output Current VCC = 3.6V VO = VCC — — ± 10 µA VO = GND — — ± 10 µA VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VCC = 3.3V — 100 — mV VCC = 3.6V VIN = GND or VCC — 0.1 40 µA Quiescent Power Supply Current Quiescent Power Supply Current Variation One input at VCC − 0.6V, other inputs at VCC or GND — — 750 µA NEW16link NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current VCC = 3.0V Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 75 — — VI = 0.8V VCC = 2.3V IBHL IBHHO Max. — Min. – 75 IBHL IBHH Typ.(2) — Test Conditions VI = 2.0V VCC = 3.6V VI = 1.7V – 45 — — VI = 0.7V 45 — — VI = 0 to 3.6V — — ± 500 Unit µA µA µA IBHLO NEW16link NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.7V VCC = 3.0V VOL Output LOW Voltage Min. VCC – 0.2 Max. — IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — IOH = – 4mA 2.2 — IOH = – 8mA 2 — IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 VCC = 2.7V VCC = 3.0V IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 Unit V V NEW16link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical 55 Typical 59 46 49 Test Conditions CL = 0pF, f = 10Mhz Unit pF pF SWITCHING CHARACTERISTICS (1) VCC = 2.5V ± 0.2V Symbol fMAX Parameter VCC = 2.7V VCC = 3.3V ± 0.3V Min. 150 Max. — Min. 150 Max. — Min. 150 Max. — Unit MHz 1 6.7 — 6.2 1 5.3 ns 1 7.2 — 7 1 5.8 ns 1 6.3 — 5.4 1 5 ns 4 — 3.6 — 3.1 — ns 3.4 — 3.1 — 2.7 — ns tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay CLK to Qx Output Enable Time OE to Qx Output Disable Time OE to Qx Setup Time, data before CLK↑ tSU Setup Time CLKEN before CLK↑ tH Hold Time, data after CLK↑ 0 — 0 — 0 — ns tH Hold Time, CLKEN after CLK↑ 0 — 0 — 0 — ns tW Pulse Width, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns tSK(o) Output Skew(2) — — — — — 500 ps NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V 6 6 2 x Vcc VIH 2.7 2.7 Vcc V SAM E PHAS E INPUT TRANSITION VT 1.5 1.5 Vcc / 2 V OUTPUT VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 Unit V 30 tPLH tPH L tPLH tPH L V IH VT 0V V OH VT V OL V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF NEW16link ALV C Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC 500 Ω (1, 2) V IN CONTROL INPUT GND tPZL V OU T Pulse Generator D.U.T. OUTPUT SW ITCH NORM ALLY CLOSE D LOW tPZH OUTPUT SW ITCH NORM ALLY OPEN HIGH 500 Ω RT DISABLE ENABLE Open CL ALV C Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. V LOAD /2 V LOAD /2 VT V LZ V OL tPH Z VT V OH V HZ 0V 0V SET-UP, HOLD, AND RELEASE TIMES DATA INPUT Switch VLOAD tS U tH tR EM ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL Open tS U tH NEW16link INPUT TSK ALV C Link (x) V IH VT 0V tPH L1 tPLH1 PULSE WIDTH V OH OUTPUT 1 tSK (x) V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V TIMING INPUT GND OUTPUT SKEW - 0V ALV C Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests tPLZ V IH VT LOW -HIGH-LOW PULSE VT V OL tSK (x) tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT ALV C Link tPLH2 tPH L2 tSK (x) = t PLH2 - tP LH1 or tPH L2 - tP HL1 ALV C Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVCH162721 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX X XXX XXX XX Bus-Hold Family Device Type Package ALVC Temp. Range CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink S mall O utline Package (S O56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 721 20-Bit Flip-Flop with 3-State Outputs 162 Double-Density with Resistors, ±12m A H Bus-Hold 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6