IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR DESCRIPTION: FEATURES: IDTCV115C is a 56 pin clock device, complying the latest Intel CK410 requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. • • • • • • One high precision N and SSC programmable PLL for SRC/PCI One high precision N and SSC programmable PLL for CPU One high precision SSC programmable PLL for SATA One high precision PLL for 96MHz/48MHz Band-gap circuit for differential outputs Support multiple spread spectrum modulation, down and center • Support SMBus block read/write, index read/write • Selectable output strength for REF, PCI, and USB48MHz • Available in SSOP package KEY SPECIFICATION: • • • • CPU/SRC CLK cycle to cycle jitter < 85ps SATA CLK cycle to cycle jitter < 85ps Static PLL frequency divide error < 114 ppm Static PLL frequency divide error for 48MHz < 5 ppm FUNCTIONAL BLOCK DIAGRAM SATA PLL SCC Programmable SRC4 - SATA SATA/ PCI[4:0], PCIF[2:0] PCI/ PCIEX PLL SCC N Programmable 14.318MHz Osc PCIE/ SRC[6:5] [3:1] CPU_ITP/ SRC7 MUX CPU PLL SCC N Programmable Host/ CPU[1:0] USB48 48MHz/ Fixed PLL No SCC DOT96 96MHz/ OUTPUT TABLE CPU CPU_ITP/SRC SRC SATA PCI/PCIF REF DOT96 48MHz 2 1 5 1 8 1 1 1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2004 1 © 2004 Integrated Device Technology, Inc. DSC - 6520/10 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION TEST MODE SELECT(1) If TEST_SEL sampled above 2V at VTT_PWRGD active LOW Pin38 (test_mode) 1 0 VDD_PCI 1 56 PCI1 VSS_PCI 2 55 PCI0 PCI2 3 54 FS_A PCI3 4 53 VDD_suspend PCI4 5 52 REF0 VSS_PCI 6 51 VSS_REF VDD_PCI 7 50 XTAL_IN PCIF0/ITP_EN 8 49 XTAL_OUT PCIF1 9 48 VDD_REF PCIF2 10 47 SCL* VDD_48 11 46 SDA* USB48MHz 12 45 CPUT0 VSS_48 13 44 CPUC0 CPU REF/N Hi-Z SRC REF/N Hi-Z PCI/F REF/N Hi-Z REF REF Hi-Z DOT96 REF/N Hi-Z USB REF/N Hi-Z NOTE: 1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N. ITP_EN ITP_EN 1 0 DOT_96 14 43 VDD_CPU DOT_96# 15 42 CPUT1 **VTT_PWRGD#/PWRDWN 16 41 CPUC1 SRCT1 17 40 VSS_CPU SRCC1 18 39 IREF VDD_SRC 19 38 FS_B/Test_Mode VSS 20 37 FS_C/Test _Sel SRCT2 21 36 CPU2_ITP/SRCT7 SRCC2 22 35 CPU2_ITP/SRCC7 SRCT3 23 34 VDD_SRC SRCC3 24 33 SRCT6 VSS_GND 25 32 SRCC6 SRCT4_SATA 26 31 SRCT5 SRCC4_SATA 27 30 SRCC5 VDD_SRC 28 29 VSS_SRC pin 38 CPUC2_ITP SRCC7 pin 39 CPUT_ITP SRCT7 * = ~ 130KΩ internal pull-up. ** = ~ 130KΩ internal pull-down. SSOP TOP VIEW HW FREQUENCY SELECTION TABLE FSC, B, A CPU SRC4_SATA SRC[3:1], SCR[7:5] PCI USB DOT REF 101 100 100 100 33.3 48 96 14.318 001 133 100 100 33.3 48 96 14.318 011 166 100 100 33.3 48 96 14.318 010 200 100 100 33.3 48 96 14.318 000 266 100 100 33.3 48 96 14.318 100 333 100 100 33.3 48 96 14.318 110 400 100 100 33.3 48 96 14.318 111 Reserve 100 100 33.3 48 96 14.318 2 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VDD _PCI VSS_PCI PCI2 PCI3 PCI4 VSS_PCI VDD _PCI PCIF0/ITP_EN PCIF1 PCIF2 VDD_48 USB48 VSS_48 DOT_96T DOT_96C **VTT_PWRGD#/PWRDWN Type PWR GND OUT OUT OUT GND PWR I/0 OUT OUT PWR OUT GND OUT OUT I/O 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SRCT1 SRCC1 VDD_SRC VSS SRCT2 SRCC2 SRCT3 SRCC3 VSS SRCT4_SATA SRCC4_SATA VDD_SRC VSS_SRC SRCC5 SRCT5 SRCC6 SRCT6 VDD_SRC CPUC2_ITP/ SRCC7 CPUT2_ITP/ SRCT7 FS_C/Test_Sel FS_B/ Test_Mode IREF VSS CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 *SDA OUT OUT PWR GND OUT OUT OUT OUT GND OUT OUT PWR GND OUT OUT OUT OUT PWR OUT OUT I/O I/O OUT GND OUT OUT PWR OUT OUT I/O Description 3.3V GND PCI clock PCI clock PCI clock GND 3.3V PCI clock, free running. CPU_2 select (sampled at VTT_PWRGD# assertion), HIGH = CPU_2. PCI clock, PCI clock, 3.3V 48MHz clock GND 96MHz 0.7V current mode differential clock output 96MHz 0.7V current mode differential clock output 3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and PCIF_0/ITP_EN inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power down (active high). Internal pull LOW. Differential Serial reference clock Differential Serial reference clock 3.3V GND Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock GND SATA clock SATA clock 3.3V GND Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock 3.3V Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7 Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7 CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted. CPU frequency selection. In test mode, 1=Hi-Z, 0=REF/N. Reference current for differential output buffer GND Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output 3.3V Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output SMBus data 3 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONT.) Pin Number Name Type 47 48 49 50 51 52 53 *SCL VDD_REF XTAL_OUT XTAL_IN VSS_REF REF0 VDD_Suspend IN PWR OUT IN GND OUT PWR 54 55 56 FS_A PCI0 PCI1 IN OUT OUT Description SMBus CLK 3.3V Xtal output Xtal input GND 14.318 MHz reference clock output In the power down mode, supply 3.3V to SM control registers, <1mA. In the normal operation, regular VDD. CPU frequency selection PCI clock PCI clock SM PROTOCOL INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N, (0 is not valid Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master INDEX BYTE READ INDEX BYTE WRITE Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), Byte 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. Setting bit[11:18] = starting address, bit[20:27] = 01h. 4 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48) Str[1:0] 00 01 10 11 Multiple loads Recommend 2L 1H 1L 2H Single loads Recommend Recommend Recommend Recommend SSC MAGNITUDE CONTROL, SMC SMC[2:0] 000 001 010 011 100 101 110 111 PCI When Byte5 bit6 = 0; otherwise, PCI = SRC frequency/3 % OFF - 0.25 - 0.5 ±0.125 ±0.25 ±0.375 ±0.5 ±0.75 PCIS[1:0] 00 01 10 11 S_CBS[1:0], H_CBS[1:0] BAND SELECTION S_CBS/H_CBS[1:0] 00 01 10 11 NS[1:0] 00 01 10 11 RESOLUTION CPU CPU CPU CPU CPU CPU CPU SRC = 100MHz mode = 133MHz mode = 166MHz mode = 200MHz mode = 266MHz mode = 333MHz mode = 400MHz mode (PCI Express) % 0.67% 0.67% 0.8% 0.67% 1.00% 0.8% 0.67% 0.67% PCI 33.33 36.36 40 S_CNS, S_PNS, H_CNS,H_PNS N SELECTION FS[C,B,A] CB1_[2:0], byte17, CPU PLL Mode selection1 CB2_[2:0], byte17, CPU PLL Mode selection2 Don’t care N Resolution (MHz) 0.666667 0.888889 1.333333 1.333333 2.666667 2.666667 2.666667 0.666667 USB48 Recommend Standard of Each CPU Mode (Band) N Selection 1 N Selection 2 Don’t care CB1[2:0]. CB2[2:0], CPU MODE SELECTION N= 150 150 125 150 100 125 150 150 CB[2:0] 101 001 011 010 000 100 110 111 5 CPU Mode, MHz 100 133 166 200 266 333 400 Reserve IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 CPUT2, CPUC2/ SRCT7, SRCC7 SRCT6, SRCC6 SRCT5, SRCC5 SRCT4, SRCC4 (SATA) SRCT3, SRCC3 SRCT2, SRCC2 SRCT1, SRCC1 REF0 2x drive Output enable Tristate Enable RW 1 Output enable Output enable Output enable Output enable Output enable Output enable 2x drive enable Tristate Tristate Tristate Tristate Tristate Tristate 1x Enable Enable Enable Enable Enable Enable 2x RW RW RW RW RW RW RW 1 1 1 1 1 1 1 Recommended 6 5 4 3 2 1 0 BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 DOT96T, DOT96C Reserve USB48 Reserve REF0 CPUT1, CPUC1 CPUT0, CPUC0 Reserve Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 0 1 1 1 0 0 0 0 BYTE 2 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 PCI4 PCI3 PCI2 PCI1 PCI0 PCIF2 PCIF1 PCIF0 Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 BYTE 3 Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function SRCT[7:1] CPUT2 CPUT1 CPUT0 DOT96T FSC latched value on power up FSB latched value on power up FSA latched value on power up SRCT PWRDWN drive mode CPUT2 PWRDWN drive mode CPUT1 PWRDWN drive mode CPUT0 PWRDWN drive mode DOT96 PWRDWN drive mode 0 Driven in power down Driven in power down Driven in power down Driven in power down Driven in power down 6 1 Type Power On Tristate in power down Tristate in power down Tristate in power down Tristate in power down Tristate R R R RW RW RW RW RW 0 0 0 0 0 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 4 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 PCIFStr1 PCIFStr0 PCIStr1 PCIStr0 REFStr1 REFStr0 48MHStr1 48MHzStr0 PCIF strength selection see SE Clock Strength table PCI strength selection see SE Clock Strength table REF strength selection see SE Clock Strength table USB48MHz0 strength selection see SE Clock Strength table 0 1 Type Power On Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 PCIPLLS PCIS1 PCI PLL select See PCIS table, only valid when Byte5 bit 6 = 0 See PCIS Table SATA PLL PCI EX PLL RW 0 During the Power Down Reset SM to default RW RW RW 0 0 1 RW RW RW 0 1 0 Type Power On 0 0 0 1 0 0 1 1 BYTE 5 4 3 PCIS0 SM control registers contents Power Down mode SATA_SMC2 SATA_SMC1 SATA_SMC0 SATA PLL spread spectrum magnitude control select see SMC table Bit Output(s) Affected Description / Function 7 WDHRB 6 WDSRB 5 SRC_SMC2 4 SRC_SMC1 Hard Alarm read back, reset by WD disable Soft Alarm read back, rest by WD disable SRC(PCIEXpress) PLL spread spectrum magnitude control select see SMC table 3 2 1 0 SRC_SMC0 CPU_SMC2 CPU_SMC1 CPU_SMC0 2 1 0 SM contents have no change BYTE 6 0 1 R R CPU PLL spread spectrum control magnitude select see SMC table 7 RW 0 RW 1 RW RW RW RW 0 1 0 0 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 7 Bit Output(s) Affected 7 6 5 4 3 2 1 0 Description / Function 0 1 Type Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID Power On 0 0 0 0 0 1 0 1 BYTE 8 Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 1 1 1 1 Type Power On RW RW RW RW RW RW RW RW 0 0 0 Type Power On RW RW RW RW RW RW RW RW 1 0 0 1 0 1 1 0 BYTES 9 - 16 ARE DUMMY BITES BYTE 17 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 CB1_2 CB1_1 CB1_0 CPU PLL Mode Selection 1 See CPU Mode Selection table CB2_2 CB2_1 CB2_0 CN1_8, MSB CPU PLL Mode Selection 2 See CPU Mode Selection table Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 CN1_7 CN1_6 CN1_5 CN1_4 CN1_3 CN1_2 CN1_1 CN1_0, LSB CPU PLL N selection 1 0 1 CPU PLL N selection 1 0 0 0 0 BYTE 18 0 8 1 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 19 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 CN2_8, MSB CN2_7 CN2_6 CN2_5 CN2_4 CN2_3 CN2_2 CN2_1 CPU N selection 2 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 CN2_0, LSB CPU N selection 2 0 1 Type Power On 0 1 0 0 1 0 1 1 BYTE 20 0 1 Type Power On 0 PN1_8, MSB PN1_7 RW RW 0 1 Type Power On RW 0 RW RW RW RW RW RW RW 0 1 0 1 1 0 0 Type Power On RW 1 RW RW RW RW RW RW RW 0 0 1 0 1 1 0 BYTE 21 Bit Output(s) Affected Description / Function 7 PN1_6 SRC PLL (PCI Express) N Selection 1 6 5 4 3 2 1 0 PN1_5 PN1_4 PN1_3 PN1_2 PN1_1 PN1_0, LSB PN2_8, MSB 0 1 BYTE 22 Bit Output(s) Affected Description / Function 7 PN2_7 SRC PLL (PCI Express) N Selection 2 6 5 4 3 2 1 0 PN2_6 PN2_5 PN2_4 PN2_3 PN2_2 PN2_1 PN2_0, LSB 0 9 1 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 23 Bit Output(s) Affected Description / Function 7 S_CBS1 6 5 4 3 S_CBS0 S_CNS1 S_CNS0 S_PNS1 2 1 0 S_PNS0 Soft Alarm CPU PLL mode select, see S_CBS Band Selection Table Soft Alarm CPU PLL N select, see S_CNS N Selection Table Soft Alarm SRC PLL (PCI Express) N select, see S_PNS N Selection Table 0 1 Type Power On RW 0 RW RW RW RW 0 0 0 0 RW 0 Type Power On RW RW RW RW RW 0 0 0 0 0 RW 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 1 0 1 1 Type Power On RW RW RW RW RW RW RW RW 0 0 0 1 BYTE 24 Bit Output(s) Affected Description / Function 7 6 5 4 3 H_CBS1 H_CBS0 H_CNS2 H_CNS0 H_PNS1 2 1 0 H_PNS0 Hard Alarm CPU PLL mode select, see H_CBS Band Selection Table Hard Alarm CPU PLL N select, see H_CNS N Selection Table Hard Alarm SRC PLL (PCI Express) N select, see H_PNS N selection table 0 1 BYTE 25 Bit Output(s) Affected 7 6 5 4 3 2 1 0 WD Timer 7 WD Timer 6 WD Timer 5 WD Timer 4 WD Timer 3 WD Timer 2 WD Timer 1 WD Timer 0 Description / Function 0 1 Watchdog timer Default is 11*290ms Hard Alarm = WD timer * 290ms BYTE 26 Bit 7 6 5 4 3 2 1 0 Output(s) Affected Soft Timer 3 Soft Timer 2 Soft Timer 1 Soft Timer 0 Description / Function 0 Soft Alarm timer Soft Alarm = Soft timer * 290ms 10 1 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 27 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 Watch Dog Enable Watch Dog Enable Disable Enable RW 0 Soft Alarm Enable Reserved Hard Alarm Enable Reserved Hard Alarm FS Relatch Enable Reserved Soft Alarm Enable Disable Enable Hard Alarm Enable Disable Enable Relatch FS[C, B, A] at Hard Alarm Disable Relatch RW RW RW RW RW 0 0 0 0 0 RW 0 0 BYTE 42, 43 SRC SPREAD MAGNITUDE (1) BYTE 44 SRC SPREAD CENTER(1) BYTE 38 SRC SPREAD CONTROL SWITCH (FROM BYTE 6 TO BYTES 42, 43, 44)(1) NOTE: 1. Contact IDT for detailed application note. 11 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PLL FREQUENCY PROGRAMMING PROCEDURES The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may enable either one or both of the alarms. User presets the CPU PLL Mode and N, and SRC PLL N value: 1. Set CPU PLL Mode, CB1 and CB2, byte 17 2. Set CPU PLL N, CN1 and CN2, byte 18 and byte 19 3. Set SRC(PCI Express) PLL N, PN1 and PN2, byte 21, 22 User selects the frequency for Soft Alarm and Hard Alarm, if enabled respectively: 4. Select Soft Alarm frequency, byte 23 5. Select Hard Alarm frequency, byte 24 User sets the Timer and enables the WD circuit for frequency switch: 6. Set Hard Alarm Timer, byte 25 7. Set Soft Alarm Timer, byte 26 8. Enable Soft and Hard Alarm, byte 27 9. Enable Watch Dog (WDE), byte 27 • • WDE Disable resets WDSRB and WDHRB. PCI CLK is selectable from SRC PLL or SATA PLL, byte 5 bit 6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI is fixed to 3 selections, 33MHz, 36MHz and 40MHz, byte 5 bit[5:4]. WD SOFT AND HARD ALARM/TIME OUT OPERATION WD HARD ALARM TIMER [7:0] WD SOFT ALARM TIMER [3:0] WDE Trigger Watch Dog Circuit If Soft Alarm Enabled (byte 27): Set WDSRB (byte 6) Load CPU N and Mode selections into PCU PLL Load SRC N selection into SRC PLL 12 If Hard Alarm Enabled (byte 27): Set WDHRB (byte 6) Load CPU N and Band selections into PCU PLL Load SRC N selections into SRC PLL If Hard Alarm Relatch Enabled: Latch FSC, B, A IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V VIH_FS FS Input HIGH Voltage For FSA,B,C and Test_Mode 0.7 — VDD + 0.3 V VIL_FS FS Input LOW Voltage For FSA,B,C and Test_Mode VSS - 0.3 — 0.35 V IIL Input LeakageCurrent 0< VIN < VDD, no internal pull-up or pull-down –5 — +5 mA IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA IDD3.3PD Powerdown Current mA FI Input Frequency(1) LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) CINX TSTAB All differential pairs driven — — 70 All differential pairs tri-stated — — 12 VDD = 3.3V — 14.31818 — MHz — — 7 nH Logic inputs — — 5 Output pin capacitance — — 6 pF X1 and X2 pins — — 5 Clock Stabilization(2,3) From VDD power-up or de-assertion of PD# to first clock — — 1.8 ms Modulation Frequency(2) Triangular modulation 30 — 33 KHz TDRIVE_SRC(2) SRC output enable after PCI_Stop# de-assertion — — 15 ns TDRIVE_PD#(2) CPU output enable after PD# de-assertion — — 300 us TFALL_PD#(2) Fall time of PD# — — 5 ns TRISE_PD#(3) Rise time of PD# — — 5 ns TDRIVE_CPU_Stop#(2) CPU output enable after CPU_Stop# de-assertion — — 10 us TFALL_CPU_Stop#(2) Fall time of PD# — — 5 ns TRISE_CPU_Stop#(3) Rise time of PD# — — 5 ns NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements. 13 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Min. Typ. Max. Unit VO = VX 3000 — — Ω Output HIGH Voltage IOH = -1mA 2.4 — — V VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 — 850 mV VLOW Voltage LOW(2) oscilloscope math function –150 — 150 VOVS Max Voltage(2) Measurement on single-ended signal using absolute value — — 1150 VUDS Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Long Accuracy(2,3) See TPERIOD Min. - Max. values –300 — 300 ppm 400MHz nominal/spread 2.4993 — 2.5008 333.33MHz nominal/spread 2.9991 — 3.0009 266.66MHz nominal/spread 3.7489 — 3.7511 200MHz nominal/spread 4.9985 — 5.0015 166.66MHz nominal/spread 5.9982 — 6.0018 133.33MHz nominal/spread 7.4978 — 7.5023 100MHz nominal/spread 9.997 — 10.003 96MHz nominal 10.4135 — 10.4198 400MHz nominal/spread 2.4143 — — 333.33MHz nominal/spread 2.9141 — — 266.66MHz nominal/spread 3.6639 — — 200MHz nominal/spread 166.66MHz nominal/spread 4.9135 5.9132 — — — — 133.33MHz nominal/spread 7.4128 — — 100MHz nominal/spread 9.912 — — 10.1635 — — Current Source Output Impedance(2) VOH3 ZO ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) Test Conditions 96MHz nominal mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps d-tR Rise Time Variation(2) — — 125 ps d-tF Fall Time Variation(2) — — 125 ps dT3 Duty Cycle(2) Measurement from differential waveform 45 — 55 % tSK3 Skew(2) VT = 50% — — 100 ps Measurement from differential waveform — — 85 ps tJCYC-CYC Jitter, Cycle to Cycle(2) NOTES: 1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 14 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol ppm TPERIOD Parameter Test Conditions Long Accuracy(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values Clock Period(2) — — 300 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 0.5 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 0.5 — 2 ns IOL Output LOW Current Cycle(1) mA dT1 Duty VT = 1.5V 45 — 55 % tSK1 Skew(1) VT = 1.5V — — 500 ps tJCYC-CYC Jitter(1) VT = 1.5V — — 250 ps Min. Typ. Max. Unit — — 300 ppm 20.8257 — 20.834 ns NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS, 48MHZ, USB Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1,2) See Tperiod Min. - Max. values Clock Period(2) 48MHz output nominal VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -29 — — mA VOH at Max. = 3.135V — — -23 VOL at Min. = 1.95V 29 — — ppm TPERIOD IOL Output LOW Current mA VOL at Max. = 0.4V — — 27 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 15 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal VOH Output HIGH Voltage(1) VOL ppm Min. Typ. Max. Unit — — 300 ppm 69.827 — 69.855 ns IOH = -1mA 2.4 — — V Output LOW Voltage(1) IOL = 1mA — — 0.4 V IOH Output HIGH Current(1) VOH at Min. = 1V, VOH at Max. = 3.135V -33 — -33 mA IOL Output LOW Current(1) VOL at Min. = 1.95V, VOL at Max. = 0.4V 30 — 38 mA tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tSK1 Skew(1) VT = 1.5V — — 500 ps VT = 1.5V 45 — 55 % VT = 1.5V — — 1000 ps TPERIOD dT1 tJCYC-CYC Duty Cycle(1) Jitter(1) NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. 16 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD, POWER DOWN PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches. PWRDWN CPU CPU# SRC SRC# PCIF/PCI USB 0 Normal 1 IREF * 2 or float Normal Normal Normal 33MHz Float IREF * 2 or float Float Low PD ASSERTION PWRDWN CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 17 DOT96 DOT96# REF 48MHz Normal Normal 14.318MHz Low IREF * 2 or float Float Low IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD DE-ASSERTION tSTABLE <1.8mS PWRDWN# CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 tDRIVE_PWRDWN <300µS, <200mV 18 IDTCV115C PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDTCV XXX Device Type XX Package X Grade CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Blank Commercial Temperature Range (0°C to +70°C) PV PVG Small Shrink Outline Package SSOP - Green 115C Programmable FlexPC™ Clock for P4 Processor for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 19 for Tech Support: [email protected] (408) 654-6459