IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV110J DESCRIPTION: FEATURES: IDTCV110J is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. • One high precision PLL for CPU, SSC, and N programming • One high precision PLL for SRC/PCI/SATA, SSC, and N programming • One high precision PLL for 96MHz/48MHz • Band-gap circuit for differential outputs • Support spread spectrum modulation, down spread 0.5% • Support SMBus block read/write, index read/write • Selectable output strength for REF • Allows for CPU frequency to change to a higher frequency for maximum system computing power • Available in SSOP package OUTPUTS: • 2*0.7V current –mode differential CPU CLK pair • 6*0.7V current –mode differential SRC CLK pair, one dedicated for SATA • One CPU_ITP/SRC selectable CLK pair • 9*PCI, 3 free running, 33.3MHz • 1*96MHz, 1*48MHz • 1*REF KEY SPECIFICATION: • • • • • CPU/SRC CLK cycle to cycle jitter < 85ps SATA CLK cycle to cycle jitter < 85ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error < 114 ppm Static PLL frequency divide error for 48MHz < 5 ppm FUNCTIONAL BLOCK DIAGRAM PLL1 SSC N Programmable X1 CPU CLK Output Buffers Stop Logic CPU[1:0] CPU_ITP/SRC7 XTAL Osc Amp IREF REF X2 ITP_EN SDATA SCLK SM Bus Controller SRC CLK Output Buffer Stop Logic PLL2 SSC N Programmable SRC[6:1] PCI[5:0], PCIF[2:0] IREF VTT_PWRGD#/PD Control Logic 48MHz FSA.B.C 48MHz/96MHz Output BUffer PLL3 DOT96 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-6507/12 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VDDA 3.3V Core Supply Voltage Min VDD_PCI 1 56 PCI2 VDDIN 3.3V Logic Input Supply Voltage GND - 0.5 VSS_PCI 2 55 PCI1 TSTG Storage Temperature PCI3 3 54 PCI0 TAMBIENT Ambient Operating Temperature PCI4 4 53 FSC/TEST_SEL TCASE Case Temperature PCI5 5 52 REF ESD Prot Input ESD Protection VSS_PCI 6 51 VSS_REF VDD_PCI 7 50 XTAL_IN PCIF0/ITP_EN 8 49 XTAL_OUT PCIF1 9 48 VDD_REF PCIF2 10 47 SDA VDD48 11 46 SCL USB48 12 45 VSS_CPU VSS48 13 44 CPU0 DOT96 14 43 CPU0# DOT96# 15 42 VDD_CPU FSB/TEST_MODE 16 41 CPU1 VTT_PWRGD#/PD 17 40 CPU1# FSA 18 39 IREF SRC1 19 38 VSSA 20 37 VDDA VDD_SRC 21 36 CPU2_ITP/SRC7 SRC2 22 35 CPU2_ITP#/SRC7# SRC2# 23 34 VDD_SRC SRC3 24 33 SRC6 25 32 SRC6# SRC4 26 31 SRC5 SRC4# 27 30 SRC5# VDD_SRC 28 29 VSS_SRC 0 2000 Unit 4.6 V 4.6 V +150 °C +70 °C +115 °C V Human Body Model SRC1# SRC3# –65 Max NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SSOP TOP VIEW FREQUENCY SELECTION TABLE FSC, B, A CPU SRC[7:1] PCI USB DOT REF 101 100 100 33.3 48 96 14.318 001 133 100 33.3 48 96 14.318 011 166 100 33.3 48 96 14.318 010 200 100 33.3 48 96 14.318 000 266 100 33.3 48 96 14.318 100 333 100 33.3 48 96 14.318 110 400 100 33.3 48 96 14.318 111 Reserve 100 33.3 48 96 14.318 2 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Number Name Type Description 1 VDD_PCI PWR 3.3V 2 VSS_PCI GND GND 3 PCI3 OUT PCI clock 4 PCI4 OUT PCI clock 5 PCI5 OUT PCI clock 6 VSS_PCI GND GND 7 VDD_PCI PWR 3.3V 8 PCIF0/ITP_EN I/O PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2. 9 PCIF1 OUT PCI clock, free running 10 PCIF2 OUT PCI clock, free running 11 VDD48 PWR 3.3V 12 USB48 OUT 48MHz clock 13 VSS48 GND GND 14 DOT96 OUT 96MHz 0.7 current mode differential clock output 15 DOT96# OUT 96MHz 0.7 current mode differential clock output 16 FSB/TEST_MODE IN CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0. 17 VTT_PWRGD#/PD IN Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH) 18 FSA IN CPU frequency selection 19 SRC1 OUT Differential serial reference clock 20 SRC1# OUT Differential serial reference clock 21 VDD_SRC PWR 3.3V 22 SRC2 OUT Differential serial reference clock 23 SRC2# OUT Differential serial reference clock 24 SRC3 OUT Differential serial reference clock 25 SRC3# OUT Differential serial reference clock 26 SRC4 OUT Differential serial reference clock 27 SRC4# OUT Differential serial reference clock 28 VDD_SRC PWR 3.3V 29 VSS_SRC GND GND 30 SRC5# OUT Differential serial reference clock 31 SRC5 OUT Differential serial reference clock 32 SRC6# OUT Differential serial reference clock 33 SRC6 OUT Differential serial reference clock 34 VDD_SRC PWR 3.3V 35 CPU2_ITP#/SRC7# OUT Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#. 36 CPU2_ITP/SRC7 OUT Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7. 37 VDDA PWR 3.3V 38 VSSA GND GND 39 IREF OUT Reference current for differential output buffer 40 CPU1# OUT Host 0.7 current mode differential clock output 41 CPU1 OUT Host 0.7 current mode differential clock output 42 VDD_CPU PWR 3.3V 3 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONT.) Pin Number Name Type 43 CPU0# OUT Host 0.7 current mode differential clock output Description 44 CPU0 OUT Host 0.7 current mode differential clock output 45 VSS_CPU GND 46 SCL IN GND SM Bus clock 47 SDA I/O 48 VDD_REF PWR 3.3V SM Bus data 49 XTAL_OUT OUT XTAL output 50 XTAL_IN IN 51 VSS_REF GND XTAL input 52 REF OUT 53 FSC/TEST_SEL IN 54 PCI0 OUT PCI clock 55 PCI1 OUT PCI clock 56 PCI2 OUT PCI clock GND 14.318 MHz reference clock output CPU frequency selection. Selects test mode if pulled to above 2V when VTT_PWRGD# is asserted LOW. INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master INDEX BYTE READ INDEX BYTE WRITE Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. Setting bit[11:18] = starting address, bit[20:27] = 01h. 4 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE CONTROL REGISTERS N PROGRAMMING PROCEDURE • • Use Index byte write. For N programming, the user only needs to access Byte17, Byte 25, and Byte8. 1. 2. 3. • • • Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17. Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f. Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly. Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much the system can sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the system will likely hang. Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming. Most of the Bytes, from Byte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according to each power on frequency selection. To avoid mistakes, don’t write on those byte (be careful about Block Write). It is suggested to use the Index Byte write to access bytes. FREQUENCY SELECTION TABLE SSC MAGNITUDE CONTROL, SMC SMC[2:0] 000 001 010 011 100 101 110 111 FS_C, B, A 101 001 011 010 000 100 110 111 -0.25 -0.5 -0.75 -1 ±0.125 ±0.25 ±0.375 ±0.5 RESOLUTION CPU (MHz) 100 133 166 200 266 333 400 Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150 5 CPU 100 133 166 200 266 333 400 RESERVE IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 1 2 3 4 5 6 7 Reserved SRC1, SRC1# SRC2, SRC2# SRC3, SRC3# SRC4, SRC4# SRC5, SRC5# SRC6, SRC6# CPU2, CPU2#/ SRC7, SRC7# Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW 1 1 1 1 1 1 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 CPU[2:0], SRC[7:1], PCI[5:0], PCIF[2:0] CPU0, CPU0# CPU1, CPU1# Reserve REF USB48 DOT96 PCIF0 Spread Spectrum mode enable Spread off Spread on RW 0 Output Enable Output Enable Tristate Tristate Enable Enable RW RW Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Enable Enable Enable Enable RW RW RW RW 1 1 0 1 1 1 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 1 2 3 4 5 6 7 PCIF1 PCIF2 PCI0 PCI1 PCI2 PCI3 PCI4 PCI5 Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 BYTE 1 1 2 3 4 5 6 7 BYTE 2 BYTE 3 Bit Output(s) Affected 0 Reserved 1 2 3 4 5 6 7 SRC1 SRC2 SRC3 SRC4 SRC5 SRC6 SRC7 Description / Function 0 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion 6 Free running, not affected by PCI_STOP 1 Stopped with PCI_STOP Type Power On RW RW RW RW RW RW RW 0 0 0 0 0 0 0 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 4 Bit Output(s) Affected 0 1 2 3 4 5 6 7 Reserved Reserved Reserved PCIF0 PCIF1 PCIF2 DOT96 Reserved Description / Function 0 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion DOT96 power down drive mode Not stopped by PCI_STOP Driven in power down 1 Type Power On Stopped with PCI_STOP Tristate RW RW RW RW RW RW RW 1 1 1 0 0 0 0 0 BYTE 5 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 1 2 3 4 5 6 7 CPU0, CPU0# CPU1, CPU1# CPU2, CPU2# SRC[7:1], SRC[7:1]# Reserved Reserved Reserved SRC[7:1], SRC[7:1]# CPU0 PWRDWN drive mode CPU1 PWRDWN drive mode CPU2 PWRDWN drive mode SRC PWRDWN drive mode Driven in power down Driven in power down Driven in power down Driven in power down Tristate in power down Tristate in power down Tristate in power down Tristate in power down RW RW RW RW SRC PCI_STOP drive mode Driven in PCI_STOP Tristate when stopped RW 0 0 0 0 0 0 0 0 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 1 2 3 CPU[2:0] CPU[2:0] CPU[2:0] PCI, SRC FSA latched value on power up FSB latched value on power up FSC latched value on power up Software PCI_STOP control for PCI and SRC CLK R R R RW 1 4 5 6 REF Reserved RW 1 0 0 7 CPU, SRC, PCI PCIF, REF, USB48, DOT96 BYTE 6 Stop all PCI, PCIF, and SRC which can be stopped by PCI_STOP# Software STOP Disabled REF drive strength 1x drive 2x drive Test clock mode entry control Normal operation Test mode, controlled Only valid when Byte 6, Bit 7 is HIGH Hi-Z by Byte 6, Bit 7 REF/N 7 0 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 7 Bit Output(s) Affected 0 1 2 3 4 5 6 7 Description / Function 0 1 Vendor ID Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Type Power On R R R R R R R R 1 0 1 0 0 0 0 0 BYTE 8 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 1 2 3 4 5 6 7 One cycle read N Programming enable Disable Disable Enable Enable SRC, PLL2, SSC enable USB 48 Strength control USB PLL power down SRC PLL power down CPU PLL power down Only valid when Byte1 bit0 is 1 1x Normal Normal Normal Disable 2x Power down Power down Power down Enable RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 1 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 1 2 3 4 5 6 7 SRC SMC0 SRC SMC1 SRC SMC2 Reserved CPU SMC0 CPU SMC1 CPU SMC2 SRC/PCI SSC control see SMC table RW RW RW RW RW RW RW RW 1 0 0 0 1 0 0 0 (Must be 0) Type Power On Reserved USB48 BYTE 9 CPU PLL SSC control see SMC table Must be 0 Must be 0 BYTE 17 Bit Output(s) Affected Description / Function 0 1 2 3 4 5 6 7 CPU_N0, LSB CPU_N1 CPU_N2 CPU_N3 CPU_N4 CPU_N5 CPU_N6 CPU_N7, MSB CPU CLK = N* Resolution see Resolution table 0 1 RW RW RW RW RW RW RW RW 8 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. BYTE 25 Bit Output(s) Affected Description / Function 0 1 2 3 4 5 6 7 SRC_N0, LSB SRC_N1 SRC_N2 SRC_N3 SRC_N4 SRC_N5 SRC_N6 SRC_N7, MSB SRC f = N*SRC Resolution Resolution = 0.666667 100MHz N= 150 0 1 Type RW RW RW RW RW RW RW RW BYTES 26-31: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. 9 Power On IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V VIH_FS LOW Voltage, HIGH Threshold For FSA.B.C test_mode 0.7 — VDD + 0.3 V VIL_FS LOW Voltage, LOW Threshold For FSA.B.C test_mode VSS - 0.3 — 0.35 V Input LeakageCurrent 0< VIN < VDD, no internal pull-up or pull-down –5 — +5 mA IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA IDD3.3PD Powerdown Current All differential pairs driven — — 70 mA All differential pairs tri-stated — — 12 VDD = 3.3V — 14.31818 — MHz — — 7 nH Logic inputs — — 5 Output pin capacitance — — 6 IIL FI Input Frequency(1) LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) CINX TSTAB pF X1 and X2 pins — — 5 Clock Stabilization(2,3) From VDD power-up or de-assertion of PD to first clock — — 1.8 ms Modulation Frequency(2) Triangular modulation 30 — 33 KHz TDRIVE_PD(2) CPU output enable after PD de-assertion — — 300 us TFALL_PD(2) Fall time of PD — — 5 ns TRISE_PD(3) Rise time of PD — — 5 ns NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements. 10 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Min. Typ. Max. Unit VO = VX 3000 — — Ω Output HIGH Voltage IOH = -1mA 2.4 — — V VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 — 850 mV VLOW Voltage LOW(2) oscilloscope math function –150 — 150 VOVS Max Voltage(2) Measurement on single-ended signal using absolute value — — 1150 VUDS Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Long Accuracy(2,3) See TPERIOD Min. - Max. values –300 — 300 ppm 400MHz nominal/spread 2.4993 — 2.5008 333.33MHz nominal/spread 2.9991 — 3.0009 266.66MHz nominal/spread 3.7489 — 3.7511 200MHz nominal/spread 4.9985 — 5.0015 166.66MHz nominal/spread 5.9982 — 6.0018 133.33MHz nominal/spread 7.4978 — 7.5023 100MHz nominal/spread 9.997 — 10.003 96MHz nominal 10.4135 — 10.4198 400MHz nominal/spread 2.4143 — — 333.33MHz nominal/spread 2.9141 — — 266.66MHz nominal/spread 3.6639 — — 200MHz nominal/spread 166.66MHz nominal/spread 4.9135 5.9132 — — — — 133.33MHz nominal/spread 7.4128 — — 100MHz nominal/spread 9.912 — — 10.1635 — — Current Source Output Impedance(2) VOH3 ZO ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) Test Conditions 96MHz nominal mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps d-tR Rise Time Variation(2) — — 125 ps d-tF Fall Time Variation(2) — — 125 ps dT3 Duty Cycle(2) Measurement from differential waveform 45 — 55 % tSK3 Skew(2) VT = 50% — — 100 ps Measurement from differential waveform — — 85 ps tJCYC-CYC Jitter, Cycle to Cycle(2) NOTES: 1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 11 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol ppm TPERIOD Parameter Test Conditions Long Accuracy(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values Clock Period(2) — — 300 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 0.5 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 0.5 — 2 ns IOL Output LOW Current Cycle(1) mA dT1 Duty VT = 1.5V 45 — 55 % tSK1 Skew(1) VT = 1.5V — — 500 ps tJCYC-CYC Jitter(1) VT = 1.5V — — 250 ps Min. Typ. Max. Unit — — 300 ppm 20.8257 — 20.834 ns NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS, 48MHZ, USB Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1,2) See Tperiod Min. - Max. values Clock Period(2) 48MHz output nominal VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -29 — — mA VOH at Max. = 3.135V — — -23 VOL at Min. = 1.95V 29 — — ppm TPERIOD IOL Output LOW Current mA VOL at Max. = 0.4V — — 27 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 12 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal VOH Output HIGH Voltage(1) VOL ppm Min. Typ. Max. Unit — — 300 ppm 69.827 — 69.855 ns IOH = -1mA 2.4 — — V Output LOW Voltage(1) IOL = 1mA — — 0.4 V IOH Output HIGH Current(1) VOH at Min. = 1V, VOH at Max. = 3.135V -33 — -33 mA IOL Output LOW Current(1) VOL at Min. = 1.95V, VOL at Max. = 0.4V 30 — 38 mA tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tSK1 Skew(1) VT = 1.5V — — 500 ps VT = 1.5V 45 — 55 % VT = 1.5V — — 1000 ps TPERIOD dT1 Duty tJCYC-CYC Cycle(1) Jitter(1) NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. PCI STOP FUNCTIONALITY If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit. PCI_STOP (Byte 6 bit 3) CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF 1 Normal Normal Normal Normal 33MHz 48MHz Normal Normal 14.318MHz 0 Normal Normal IREF * 6 or float Low Low 48MHz Normal Normal 14.318MHz 13 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD, POWER DOWN PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches. PD CPU CPU# SRC SRC# PCIF/PCI USB 0 Normal 1 IREF * 2 or float Normal Normal Normal 33MHz Float IREF * 2 or float Float Low PD ASSERTION PD CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 14 DOT96 DOT96# REF 48MHz Normal Normal 14.318MHz Low IREF * 2 or float Float Low IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD DE-ASSERTION The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion. tSTABLE <1.8mS PD CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 tDRIVE_PD <300µS, <200mV 15 IDTCV110J PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDTCV XXX Device Type XX Package X Grade CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Blank Commercial Temperature Range (0°C to +70°C) PV PVG Small Shrink Outline Package SSOP - Green 110J Programmable FlexPC Clock for P4 Processor for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 16 for Tech Support: [email protected] (408) 654-6459