IMP1 832 POWER MANAGEMENT 3.3V µP Power Supply Monitor and Reset Circuit – Selectable Trip -Point Tolerance and Watchdog Period – Push-Button Reset – Push-Pull Reset Outputs The IMP1832 microprocessor supervisor can halt and restart a “hungup” or “stalled” microprocessor, restart a microprocessor after a power failure, and debounce a manual push-button microprocessor reset switch. The IMP1832 features over 40% lower supply current than the pin compatible Dallas Semiconductor DS1832. Key Features ◆ Pin compatible with the Dallas Semiconductor DS1832 — Over 40% lower supply current ◆ 3.3V supply monitor ◆ Push-pull output ◆ Selectable watchdog period ◆ Debounce manual push-button reset input ◆ Precision temperature-compensated voltage reference and comparator ◆ Power-up, power-down and brownout detection ◆ 250ms minimum reset time ◆ Active LOW and HIGH reset signal ◆ Selectable trip point tolerance: 10% or 20% ◆ Low-cost 8-pin DIP/SO and 8-pin MicroSO packages ◆ Wide operating temperature – 40°C to +85°C Precision temperature compensated reference and comparator circuits monitor the 3.3V, VCC input voltage. During power-up or when the VCC power supply falls outside selectable tolerance limits, both RESET and RESET become active. When VCC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point Also included is a watchdog timer to stop and restart a tolerance signal, TOL, selects the trip level tolerance to be either 10- or microprocessor that is “hung-up”. Three watchdog time20-percent. out periods are selectable: 150ms, 610ms and 1,200ms. If the ST input is not strobed LOW before the time-out period RESET and RESET outputs are push-pull. expires, a reset is issued. A debounced manual reset input, PBRST, activates the reset outputs for Devices are available in 8-pin DIP, 8-pin SO and compact a minimum period of 250ms. 8-pin MicroSO packages. Block Diagram VCC TOL VCC IMP1832 8 3 6 10%/20% Tolerance Selection RESET + VCC Reference VCC – 5 40kW PBRST TD ST 1 Push Button Debounce 2 Watchdog Timebase Selection 7 Watchdog Transition Detector RESET Reset & Watchdog Timer 4 1832_02.eps GND © 1999 IMP, Inc. 408-432-9100/www.impweb.com 1 IMP1 832 Pin Configuration DIP/SO/MicroSO PBRST 1 TD 2 8 VCC IMP1832 7 ST TOL 3 6 RESET GND 4 5 RESET 1832_01.eps Pin Descriptions Pin Number 8-Pin Package Name Function 1 2 PBRST TD 3 4 5 TOL GND RESET 6 7 8 RESET ST VCC Debounced manual pushbutton reset input Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD = Open, and tTD =1200ms for TD = VCC) Selects 10% (TOL connected to GND) or 20% (TOL connected to VCC) trip point tolerance Ground Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. Active LOW reset output. (See RESET) Strobe Input 5V power Ordering Information Package Operating Temperature Range Maximum Supply Current (µA) Voltage Monitoring Application IMP1832 8-DIP – 40°C to 85°C 20 3.3V IMP1832S 8-SO – 40°C to 85°C 20 3.3V 8-MicroSO – 40°C to 85°C 20 3.3V Part Number IMP1832SEMA 1832_t01.eps 2 408-432-9100/www.impweb.com © 1999 IMP, Inc. IMP1 832 Absolute Maximum Ratings Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . –0.5V to VCC + 0.5V Voltage on PBRST, RESET, RESET . . . . . . . . –0.5V to VCC + 0.5V Operating Temperature Range . . . . . . . . . . . –40°C to 85°C Soldering Temperature . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to 125°C Voltages measured with respect to ground. These are stress ratings only and functional operation is not implied. Electrical Characteristics Unless otherwise stated, 1.2V ≤ VCC ≤ 5.5V and over the operating temperature range of –40°C to +85°C . All voltages are referenced to ground. Parameter Symbol Conditions Min Typ Max Units Supply Voltage (VCC) VCC 1.0 5.5 V ST and PBRST Input High Level VIH VCC ≥ 2.7V 2 VCC + 0.3V V ST and PBRST Input High Level VIH VCC < 2.7V VCC - 0.4V ST and PBRST Input Low Level VIL – 0.3 VCC Trip Point (TOL = GND) VCCTP 2.80 VCC Trip Point (TOL = VCC) VCCTP 2.47 Watchdog Time-Out Period tTD TD = GND 62.5 Watchdog Time-Out Period tTD TD = VCC 500 Watchdog Time-Out Period tTD TD floating 250 610 Output Voltage VOH I = –500µA, VCC < 2.7V VCC - 0.3V VCC - 0.1V Output Current IOH Output = 2.4V, VCC ≥ 2.7V Output Current IOL Output = 0.4V, VCC ≥ 2.7V Input Leakage RESET Low Level IIL V 2.88 2.97 V 2.55 2.64 V 150 250 ms 1200 2000 ms 1000 ms µA 350 mA –1.0 PBRST pin ICC1 V 10 VOL Internal Pull-Up Resistor Operating Current V 0.5 1.0 µA 0.4 V 40 Outputs open. VCC ≤ 3.6V and all inputs at VCC or GND kΩ 20 µA Input Capacitance CIN 5 pF Output Capacitance COUT 7 pF PBRST Manual Reset Minimum Low Time tPB PBRST = VIL Reset Active Time tRST ST Pulse Width tST Must not exceed tRD minimum. Watchdog cannot be disabled. VCC Fail Detect to RESET or RESET tRPD Pulses < 2µs at VCCTP minimum will not cause reset. VCC Slew Rate tPDLY VCC Detect to RESET or RESET Inactive tRPU VCC Slew Rate © 1999 IMP, Inc. 250 tF PBRST Stable LOW to RESET and RESET Active 20 ms 610 1000 20 ns 5 8 tR 250 0 408-432-9100/www.impweb.com µs µs 20 trise = 5µs ms 610 20 ms 1000 ms ns 3 IMP1 832 Application Information Supply Voltage Monitor The IMP1832 monitors the microprocessor or microcontroller power supply and issues reset signals, both active HIGH and active LOW, that halt processor operation whenever the power supply voltage levels are outside a predetermined tolerance. Tolerance levels are set with the TOL pin. RESET and RESET signals are generated at the last moment of a valid VCC signal. On power-up, both reset signals are active for a minimum of 250ms after the supply has returned to intolerance level. This allows the power supply and monitored processor to stabilize before instruction execution is allowed to begin. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until VCC drops below 1.2V. The active HIGH reset signal is valid down to a VCC level of 1.2V also. TRIP Point Voltage (V) Tolerance Select Tolerance Min Nominal Max TOL = VCC 20% 2.47 2.55 2.64 TOL = GND 10% 2.80 2.88 2.97 1832 t02.eps Trip Point Tolerance Selection Manual Reset Operation With TOL connected to VCC, RESET and RESET become active whenever VCC falls below 2.64V. RESET and RESET become active when VCC falls below 2.98V if TOL is connected to ground. Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is pulled HIGH through an internal 40kΩ resistor. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. tR The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40kΩ resistor. VCCTP(MAX) VCCTP VCCTP(MIN) When PBRST is held LOW for the minimum time tPB , both resets become active and remain active for a minimum time period of 250ms after PBRST returns HIGH. The PBRST can be driven from a TTL or CMOS logic line or shorted to ground with a mechanical switch. VCC tRPU RESET tPB PBRST VOH tPDLY VIH VIL VOL tRST RESET 1832_04.eps RESET Figure 1. Timing Diagram: Power Up VOH VOL RESET 1832_07.eps tF VCC VCCTP(MAX) VCCTP Figure 3. Timing Diagram: Pushbutton Reset Supply Voltage VCCTP(MIN) IMP1832 1 tRPD RESET 2 3 RESET 4 VOH VOL TD VCC ST TOL RESET GND RESET 8 7 6 5 µP RESET 1832_05.eps 1832_03.eps Figure 2. Timing Diagram: Power Down 4 PBRST Figure 4. Application Circuit: Pushbutton Reset 408-432-9100/www.impweb.com © 1999 IMP, Inc. IMP1 832 Application Information Watchdog Timer and ST Input A watchdog timer stops and restarts a microprocessor that is “hung-up”. Through the time delay input, TD, three watchdog time-out periods are selectable: 150ms, 610ms and 1,200ms. If the strobe input, ST, is not strobed LOW prior to timeout, reset signals become active. On power-up or after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, allowing the power supply and system microprocessor to stabilize. ST Valid Strobe Invalid Strobe tST RESET Watchdog Time-Out Period (ms) GND Floating VCC Min Nominal Max 62.5 250 500 150 610 1200 250 1000 2000 1832_t03.eps tTD (Min) tRST Timeouts periods of approximately 150ms, 610ms or 1,200ms are selected through the TD pin. TD Voltage Level ST Pulses as short as 20ns can be detected. Valid Strobe A HIGH-to-LOW ST signal transition must be regularly issued no later than the minimum time-out period defined by the state of the TD signal. This guarantees the watchdog timer does not time-out. The watchdog timer can not be disabled. It must be strobed with a high-to-low transition to avoid a watchdog timeout and reset. tTD (Max) 1832_08.eps Note: ST is ignored whenever a reset is active. Figure 5. Timing Diagram: Strobe Input Supply Voltage IMP1832 1 2 3 4 PBRST TD VCC ST TOL RESET GND RESET 8 MREQ 7 6 mP RESET Address Bus Decoder 5 1832_06.eps Figure 6. Application Circuit: Watchdog Timer © 1999 IMP, Inc. 408-432-9100/www.impweb.com 5 IMP1 832 Package Dimensions MicroSO (8-Pin) Inches Min a + L D C D A e 0.10mm 0.004in Max A A1 A2 b C D e E E1 L a ––––– 0.0433 0.0020 0.0059 0.0295 0.0374 0.0098 0.0157 0.0051 0.0091 0.1142 0.1220 0.0256 BSC 0.193 BSC 0.1142 0.1220 0.0157 0.0276 0° 6° A A1 B C e E H L D 0.053 0.004 0.013 0.007 SO (8-Pin) 0°– 8° L E Max –––– 1.10 0.050 0.15 0.75 0.95 0.25 0.40 0.13 0.23 2.90 3.10 0.65 BSC 4.90 BSC 2.90 3.10 0.40 0.70 0° 6° SO (8-Pin)** MicroSO (8-Pin).eps A1 b Min MicroSO (8-Pin)* E1 E A2 Millimeters H 0.069 0.010 0.020 0.010 1.35 0.10 0.33 0.19 0.050 0.150 0.228 0.016 0.189 1.75 0.25 0.51 0.25 1.27 0.157 0.244 0.050 0.197 3.80 5.80 0.40 4.80 4.00 6.20 1.27 2.00 Plastic DIP (8-Pin)*** C D A e B A1 SO (8-Pin).eps Plastic DIP (8-Pin) D1 E D E1 A ––––– 0.210 A1 0.015 ––––– A2 0.115 0.195 b 0.014 0.022 b2 0.045 0.070 b3 0.030 0.045 D 0.355 0.400 D1 0.005 ––––– E 0.300 0.325 E1 0.240 0.280 e 0.100 ––––– eA 0.300 ––––– eB ––––– 0.430 eC ––––– 0.060 L 0.115 0.150 *** JEDEC Drawing MO-187AA *** JEDEC Drawing MS-112AA *** JEDEC Drawing MS-001BA –––– 0.38 2.92 0.36 1.14 0.80 9.02 0.13 7.62 6.10 5.33 ––––– 4.95 0.56 1.78 1.14 10.16 ––––– 8.26 7.11 2.54 7.62 ––––– 10.92 2.92 3.81 1832_t04.at3 A A2 L A1 0°–15° e C b2 b eA eB Plastic DIP (8-Pin)a.eps 6 408-432-9100/www.impweb.com © 1999 IMP, Inc. IMP1 832 IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: [email protected] http://www.impweb.com The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners. © 1999 IMP, Inc. Printed in USA Publication #: 1015 Revision: B Issue Date: 11/08/99 Type: Preliminary