ASM1832 October 2006 rev 1.6 3.3V µP Power Supply Monitor and Reset Circuit General Description Devices are available in 8-pin PDIP, 8-pin SO and compact 8- The ASM1832 is a fully integrated microprocessor supervisor. It can halt and restart a “hung-up” microprocessor, restart a pin MicroSO packages. microprocessor after a power failure. It has a watchdog timer Key Features and external reset override. RESET and RESET outputs are • 3.3V supply monitor push-pull. • Push-pull output • Selectable watchdog period and • Debounce manual push-button reset input comparator circuits monitor the 3.3V, VCC input voltage status. • Precision temperature-compensated voltage reference A precision temperature-compensated reference and comparator. During power-up or when the VCC power supply falls outside selectable tolerance limits, both RESET and RESET become • Power-up, power-down and brown out detection active. When VCC rises above the threshold voltage, the reset • 250ms minimum reset time • Active LOW and HIGH reset signal • Selectable trip point tolerance: 10% or 20% • Low-cost 8-pin DIP/SO and 8-pin Micro SO packages • Wide operating temperature -40°C to +85°C signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 10% or 20%. A debounced manual reset input, PBRST, activates the reset outputs for a minimum period of 250ms. There is a watchdog Applications timer to stop and restart a microprocessor that is “hung-up”. • Microprocessor systems The watchdog timeouts periods are selectable: 150ms, 610ms, • Computers and 1200ms. If the ST input is not strobed LOW before the • Controllers time-out period expires, a reset is generated. • Portable instruments • Automotive systems Typical Operating Circuit Block Diagram 3.3V TOL Tolerance Selection µP ASM1832 ST RESET + - VCC I/O Reference VCC 40KΩ RESET GND TD TOL RESET VCC ASM1832 VCC PBRST Push Button Debounce TD Voltage Sense Comparator ST Watchdog Transition Detector Reset & Watchdog Timer GND PulseCore Semiconductor Corporation 1715 S, Boscom Ave Suit 200,Campbell, CA 95008. Tel:408-879-9077. Fax:408-879-9018. www.pulsecoresemi.com Notice: The information in this document is subject to change without notice RESET ASM1832 October 2006 rev 1.6 Pin Configuration PBRST 1 TD 2 TOL 3 GND 4 ASM1832 8 VCC 7 ST 6 RESET 5 RESET Pin Description Pin # 8-Pin Package Pin Name 1 PBRST 2 TD 3 TOL 4 GND Function Debounced manual pushbutton reset input. Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD=Open, and tTD = 1200ms for TD = VCC). Selects 10% (TOL connected to GND) or 20% (TOL connected to VCC) trip point tolerance. Ground. Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 5 RESET 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. 6 RESET Active LOW reset output. (See RESET). 7 ST Strobe input. 8 VCC 3.3V power. 3.3V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 2 of 9 ASM1832 October 2006 rev 1.6 Detailed Description The ASM1832 . monitors the microprocessor or microcontroller power supply and issues reset signals, both active HIGH and active LOW, that halt processor operation Tolerance Select TRIP Point Voltage (V) Tolerance whenever the power supply voltage levels are outside a Min Nom Max predetermined tolerance. RESET and RESET outputs TOL = VCC 20% 2.47 2.55 2.64 TOL = GND 10% 2.80 2.88 2.97 RESET and RESET signals are active for a minimum of 250ms after the supply has returned to in-tolerance level. This allows the power supply and monitored processor to stabilize before instruction execution is allowed to begin. Trip Point Tolerance Selection The TOL input is used to determine the level VCC can vary tR VCCTP(MAX) VCCTP VCCTP(MIN) ~~ tRPU below 3.3V without asserting a reset. With TOL conected to VCC, RESET and RESET become active whenever VCC falls below 2.64V. RESET and RESET become active when the VCC RESET VOH VCC falls below 2.98V if TOL is connected to ground. ~~ ~ ~ After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of VOL RESET Figure 1: Timing Diagram : Power Up 250ms. On power-down, once VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or ASM1832 uses a push-pull drive stage that can maintain a tF VCC VCCTP (MAX) VCCTP valid output below 1.2V. To sink current with VCC below 1.2V, a resistor can be connected from the reset pin (RESET) to VCCTP (MIN) Ground. This configuration will give a valid value on the reset output with VCC approaching 0V. During both power up and down, the configuration will draw current when the RESET is RESET VOH in the high state. The value of 100KΩ should be adequate to maintain a valid condition. The active HIGH reset signal is valid down to a VCC level of 1.2V also. tRPD VOL RESET ~~ ~~ ~ less until VCC drops below 1.2V. The reset output on the Figure 2: Timing Diagram : Power Down Microprocessor ASM1832 RESET RESET 100kΩ Application Information Manual Reset Operation Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset 3.3V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 3 of 9 ASM1832 October 2006 rev 1.6 signals. The pushbutton input is debounced and is pulled minimum timeout period, reset signals become active. On HIGH through an internal 40kΩ resistor. power-up after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms When PBRST is held LOW for the minimum time tPB, both resets become active and remain active for a minimum time minimum, allowing the power supply and system microprocessor to stabilize. period of 250ms after PBRST returns HIGH. ST Pulses as short as 20ns can be detected. The debounced input is guaranteed to recognize pulses Valid Strobe greater than 20ms. No external pull-up resistor is required, Valid Strobe Invalid Strobe ST since PBRST is pulled HIGH by an internal 40kΩ resistor. tST tRST The PBRST can be driven from a TTL or CMOS logic line or tTD (min) tTD (max) ~ shorted to ground with a mechanical switch. RESET tPB PBRST Note: ST is ignored whenever a reset is active Figure 5: Timing Diagram: Strobe Input VIH tPDLY VIL Timeouts periods of approximately 150ms, 610ms or ~ RESET VOH VOL Min Nom Max GND 62.5 150 250 Floating 250 610 1000 VCC 500 1200 2000 Figure 3: Timing Diagram: Pushbutton Reset Supply Voltage The watchdog timer can not be disabled. It must be strobed ASM1832 1 2 3 4 PBRST TD with a high-to-low transition to avoid watchdog timeout and VCC 8 ST TOL RESET GND RESET Watchdog Time-out Period (ms) TD Voltage level ~~ RESET 1,200ms are selected through the TD pin. tRST 7 6 5 reset. I/O µP Supply Voltage RESET ASM1832 1 Figure 4: Application Circuit: Pushbutton Reset 2 Watchdog Timer and ST Input 3 A watchdog timer stops and restarts a microprocessor that is 4 “hung-up”. The µP must toggle the ST input within a set PBRST TD MREQ VCC 8 ST TOL RESET GND RESET 7 6 µP RESET 5 Decoder Address Bus period (as selectable through TD input) to verify proper software execution. If the ST is not toggled low within the Figure 6: Application Circuit: Watchdog Timer 3.3V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 4 of 9 ASM1832 October 2006 rev 1.6 Absolute Maximum Ratings Parameter Min Max Unit Voltage on VCC -0.5 7 V Voltage on ST, TD -0.5 VCC + 0.5 V Voltage on PBRST, RESET, RESET -0.5 VCC + 0.5 V Operating Temperature Range -40 +85 °C +260 °C +125 °C 2 200 KV V Soldering Temperature (for 10 sec) Storage Temperature -55 ESD rating HBM MM Note: 1. Voltages are measured with respect to ground 2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC Electrical Characteristics Unless otherwise stated, 1.2 <= VCC<=5.5V and over the operating temperature range of -40°C to +85°C. All voltages are referenced to ground. Parameter Symbol Conditions Min Max Unit 1.0 5.5 V 2 VCC + 0.3 V Supply Voltage VCC ST and PBRST Input High Level VIH VCC >=2.7V ST and PBRST Input High Level VIH VCC<2.7V ST and PBRST Input Low Level VIL -0.3 VCC Trip Point (TOL = GND) VCCTP 2.80 VCC Trip Point (TOL = VCC) VCCTP Watchdog Timeout Period tTD TD = GND Typ VCC - 0.4V V 0.5 V 2.88 2.97 V 2.47 2.55 2.64 V 62.5 150 250 ms 3.3V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 5 of 9 ASM1832 October 2006 rev 1.6 Parameter Symbol Conditions Min Typ Max Unit Watchdog Timeout Period tTD TD = VCC 500 1200 2000 ms Watchdog Timeout Period tTD TD Floating 250 610 1000 ms Output Voltage VOH VCC - 0.3V VCC - 0.1V V Output Current IOH Output = 2.4V, VCC >=2.7V 350 µA Output Current IOL Output = 0.4V, VCC >=2.7V Input Leakage IIL RESET Low Level VOL 1 10 Operating Current ICC1 Input Capacitance mA -1.0 Note 1 PBRST pin Internal Pull-up Resistor Output Capacitance I=-500µA, VCC < 2.7.V Note 1.0 µA 0.4 V 40 Outputs open, VCC <= 3.6V kΩ 20 µA CIN 5 pF COUT 7 pF PBRST Manual Reset Minimum Low Time tPB Reset Active Time tRST ST Pulse Width tST and all inputs at VCC or GND PBRST = VIL 20 250 ms 610 1000 ms Must not exceed tRD mini- VCC Fail Detect to RESET or RESET VCC Slew Rate PBRST Stable LOW to RESET and RESET Active VCC Detect to RESET or RESET inactive VCC Slew Rate tRPD mum. Watchdog cannot be disabled. 20 Pulses < 2 µs at VCCTP min- 5 imum will not cause reset tF ns 20 tR trise=5µs 250 µs µs tPDLY tRPU 8 610 0 20 ms 1000 ms ns Notes 1. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. 3.3V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 6 of 9 ASM1832 October 2006 rev 1.6 Package Information MicroSO (8-Pin) Inches Min Millimeteres Max Min Max MicroSO (8-Pin) A 0.032 0.044 0.81 1.10 A1 0.002 0.006 0.05 0.15 A2 0.030 0.038 0.76 0.97 b 0.012 BSC 0.004 0.008 0.10 D 0.114 0.122 2.90 e 0.0256 BSC 0.20 3.10 0.65 BSC E 0.184 0.200 4.67 5.08 E1 0.114 0.122 2.90 3.10 L 0.016 0.026 0.41 S a 0.0206 BSC 0° 0.66 0.52 BSC 6° 0° 6° SO (8-Pin) SO (8-Pin) A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 H E D D A2 A D A1 B 0.193 BSC L 0.25 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H C θ e 0.30 BSC C 0.236 BSC L 0.016 θ 0° 6.00 BSC 0.050 0.41 1.27 8° 0° 8° Plastic DIP (8-Pin) Plastic DIP (8-Pin) A - 0.210 - 5.33 A1 0.015 - 0.38 - A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.36 0.56 b2 0.045 0.070 1.14 1.78 C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 e 0.100 BSC 7.11 2.54 BSC eB - 0.430 - 10.92 L 0.115 0.150 2.92 3.81 3.3V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 7 of 9 ASM1832 October 2006 rev 1.6 Ordering Information Part Number Package Operating Temperature Range Maximum Supply Current (µA) Voltage Monitoring Application Package Marking TIN - LEAD DEVICES ASM1832 8-Pin PDIP -40°C to 85°C 20 3.3 V ASM1832 ASM1832S 8-SO -40°C to 85°C 20 3.3 V ASM1832S ASM1832U 8-MicroSO -40°C to 85°C 20 3.3 V ASM1832 LEAD FREE DEVICES ASM1832F 8-Pin PDIP -40°C to 85°C 20 3.3 V ASM1832F ASM1832SF 8-SO -40°C to 85°C 20 3.3 V ASM1832SF ASM1832UF 8-MicroSO -40°C to 85°C 20 3.3 V ASM1832F 3.3V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 8 of 9 ASM1832 October 2006 PulseCore Semiconductor Corporation 1715 S, Bascom Ave Suit 200, Campbell, CA 95008 Tel:408-879-9077 Fax:408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: ASM1832 Document Version: 1.6 © Copyright 2006 Pulsecore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCOre products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore.) All sales of PulseCOre products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V µP Power Supply Monitor and Reset Circuit 9 of 9