IS61NVVP25672 IS61NVVP51236 ISSI ® 256K x 72 and 512K x 36, 18Mb PIPELINE 'NO WAIT' STATE BUS SRAM ADVANCE INFORMATION JULY 2002 FEATURES DESCRIPTION • 100 percent bus utilization The 16 Meg 'NVVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 256K words by 72 bits, 512K words by 36 bits and are fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. • Interleaved or linear burst sequence control using MODE input • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. • Single +1.8V (± 5%) power supply • JTAG Boundary Scan • Industrial temperature available Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 2.6 4 250 -200 3.2 5 200 Units ns ns MHz Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 1 IS61NVVP25672 IS61NVVP51236 ISSI ® BLOCK DIAGRAM A [0:17] or A [0:18] ADDRESS REGISTER A2-A17 or A2-A18 256Kx72; 512Kx36 MEMORY ARRAY MODE A0-A1 CLK CONTROL LOGIC K CKE WRITE ADDRESS REGISTER BURST ADDRESS COUNTER A'0-A'1 WRITE ADDRESS REGISTER K DATA-IN REGISTER K DATA-IN REGISTER CE CE2 CE2 ADV WE BWŸX } CONTROL REGISTER K CONTROL LOGIC (X=a,b,c,d or a,b) OUTPUT REGISTER BUFFER OE ZZ DQa0-DQd7 or DQa0-DQb8 DQPa-DQPd 2 72 or 36 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE2 A ADV A CE2 A DQb DQb B DQg DQg BWc BWg NC WE A BWb BWf DQb DQb C DQg DQg BWh BWd NC CE NC BWe BWa DQb DQb D DQg DQg GND NC NC OE NC NC GND DQb DQb E DQPg DQPc VCCQ VCCQ VCC VCC VCC VCCQ VCCQ DQPf DQPb F DQc DQc GND GND GND NC GND GND GND DQf DQf G DQc DQc VCCQ VCCQ VCC NC VCC VCCQ VCCQ DQf DQf H DQc DQc GND GND GND NC GND GND GND DQf DQf J DQc DQc VCCQ VCCQ VCC NC VCC VCCQ VCCQ DQf DQf K NC NC CLK NC GND CKE GND NC NC NC NC L DQh DQh VCCQ VCCQ VCC NC VCC VCCQ VCCQ DQa DQa M DQh DQh GND GND GND NC GND GND GND DQa DQa N DQh DQh VCCQ VCCQ VCC NC VCC VCCQ VCCQ DQa DQa P DQh DQh GND GND GND ZZ GND GND GND DQa DQa R DQPd DQPh VCCQ VCCQ VCC VCC VCC VCCQ VCCQ DQPa DQPe T DQd DQd GND NC NC MODE NC NC GND DQe DQe U DQd DQd NC A NC A NC A NC DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe 11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch PIN DESCRIPTIONS A Synchronous Address Inputs A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. GND Ground MODE Burst Sequence Mode Selection OE Output Enable JTAG Boundary Scan Pins ADV Synchronous Burst Address Advance TCK, TDI TDO, TMS BWa-BWh Synchronous Byte Write Enable VCC +1.8V Power Supply CE, CE2, CE2 Synchronous Chip Enable VCCQ Isolated Output Buffer Supply: 1.8V CLK Synchronous Clock WE Write Enable CKE Clock Enable ZZ Snooze Enable DQa-DQh Synchronous Data Input/Output DQPa-DQPh Parity Data Input/Output Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 3 IS61NVVP25672 IS61NVVP51236 ISSI ® PIN CONFIGURATION 119-pin PBGA (Top View) 1 2 3 4 5 6 7 VCCQ A A A A A VCCQ NC CE2 A ADV A CE2 NC A B C NC A A VCC A A NC DQc DQPc GND NC GND DQPb DQb DQc DQc GND CE GND DQb DQb VCCQ DQc GND OE GND DQb VCCQ DQc DQc BWc A BWb DQb DQb DQc DQc GND WE GND DQb DQb VCCQ VCC NC VCC NC VCC VCCQ DQd DQd GND CLK GND DQa DQa D E F G H J K L DQd DQd BWd NC BWa DQa DQa VCCQ DQd GND CKE GND DQa VCCQ DQd DQd GND A1 GND DQa DQa DQd DQPd GND A0 GND DQPa DQa NC A MODE VCC NC A NC NC NC A A A NC ZZ VCCQ TMS TDI TCK TDO NC VCCQ M N P R T U 512K x 36 PIN DESCRIPTIONS 4 A Synchronous Address Inputs A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. GND Ground MODE Burst Sequence Mode Selection OE Output Enable JTAG Boundary Scan Pins ADV Synchronous Burst Address Advance TCK, TDI TDO, TMS BWa-BWh Synchronous Byte Write Enable VCC 1.8V Power Supply CE, CE2, CE2 Synchronous Chip Enable VCCQ Isolated Output Buffer Supply: 1.8V CLK Synchronous Clock WE Write Enable CKE Clock Enable ZZ Snooze Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/Output Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE DS WRITE BURST DS BURST DS DS WRITE WRITE BURST WRITE READ BURST SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Continue Not Selected Not Selected Not Selected Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Address Used CS CS1 CS2 CS CS2 ADV WE BW BWx OE CKE CLK N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address X H X X L X L X L X L X X X X L X H X H X H X H X X X X X H L X L X L X L X X H L L L L H L H L H L H X X X X X H X H X L X L X X X X X X X X X X L L H H X X X X X L L H H X X X X X L L L L L L L L L L L L H ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 5 IS61NVVP25672 IS61NVVP51236 ISSI ® ASYNCHRONOUS TRUTH TABLE(1) Operation ZZ OE I/O STATUS Sleep Mode H L L L L X L H X X High-Z DQ High-Z Din, High-Z High-Z Read Write Deselected Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP WE BW BWa BW BWb BW BWc BW BWd H L L L L L L X L H H H L H X H L H H L H X H H L H L H X H H H L L H Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® WRITE TRUTH TABLE (x72) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE BYTE e WRITE BYTE f WRITE BYTE g WRITE BYTE h WRITE ALL BYTEs WRITE ABORT/NOP WE BW BWa BW BWb BW BWc BW BWd BW BWe BW BWf BW BWg BW BWh H L L L L L L L L L L X L H H H H H H H L H X H L H H H H H H L H X H H L H H H H H L H X H H H L H H H H L H X H H H H L H H H L H X H H H H H L H H L H X H H H H H H L H L H X H H H H H H H L L H Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = VCC) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GND) 0,0 A1', A0' = 1,1 0,1 1,0 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 7 IS61NVVP25672 IS61NVVP51236 ISSI ® ABSOLUTE MAXIMUM RATINGS(1) Symbol TOPR Parameter Operating Temperature TSTG PD IOUT VIN, VOUT VIN Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Com Ind Value –0 to +70 -40 to +85 –65 to +150 1.6 100 –0.5 to VCCQ + 0.3 –0.5 to VCCQ + 0.3 Unit °C °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C VCC 1.8V ± 5% VCCQ 1.8V ± 5% -40°C to +85°C 1.8V ± 5% 1.8V ± 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 1.8V 8 Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = –4.0 mA VCCQ –0.4 — V VOL Output LOW Voltage IOL = 4.0 mA — 0.4 V VIH Input HIGH Voltage 1.1 VCC + 0.3 V VIL Input LOW Voltage –0.3 0.6 V ILI Input Leakage Current GND ≤ VIN ≤ VCC –5 5 µA ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VI –10 10 µA (1) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions -250 MAX x36 x72 -200 MAX x36 x72 Unit ICC AC Operating Supply Current Device Selected, Com. OE = VIH, ZZ ≤ VIL, IND. All Inputs ≤ 0.2V OR ≥ VCC – 0.2V, Cycle Time ≥ tKC min. 450 500 500 550 400 450 450 500 mA ISB Standby Current TTL Input Device Deselected, COM. VCC = Max., Ind. All Inputs ≤ 0.2V OR ≥ VCC – 0.2V, ZZ ≤ VIL, f = Max. 225 — 250 — 175 200 200 230 mA ISBI Standby Current CMOS Input Device Deselected, Com. VCC = Max., Ind. VIN ≤ GND + 0.2V or ≥ VCC – 0.2V f=0 150 — 150 — 150 200 150 200 mA Note: 1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits ±30 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 9 IS61NVVP25672 IS61NVVP51236 ISSI ® 1.8V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 1.4V 2V/ ns 0.9V See Figures 1 and 2 1.8V I/O OUTPUT LOAD EQUIVALENT 317 Ω ZO = 50Ω +1.8V OUTPUT OUTPUT 50Ω 351 Ω 0.9V Figure 1 10 5 pF Including jig and scope Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -250 Min. Max. -200 Min. Max. Symbol Parameter fmax Clock Frequency — 250 — 200 MHz tKC Cycle Time 4.0 — 5 — ns tKH Clock High Time 1.7 — 2 — ns tKL Clock Low Time 1.7 — 2 — ns Clock Access Time — 2.6 — 3.0 ns Clock High to Output Invalid 0.8 — 1.5 — ns tKQLZ Clock High to Output Low-Z 0.8 — 1 — ns tKQHZ(2,3) Clock High to Output High-Z — 2.6 — 3.0 ns tOEQ tKQ tKQX (2) (2,3) Unit Output Enable to Output Valid — 2.6 — 3.0 ns (2,3) Output Enable to Output Low-Z 0 — 0 — ns (2,3) tOEHZ Output Disable to Output High-Z — 2.6 — 3.0 ns tAS Address Setup Time 1.0 — 1.2 — ns tWS Read/Write Setup Time 1.0 — 1.2 — ns tCES Chip Enable Setup Time 1.0 — 1.2 — ns tSE Clock Enable Setup Time 1.0 — 1.2 — ns tADVS Address Advance Setup Time 1.0 — 1.2 — ns tDS Data Setup Time 1.0 — 1.2 — ns tAH Address Hold Time 0.5 — 0.5 — ns tHE Clock EnableHold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tADVH Address Advance Hold Time 0.5 — 0.5 — ns tDH Data Hold Time 0.5 — 0.5 — ns tPDS ZZ High to Power Down — 2 — 2 cyc tPUS ZZ Low to Power Down — 2 — 2 cyc tOELZ Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 11 IS61NVVP25672 IS61NVVP51236 ISSI ® SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit ISB2 Current during SLEEP MODE ZZ ≥ Vih 150 mA tPDS ZZ active to input ignored ZZ ≥ Vih 2 cycle tPUS ZZ inactive to input sampled ZZ ≤ Vil 2 cycle tZZI ZZ active to SLEEP current ZZ ≥ Vih 2 cycle tRZZI ZZ inactive to exit SLEEP current ZZ ≤ Vil 0 ns SLEEP MODE TIMING K tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® READ CYCLE TIMING tKH tKL Clock tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ tDS tKQ tKQHZ tOEHZ Data Out Q1-1 Q2-1 Q2-2 Q2-3 NOTES: WE = H and BWX = H CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined 13 IS61NVVP25672 IS61NVVP51236 ISSI ® WRITE CYCLE TIMING tKH tKL Clock tKC ADV Address A1 A3 A2 WE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-3 Q0-4 NOTES: WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 14 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® SINGLE READ/WRITE CYCLE TIMING tKH tKL Clock tSE tHE tKC CKE Address A1 A2 A3 A4 Q1 Q3 A5 A6 A7 A8 A9 WRITE CS ADV OE tOEQ tOELZ Data Out tDS Data In Q6 Q7 tDH D2 NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 Q4 D5 Don't Care Undefined 15 IS61NVVP25672 IS61NVVP51236 ISSI ® CKE OPERATION TIMING tKH tKL Clock tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CS ADV OE tKQ tKQHZ tKQLZ Data Out Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L 16 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® CS OPERATION TIMING tKH tKL Clock tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CS ADV OE tOEQ tKQHZ tKQ tKQLZ tOELZ Q1 Data Out Q2 Q4 tDS tDH D3 Data In NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 D5 Don't Care Undefined 17 IS61NVVP25672 IS61NVVP51236 ISSI ® IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) TEST ACCESS PORT (TAP) - TEST CLOCK The IS61NVVP51236 and IS61NVVP25672 have a serial boundary scan Test Access Port (TAP) in the PBGA package only. This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 1.8V I/O logic levels. The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. DISABLING THE JTAG FEATURE The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (GND) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VCC through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation. TEST MODE SELECT (TMS) The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level. TEST DATA-IN (TDI) The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. TAP CONTROLLER BLOCK DIAGRAM 0 Bypass Register 2 1 0 Instruction Register TDI Selection Circuitry Selection Circuitry 31 30 29 . . . 2 1 0 2 1 0 TDO Identification Register x . . . . . Boundary Scan Register* TCK TMS 18 TAP CONTROLLER Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMING A TAP RESET A Reset is performed by forcing TMS HIGH (VCC) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state. TAP REGISTERS Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register ISSI is set LOW (GND) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 84-bit-long register and the x72 configuration has a 123-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Scan Register Sizes Register Name Bit Size (x36) Bit Size (x72) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 84 123 Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 ® 19 IS61NVVP25672 IS61NVVP51236 ISSI ® IDENTIFICATION (ID) REGISTER The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Die Revision Code Bit # x72 x36 20 Not Used I/O Configuration ISSI Technology JEDEC Vendor ID Code 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 0 1 Presence Register ID REGISTER CONTENTS 0 1 1 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® TAP INSTRUCTION SET SAMPLE/PRELOAD Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK and CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. RESERVED These instructions are not implemented but are reserved for future use. Do not use these instructions. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 21 IS61NVVP25672 IS61NVVP51236 ISSI ® JTAG TAP INSTRUCTION SET SUMMARY Instruction Code Description EXTEST(1) 000 Places the Boundary Scan Register between TDI and TDO. When EXTEST is selected, data will be driven out of the DQ pad. 001 Preloads ID Register and places it between TDI and TDO. SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all Data and Clock output drivers to High-Z. RFU(1) 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 101 Private instruction. 110 Do not use this instruction; Reserved for Future Use. 111 Places Bypass Register between TDI and TDO. IDCODE(1,2) (1) SAMPLE/PRELOAD(1) Private (1) (1) RFU (1) BYPASS Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state. TAP ELECTRICAL CHARACTERISTICS Over the Operating Range(1,2) Symbol Parameter Test Conditions Min. Max. Units VOH1 Output HIGH Voltage IOH = –100 µA Vcc –0.1 — V VOH2 Output HIGH Voltage IOH = –8 mA Vcc –0.4 — V VOL1 Output LOW Voltage IOL = 100 µA — 0.1 V VOL2 Output LOW Voltage IOL = 8 mA — 0.4 V VIH Input HIGH Voltage 1.2 VCC +0.3 V VIL Input LOW Voltage IOLT = 2mA –0.3 0.6 V IX Input Leakage Current GND ≤ V I ≤ VDDQ –10 10 µA Notes: 1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2, Undershoot:VIL (AC) ≤ 0.5V for t ≤ tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. 22 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® TAP AC ELECTRICAL CHARACTERISTICS(1) (OVER OPERATING RANGE) Symbol Parameter Min. Max. Unit tTCYC TCK Clock cycle time 100 — ns fTF TCK Clock frequency — 10 MHz tTH TCK Clock HIGH 40 — ns tTL TCK Clock LOW 40 — ns tTMSS TMS setup to TCK Clock Rise 10 — ns tTDIS TDI setup to TCK Clock Rise 10 — ns tCS Capture setup to TCK Rise 10 — ns tTMSH TMS hold after TCK Clock Rise 10 — ns tTDIH TDI Hold after Clock Rise 10 — ns tCH Capture hold after Clock Rise 10 — ns tTDOV TCK LOW to TDO valid — 20 ns tTDOX TCK LOW to TDO invalid 0 — ns Notes: 7. tCS and tCHrefer to the set-up and hold time requirements of latching data from the boundary scan register. 8. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 1 Select DR 0 0 1 1 1 Capture DR 0 Shift DR 1 Exit1 DR 0 Select IR 0 1 Exit1 IR 0 Pause DR 0 1 0 1 Exit2 DR 1 Update DR 0 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 Capture IR 0 Shift IR 1 0 Pause IR 1 0 1 1 0 1 0 Exit2 IR 1 Update IR 0 23 IS61NVVP25672 IS61NVVP51236 ISSI ® TAP AC TEST CONDITIONS Input pulse levels 0.2 to 1.6V Input rise and fall times 1ns Input timing reference levels 0.9V Output reference levels 0.9V Test load termination supply voltage 0.9V TAP OUTPUT LOAD EQUIVALENT 50Ω 0.9V TDO 20 pF Z0 = 50Ω GND TAP TIMING 1 2 3 tTHTH 4 5 6 tTLTH TCK tTHTL tMVTH tTHMX TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED 24 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) PH =Place Holder X72 X36 Sequence Pkg. Ball Ball Location Sequence Pkg. Ball 1 A0 W6 1 A0 2 A V7 2 A 3 A V8 3 A 4 A U8 4 A 5 A V9 5 A 6 A U6 6 A (1) 7 PH U5 7 PH(1) 8 A W7 8 A 9 (1) PH U7 9 PH(1) 10 Mode T6 10 Mode 11 NC (2) M6 11 NC(2) 12 NC(2) J6 12 NC(2) 13 CKE K6 13 CKE 14 OE D6 14 OE C7 15 PH(1) 15 PH (1) 16 Be C8 17 Ba C9 16 Ba 18 Bb B8 17 Bb 19 Bf B9 20 W B6 18 W 21 ADV A6 19 ADV 22 A B7 20 A 23 CE2 A8 21 CE2 24 A A9 22 A 25 NC(2) F6 23 NC 26 A A3 24 A 27 CE2 A4 25 CE2 28 A A5 26 A 29 A A7 27 A B5 28 A 29 Bc 30 Bc B3 31 Bg B4 32 Bh C3 33 Bd C4 30 Bd C5 31 PH(1) C6 32 CE G6 33 NC 34 35 36 PH (1) CE (2) NC Ball Location Notes: 1.Input of PH register connected to VSS 2. NC = Don't care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 25 IS61NVVP25672 IS61NVVP51236 ISSI ® BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued: X72 Sequence 37 X36 Pkg. Ball NC Ball Location (2) Sequence H6 34 Pkg. Ball NC Ball Location (2) 38 CK K3 35 CK 39 NC(2) L6 36 NC(2) 40 NC(2) N6 37 NC(2) 41 ZZ P6 38 ZZ 42 A V3 39 A 43 A U4 40 A 44 A V4 41 A 45 A V5 42 A 46 A W5 43 A 47 A V6 44 A1 48 DQd W2 45 DQd 49 DQd W1 46 DQd 50 DQd V2 47 DQd 51 DQd V1 48 DQd 52 DQd U2 49 DQd 53 DQd U1 50 DQd 54 DQd T2 51 DQd 55 DQd T1 52 DQd 53 DQPd 56 DQPd R1 57 DQPh R2 58 DQh P2 59 DQh P1 60 DQh N2 61 DQh N1 62 DQh M2 63 DQh M1 64 DQh L2 65 DQh L1 66 NC (2) K2 54 NC(2) 67 NC(2) K1 55 NC(2) 68 DQc J2 56 DQc 69 DQc J1 57 DQc 70 DQc H2 58 DQc 71 DQc H1 59 DQc 72 DQc G2 60 DQc 73 DQc G1 61 DQc Notes: 1.Input of PH register connected to VSS 2. NC = Don't care 26 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued: X72 X36 Sequence Pkg. Ball Ball Location Sequence Pkg. Ball 74 DQc F2 62 DQc 75 DQc F1 63 DQc 76 DQPc E2 64 DQPc 77 DQPg E1 78 DQg D2 79 DQg D1 80 DQg C2 81 DQg C1 82 DQg B2 83 DQg B1 84 DQg A2 85 DQg A1 86 DQb A10 65 DQb 87 DQb A11 66 DQb 88 DQb B10 67 DQb 89 DQb B11 68 DQb 90 DQb C10 69 DQb 91 DQb C11 70 DQb 92 DQb D10 71 DQb 93 DQb D11 72 DQb 94 DQPb E11 73 DQPb 95 DQPf E10 96 DQf F10 97 DQf F11 98 DQf G10 99 DQf G11 100 DQf H10 101 DQf H11 102 DQf J10 103 DQf J11 104 (2) NC K11 74 NC(2) 105 NC(2) K10 75 NC(2) 106 DQa L10 76 DQa 107 DQa L11 77 DQa 108 DQa M10 78 DQa 109 DQa M11 79 DQa 110 DQa N10 80 DQa Ball Location Notes: 1.Input of PH register connected to VSS 2. NC = Don't care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 27 IS61NVVP25672 IS61NVVP51236 ISSI ® BOUNDARY SCAN ORDER ASSIGNMENTS (by Exit Sequence) Continued: X72 X36 Sequence Pkg. Ball Ball Location Sequence Pkg. Ball 111 DQa N11 81 DQa 112 DQa P10 82 DQa 113 DQa8 P11 83 DQa8 114 DQPa9 R10 84 DQPa9 115 DQPe R11 116 DQe T10 117 DQe T11 118 DQe U10 119 DQe U11 120 DQe V10 121 DQe V11 122 DQe W10 123 DQe W11 Ball Location Notes: 1.Input of PH register connected to VSS 2. NC = Don't care 28 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 IS61NVVP25672 IS61NVVP51236 ISSI ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Frequency Order Part Number Package Industrial Range: -40°C to +85°C Frequency Order Part Number Package 256Kx72 256Kx72 250 IS61NVVP25672-250B PBGA 250 IS61NVVP25672-250BI PBGA 200 IS61NVVP25672-200B PBGA 200 IS61NVVP25672-200BI PBGA 512Kx36 512Kx36 250 IS61NVVP51236-250B PBGA 250 IS61NVVP51236-250BI PBGA 200 IS61NVVP51236-200B PBGA 200 IS61NVVP51236-200BI PBGA Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 29