ISL6206 ® Data Sheet May 2002 FN9071.1 High Voltage Synchronous Rectified Buck MOSFET Driver Features The ISL6206 is a high voltage, high frequency, dual MOSFET driver specifically designed to drive two N-Channel power MOSFETs in a synchronous-rectified buck converter topology in mobile computing applications. This driver combined with an Intersil Multi-Phase Buck PWM controller forms a complete single-stage core-voltage regulator solution for advanced mobile microprocessors. • Adaptive Shoot-Through Protection The ISL6206 features a three-state PWM input that, working together with any Intersil multiphase PWM controllers, will prevent a negative transient on the output voltage when the output is being shut down. This feature eliminates the Schottky diode that is usually seen in a microprocessor power system for protecting the microprocessor from reversed-output-voltage damage. • Internal Bootstrap Schottky Diode The output drivers in the ISL6206 has the capacity to efficiently switch power MOSFETs at frequencies up to 2MHz. Each driver is capable of driving a 3000pF load with a 15ns propagation delay and 20ns transition time. This product implements bootstrapping on the upper gate, reducing implementation complexity and allowing the use of higher performance, cost effective, N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. • High Current Low Output Voltage DC-DC Converters • Drives Two N-Channel MOSFETs • 30V Operation Voltage • Supports High Switching Frequency - Fast Output Rise Time - Propagation Delay 15ns • Three-state Input for Output Stage Shutdown Applications • Core Voltage Supplies for Intel and AMD® Mobile Microprocessors • High Frequency Low Profile DC-DC Converters • High Input Voltage DC-DC Converters Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” Pinout ISL6206CB (SOIC) TOP VIEW Ordering Information PART NUMBER ISL6206CB ISL6206CB-T TEMP. RANGE (oC) -10 to 85 PACKAGE 8 Ld SOIC UGATE 1 8 PHASE BOOT 2 7 NC PWM 3 6 VCC GND 4 5 LGATE PKG. NO. M8.15 8 Ld SOIC Tape and Reel ti 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved AMD® is a registered trademark of Advanced Micro Devices, Inc. ISL6206 Block Diagram ISL6206 VCC BOOT UGATE VCC 10K PWM PHASE SHOOTTHROUGH PROTECTION CONTROL LOGIC VCC LGATE 10K GND Typical Application - Two Phase Converter Using ISL6206 Gate Drivers VBAT +5V +5V +5V +VCORE BOOT VCC FB COMP UGATE VCC VSEN PWM1 PWM DRIVE ISL6206 PHASE PWM2 PGOOD LGATE NC MAIN CONTROL ISEN1 VID VBAT ISEN2 +5V VCC FS BOOT DACOUT GND UGATE PWM DRIVE ISL6206 NC 2 PHASE LGATE ISL6206 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V BOOT Voltage (VBOOT). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 36V Phase Voltage (VPHASE) (Note 1) . . . VBOOT - 7V to VBOOT + 0.3V Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V UGATE. . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 125oC Thermal Resistance θJA (oC/W) SOIC Package (Note 2) . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -10oC to 85oC Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125oC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is shorted to GND. 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM pin floating, VVCC = 5V - 30 - µA VPWM = 5V - 250 - µA VPWM = 0V - -250 - µA VCC SUPPLY CURRENT Bias Supply Current IVCC PWM INPUT Input Current IPWM PWM three-state Rising Threshold VVCC = 5V - - 1.7 V PWM three-state Falling Threshold VVCC = 5V 3.3 - - V three-state Shutdown Holdoff Time VVCC = 5V, Temperature = 25° C - 300 - ns tRUGATE VVCC = 5V, 3nF Load - 20 - ns LGATE Rise Time tRLGATE VVCC = 5V, 3nF Load - 20 - ns UGATE Fall Time tFUGATE VVCC = 5V, 3nF Load - 15 - ns LGATE Fall Time tFLGATE VVCC = 5V, 3nF Load - 15 - ns UGATE Turn-Off Propagation Delay tPDLUGATE VVCC = 5V, 3nF Load - 15 - ns LGATE Turn-Off Propagation Delay tPDLLGATE VVCC = 5V, 3nF Load - 15 - ns SWITCHING TIME UGATE Rise Time OUTPUT Upper Drive Source Resistance RUGATE 500mA Source Current - 3.1 5.0 Ω Upper Driver Source Current (Note 3) IUGATE VUGATE-PHASE = 2.5V - 700 - mA Ω Upper Drive Sink Resistance RUGATE 500mA Sink Current - 1.5 2.6 Upper Driver Sink Current (Note 3) IUGATE VUGATE-PHASE = 2.5V - 1.1 - A Lower Drive Source Resistance RLGATE 500mA Source Current - 3.1 5.0 Ω Lower Driver Source Current (Note 3) ILGATE VLGATE = 2.5V - 700 - mA Lower Drive Sink Resistance RLGATE 500mA Sink Current - 1.5 2.6 Ω Lower Driver Sink Current (Note 3) ILGATE VLGATE = 2.5V - 1.1 - A NOTE: 3. Guaranteed by design, not tested. 3 ISL6206 Functional Pin Description PHASE (Pin 8) UGATE (Pin 1) Upper gate drive output. Connect to the gate of the high-side N-Channel power MOSFET. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver. Description BOOT (Pin 2) Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Bootstrap Diode and Capacitor section under DESCRIPTION for guidance in choosing the appropriate capacitor value. PWM (Pin 3) The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of any Intersil multiphase controllers. GND (Pin 4) Ground pin. All signals are referenced to this node. LGATE (Pin 5) Lower gate drive output. Connect to the gate of the low-side N-Channel power MOSFET. VCC (Pin 6) Connect this pin to a +5V bias supply. Place a high quality bypass capacitor from this pin to GND. NC (Pin 7) No connection. Leave this pin floating. Operation The ISL6206 dual MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [tPDLLGATE], the lower gate begins to fall. Typical fall times [tFLGATE] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [tPDHUGATE] based on how quickly the LGATE voltage drops below 1V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shootthrough. Once this delay period is complete the upper gate drive begins to rise [tRUGATE] and the upper MOSFET turns on. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLUGATE] is encountered before the upper gate begins to fall [tFUGATE]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, tPDHLGATE. The upper MOSFET gate voltage is monitored and the lower gate is allowed to rise after the upper MOSFET gate-to-source voltage drops below 1V. The lower gate then rises [tRLGATE], turning on the lower MOSFET. Timing Diagram PWM tPDHUGATE tPDLUGATE tRUGATE tFUGATE UGATE LGATE tRLGATE tFLGATE tPDLLGATE tPDHLGATE 4 ISL6206 Three-state PWM Input Power Dissipation A unique feature of the ISL6206 and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled. Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125oC. The maximum allowable IC power dissipation for the SO-8 package is approximately 800mW. When designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the driver is approximated as: Adaptive Shoot-Through Protection Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the gate driver has turned off one MOSFET before the gate voltage of the other MOSFET is allowed to rise. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise. Bootstrap Diode and Capacitor This driver features an internal Schottky bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap capacitor must have a maximum voltage rating above the maximum battery voltage plus 5V. The bootstrap capacitor can be chosen from the following equation: Q GATE C BOOT ≥ -----------------------∆V BOOT where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The ∆VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125µF is required. The next larger standard value capacitance is 0.22µF. A good quality ceramic capacitor is recommended. 5 P = fsw ( 1.5V U Q + V L Q ) + I DDQ V U L CC where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltage. QU and QL is the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The IDDQ VCC product is the quiescent power of the driver and is negligible ISL6206 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA 0.25(0.010) M H 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- µα e A1 B 0.25(0.010) M C C A M B S MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.10(0.004) 0.050 BSC 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC 0.2284 0.2440 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o α 5.80 8 0o 6.20 - H N NOTES: MILLIMETERS MIN 8 - 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6