ISL88042 ® Data Sheet July 26, 2010 FN6655.2 Quadruple Voltage Monitor Features The ISL88042 is a Quadruple voltage-monitoring supervisor combining competitive reset threshold accuracy and low power consumption. This device combines popular functions such as Power-On Reset, Undervoltage Supply Supervision, reset signaling and Manual Reset. Monitoring four different supplies in a 8 Ld 2x3 TDFN package, the ISL88042 devices can help to lower system cost, reduce board space requirements, and increase the reliability of multi-voltage systems. • Quadruple Voltage Monitoring Low VDD detection circuitry protects the user’s system from low voltage conditions, resetting the system when VDD or any of the other monitored power supply voltages fall below their respective minimum voltage thresholds. The reset signal remains asserted until all of these voltages return to proper operating levels and stabilize. • Immune to Power-Supply Transients Two of the four voltage monitors have preset thresholds for either dual 3.3V or one each for one 5V and one 3.3V supplies. Users can adjust the threshold voltages of the third and fourth voltage monitors in order to meet specific system level requirements. • Telecom and Datacom Systems Pinout • Desktop and Notebook Computer Systems • Fixed-Voltage Options Allow Precise Monitoring of +5.0V and +3.3V Power Supplies • Two Adjustable Voltage Inputs Monitor Voltages > 0.6V • 95ms Nominal Reset Pulse Width • Manual Reset Capability • Reset Signals Valid Down to VDD = 1V • Low 22µA Maximum Supply Current at 5V • Pb-Free (RoHS Compliant) Applications • Routers and Servers • Access Concentrators • Cable/Satellite Applications • Data Storage Equipment ISL88042 (8 LD TDFN) TOP VIEW MR 1 VDD 2 V2MON 3 GND 4 EPAD (GND) • Set-Top Boxes • Industrial Equipment 8 RST 7 VDDA 6 V4MON 5 V3MON • Multi-Voltage Systems Ordering Information PART NUMBER (Notes 1, 2) PART MARKING VTH1 (V) VTH2 (V) TEMP RANGE (°C) PACKAGE Tape & Reel (Pb-free) PKG. DWG. # ISL88042IRTHFZ-T 4P6 4.60 3.09 -40 to +85 8 Ld TDFN L8.2x3A ISL88042IRTHFZ-TK 4P6 4.60 3.09 -40 to +85 8 Ld TDFN L8.2x3A ISL88042IRTEEZ-T 2P9 2.87 2.95 -40 to +85 8 Ld TDFN L8.2x3A ISL88042IRTEEZ-TK 2P9 2.87 2.95 -40 to +85 8 Ld TDFN L8.2x3A ISL88042IRTJJZ-T 2P8 2.78 2.86 -40 to +85 8 Ld TDFN L8.2x3A ISL88042IRTJJZ-TK 2P8 2.78 2.86 -40 to +85 8 Ld TDFN L8.2x3A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL88042 Pin Descriptions ISL88042 PIN NUMBER PIN NAME 1 MR Active-Low open drain manual reset input with internal pull-up resistor 2 VDD Chip Bias Input and primary integrated preset undervoltage monitor 3 V2MON 4 GND 5 V3MON Adjustable undervoltage monitor input 6 V4MON Adjustable undervoltage monitor input 7 VDDA Must be tied to VDD for proper operation 8 RST Active-low open drain reset output FUNCTION Secondary integrated preset undervoltage monitor input Ground Functional Block Diagram VDD MR POR PB ¬ VREF RST tPOR V2MON V4MON ¬ VREF VREF ¬ V3MON GND 2 VREF ¬ FN6655.2 July 26, 2010 ISL88042 Absolute Maximum Ratings Thermal Information Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Voltage on VDD with Respect to GND. . . . . . . . . . . . . . -1.0V to +7V Voltage on V3MON, V4MON . . . . . . . . . . . . . . . . . . . . . . -1.0V to 3V Voltage on Any Other Pin. . . . . . . . . . . . . . . . . -1.0V to VDD + 0.3V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld TDFN Package (Notes 3, 4). . . . . 60 8 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Temperature Range (Industrial) . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications SYMBOL Over the recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS 5.5 V VDD Supply Voltage Range IDD1 VDD Supply Current VDD = 5.0V 14 22 µA IDD2 V2MON Input Current V2MON = 3.3V 5.5 8 µA IDDA V3MON, V4MON Input Current V3MON, V4MON = 1.0V 19 100 nA 2.0 VOLTAGE THRESHOLDS VTH1 VTH1HYST VTH2 VTH2HYST Fixed Voltage Trip Point for VDD Hysteresis of VTH1 Fixed Voltage Trip Point for V2MON Hysteresis of VTH2 ISL88042IRTHFZ 4.370 4.600 4.830 V ISL88042IRTEEZ 2.734 2.872 3.010 V ISL88042IRTJJZ 2.647 2.780 2.914 V VTH1 = 4.60V 92 mV VTH1 = 2.87V 58 mV VTH1 = 2.78V 58 mV ISL88042IRTHFZ 2.936 3.090 3.245 V ISL88042IRTEEZ 2.815 2.957 3.099 V ISL88042IRTJJZ 2.725 2.860 3.000 V VTH2 = 3.09V 61 mV VTH2 = 2.96V 60 mV VTH2 = 2.86V 60 VREF ISL88042IRTHFZ, ISL88042IRTEEZ Adj. Reset Threshold Voltage VTH for V3MON, V4MON 0.572 0.600 0.630 V VREF ISL88042IRTJJZ Adj. Reset Threshold Voltage VTH for V3MON, V4MON 0.554 0.581 0.610 V VREFHYST Hysteresis Voltage 12 mV RESET VOL Reset Output Voltage Low tRPD VTH to Reset Asserted Delay tPOR POR Timeout Delay 3 VDD ≥ 3.3V, Sinking 2.5mA 0.05 0.40 V VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V 6 V3MON, V4MON < 3V 40 95 µs 150 ms FN6655.2 July 26, 2010 ISL88042 Electrical Specifications SYMBOL Over the recommended operating conditions, unless otherwise specified. (Continued) PARAMETER MIN (Note 5) TEST CONDITIONS TYP MAX (Note 5) UNITS 0.8 V MANUAL RESET VMRL MR Input Voltage Low VMRH MR Input Voltage High tMR MR Minimum Pulse Width RPU Internal Pull-Up Resistor VDD - 0.6 V 550 ns 10 kΩ NOTE: 5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Pin Descriptions . RST VDD RST The RST output is an open drain output, which is asserted low whenever the following occurs: V2MON MR 1. The device is initially powered up to 1V or 2. VDD, V2MON, V3MON or V4MON fall below their minimum voltage sense level. MR ISL88042 V3MON PB RESET SIGNAL V4MON The MR input is an active low debounced input to which a user can connect a push-button to add manual reset capability or use a signal to pull low. MR has an internal pull-up resistor. VDD The VDD pin is the IC power supply terminal. The voltage at this pin is compared against an internal factory-programmed voltage trip point, VTH1. RST is first asserted low when the device is initially powered and VDD < 1V and then at any time thereafter when VDD falls below VTH1. The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief power-supply transients. V2MON The V2MON input is the second preset monitored voltage that causes the RST output to go low when the voltage on V2MON falls below VTH2. V3MON, and V4MON The VxMON inputs provide monitoring and UV compliance of three additional voltages through resistor dividers. A reset is issued on the ISL88042 if the voltage on any VxMON falls below the internal VREF of 0.6V. GND FIGURE 1. TYPICAL APPLICATION DIAGRAM Principles of Operation The ISL88042 device provides those functions needed for monitoring critical voltages, such as power-supply and battery functions in microprocessor systems. It provides such features as Power-On Reset control, supply voltage supervision, and Manual Reset Assertion. The integration of all these features along with competitive reset threshold accuracy and low power consumption, makes the ISL88042 device suitable for a wide variety of applications needing multi-voltage monitoring. See Figure 1 for the “Typical Application Diagram”. Low Voltage Monitoring During normal operation, the ISL88042 monitors the voltage levels of VDD, V2MON, V3MON and V4MON. If the voltage on any of these four inputs falls below their respective voltage trip points, a reset is asserted (RST = low) to prevent the microprocessor from operating during a power failure or brownout condition. This reset signal remains low until the voltages exceeds the voltage threshold settings for the reset time delay period tPOR. The ISL88042 allows users to customize the minimum voltage sense level for two of the four monitored voltages. For example, the user can adjust the voltage input trip point (VTRIP) for the V3MON and V4MON inputs. To do this, connect an external resistor divider network to the VxMON pin in order to set the trip 4 FN6655.2 July 26, 2010 ISL88042 point to some other voltage above 600mV according to Equation 1: V TRIP = 0.6V × R 1 + R 2 / R 2 (EQ. 1) The reset signal remains active until VDD rises above the minimum voltage sense level for time period tPOR. This ensures that the supply voltage has stabilized to sufficient operating levels. Power-On Reset (POR) Manual Reset Applying power to the ISL88042 activates a POR circuit, which makes the reset pin(s) active (i.e. RST goes high while RST goes low). These signals provide several benefits: The manual-reset input (MR) allows the user to trigger a reset by using a push-button switch or by signaling the input low. The MR input is an active low debounced input. Reset is asserted if the MR pin is pulled low to less than 100mV for the minimum MR pulse width or longer while the push-button is closed. After MR is released, the reset output remains asserted low for tPOR (200ms) and then is released. • They prevent the system microprocessor from starting to operate with insufficient voltage. • They prevent the processor from operating prior to stabilization of the oscillator. Figures 2 and 3 illustrate the ISL88042’s operation. • They ensure that the monitored device is held out of operation until internal registers are properly loaded. • They allow time for an FPGA to download its configuration prior to initialization of the circuit. VTH1/VTH2 VDD / V2MON 1V >tMR MR tPOR tRPD tPOR tPOR RST >tMD FIGURE 2. POWER SUPPLY MONITORING DIAGRAM VXMON VTH tRPD tPOR RST FIGURE 3. VOLTAGE MONITORING DIAGRAM 5 FN6655.2 July 26, 2010 ISL88042 The ISL88042EVAL1Z and Applications Special Application Considerations The ISL88042EVAL1Z supports all variants of the ISL88042 devices, enabling evaluation of basic functional operation and common application implementations. Figure 10 illustrates the ISL88042EVAL1Z in schematic and photographic forms. The ISL88042EVAL1Z is populated with the ISL88042IRTEEZ (VDD VTH1 and V2MON VTH2 = 2.90V). Using good decoupling practices on bias and other monitoring inputs will prevent transients (i.e. due to switching noises and short duration droops in the supply voltage) from causing unwanted resets. With adequate bias on the two preset and the two adjustable monitor inputs the RST output will release to pull high indicating that all supplies are compliant for a minimum of tPOR. For the ISL88042EVAL1Z as shipped, the VDD and V2MON nominal thresholds are as previously noted with the voltage thresholds being monitored by V3MON and V4MON being left open for programming via the non populated resistor dividers. In unusually noisy environments or situations where unwanted signals may be injected into the adjustable VMON inputs, lowering the node impedance and/or positioning a small valued filter capacitor as close to the pin as possible can increase noise immunity. Although the internal ISL88042 threshold references are guaranteed over the full temp range, accuracy errors due to external component tolerances and distribution losses will occur. High tolerance resistors and layout for extreme accuracy and critical performance must be considered. Typical Performance Curves ISL88042IRTHF VDD 3.10 3.05 ISL88042IRTHF V2MON 3.00 ISL88042IRTEE V2MON 2.80 ISL88042IRTJJ V2MON 2.75 ISL88042IRTJJ VDD -40 -20 0 4.59 605 4.58 600 4.56 ISL88042IRTEE VDD 2.85 2.70 610 4.57 2.95 2.90 4.60 25 50 85 TEMPERATURE (°) 4.55 100 125 590 575 4.53 570 BIAS CURRENT (µA) 14 95 90 85 80 ISL88042IRTJJ V3MON -40 -20 0 25 50 85 TEMPERATURE (°C) 100 125 FIGURE 5. V3MON and V4MON Vth vs TEMPERATURE 16 100 ISL88042IRTJJ V4MON 580 115 105 ISL88042IRTHF ISL88042IRTEE V3MON 585 120 110 ISL88042IRTHF ISL88042IRTEE V4MON 595 4.54 FIGURE 4. VDD and V2MON Vth vs TEMPERATURE tPOR (ms) VXMON Vth (mV) VDD & V2MON Vth (V) 3.20 3.15 VDD = 5V 12 10 8 6 4 V2MON = 3.3V 2 -40 -20 0 25 50 85 TEMPERATURE (°C) 100 FIGURE 6. tpor vs TEMPERATURE 6 125 0 -40 -20 0 25 50 85 TEMPERATURE (°C) 100 125 FIGURE 7. BIAS CURRENT vs TEMPERATURE FN6655.2 July 26, 2010 ISL88042 Typical Performance Curves RST 1V/DIV RST 1V/DIV tRPD = 4.3µs tPOR = 94ms VMON = 0.5V/DIV VMON = 0.5V/DIV 20ms/DIV 1µs/DI FIGURE 9. ISL88042 tPOR FIGURE 8. ISL88042 tRPD VDD MRST A MR RST VDD VDD R2 10k U1 RST C1 OPEN V2MON AGND A V2MON V4MON GND V3MON V4MON R5 OPEN R3 OPEN V4 V3 V3MON ISL88042 R4 OPEN R6 OPEN A FIGURE 10. ISL88042EVAL1Z SCHEMATIC AND PHOTOGRAPH All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN6655.2 July 26, 2010 ISL88042 Package Outline Drawing L8.2x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE WITH E-PAD Rev 1, 06/09 0.25 B 0.50 2.20 6 PIN 1 INDEX AREA (4X) 6 PIN #1 INDEX AREA 3.00 A 1.80 +0.1/ -0.15 2.00 0.15 (8x0.40) 1.65 +0.1/ -0.15 TOP VIEW BOTTOM VIEW (8x0.25) PACKAGE OUTLINE (6x0.50) 0.75 SEE DETAIL "X" SIDE VIEW 1.80 3.00 0.05 (8x0.40) 1.65 C 0.20 REF C BASE PLANE SEATING PLANE 0.08 C 5 (8x0.20) 0.05 2.00 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.20mm and 0.32mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 8 FN6655.2 July 26, 2010