INTERSIL ISL89163FBECZ

ISL89163, ISL89164, ISL89165
Features
The ISL89163, ISL89164, and ISL89165 are high-speed,
6A, dual channel MOSFET drivers with enable inputs.
These parts are identical to the ISL89160, ISL89161,
ISL89162 drivers but with an added enable input for
each channel occupying NC pins 1 and 8 of the
ISL89160, ISL89161, ISL89162.
• Dual output, 6A peak current (sink and source)
Precision thresholds on all logic inputs allow the use of
external RC circuits to generate accurate and stable time
delays on both the main channel inputs, INA and INB,
and the enable inputs, ENA and ENB. The precision
delays capable of these precise logic threshold makes
these parts very useful for dead time control and
synchronous rectifiers. Note that the ENable and INput
logic inputs can be interchanged for alternate logic
implementations.
Three input logic thresholds are available: 3.3V (CMOS),
5.0V (CMOS or TTL compatible), and CMOS thresholds
that are proportional to VDD.
At high switching frequencies, these MOSFET drivers
use very little internal bias currents. Separate,
non-overlapping drive circuits are used to drive each
CMOS output FET to prevent shoot-thru currents in the
output stage.
The under voltage lockout (UV) insures that driver
outputs remain off (low) during turn-on until VDD is
sufficiently high for correct logic control. This prevents
unexpected glitches when VDD is being turn-on or
turn-off.
INA
GND
INB
ENB
8
1
7
2
3
EPAD
OUTA
6
5
4
• Very low thermal impedance (θJC = 3°C/W)
• Input logic levels for 3.3V CMOS, 5V CMOS, TTL and
Logic levels proportional to VDD
• Hysteretic logic inputs for high noise immunity
• Precision threshold inputs for time delays with
external RC components
• ~ 20ns rise and fall time driving a 10nF load.
• Low operating bias currents
Applications
• Synchronous Rectifier (SR) Driver
• Switch mode power supplies
• Motor Drives, Class D amplifiers, UPS, Inverters
• Pulse Transformer driver
• Clock/Line driver
Related Literature
• AN1602 “ISL8916xA, ISL8916xB, ISL8916xC,
Evaluation Board User’s Guide”
• AN1603 “ISL6752_54 Evaluation Board Application
Note”
Temp Stable Logic Thresholds
VDD
ENA
• Specified Miller plateau drive currents
OUTB
4.7µF
OPTION B THRESHOLDS (5.0V)
Typical Application
• Dual AND-ed input logic, (INput and ENable)
• Typical ON-resistance <1Ω
3.0
POSITIVE THRESHOLD LIMITS
2.5
2.0
1.5
NEGATIVE THRESHOLD LIMITS
1.0
0.5
0.0
-40 -25 -10
October 12, 2010
FN7707.0
1
5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL89163, ISL89164, ISL89165
High Speed, Dual Channel, 6A, Power MOSFET
Driver with Enable Inputs
ISL89163, ISL89164, ISL89165
Block Diagram
VDD
FOR OPTIONS A AND B,
THE UV COMPARATOR
HOLDS OFF THE OUTPUTS
UNTIL VDD ~> 3.3VDC.
FOR OPTION C, THE UV
RELEASE IS ~> 6.5V
FOR CLARITY, ONLY
ONE CHANNEL IS
SHOWN
SEPARATE FET DRIVES, WITH NONOVERLAPPING OUTPUTS, PREVENT
SHOOT-THRU CURRENTS IN THE
OUTPUT CMOS FETS RESULTING
WITH VERY LOW HIGH FREQUENCY
OPERATING CURRENTS.
ENx
ISL89163
ENX AND INX INPUTS
ARE IDENTICAL AND
MAY BE INTERCHANGED
FOR ALTERNATE LOGIC
OUTx
INx
10k
ISL89164, ISL89165
GND
EPAD
FOR PROPER THERMAL AND
ELECTRICAL PERFORMANCE, THE
EPAD MUST BE CONNECTED TO
THE PCB GROUND PLANE.
Pin Configurations
ISL89163FR, ISL89163FB
(8 LD TDFN, EPSOIC)
TOP VIEW
Pin Descriptions
ISL89164FR, ISL89164FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ENA 1
8 ENB
ENA 1
8 ENB
INA 2
7 OUTA
INA 2
7 /OUTA
GND 3
INB 4
6 VDD
5 OUTB
GND 3
INB 4
ISL89165FR, ISL89165FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ENA 1
8 ENB
INA 2
7 /OUTA
GND 3
6 VDD
5 /OUTB
DESCRIPTION
(See Truth Table for
Logic Polarities)
PIN
NUMBER SYMBOL
1
ENA
Channel A enable, 0V to VDD
2
INA
Channel A input, 0V to VDD
3
GND
Power Ground, 0V
4
INB
Channel B enable, 0V to VDD
5
OUTB,
/OUTB
6
VDD
7
OUTA,
/OUTA
Channel A output, 0V to VDD
8
ENB
Channel B enable, 0V to VDD
Channel B output
Power input, 4.5V to 16V
EPAD
Power Ground, 0V
6 VDD
INB 4
5 /OUTB
ENx
OUTx
INx
ENx
OUTx
INx
NON-INVERTING
INVERTING
ENx* INx* OUTx*
ENx* INx* OUTx*
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
1
1
1
1
1
0
*SUBSTITUTE A OR B FOR x
2
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Ordering Information
PART NUMBER
(Notes 1, 2, 3, 4)
ISL89163FRTAZ
PART
MARKING
163A
TEMP RANGE
(°C)
INPUT
CONFIGURATION
INPUT LOGIC
-40 to +125
non-inverting
3.3V
PACKAGE
(Pb-Free)
PKG.
DWG. #
8 Ld 3x3 TDFN L8.3x3I
ISL89163FRTBZ
163B
-40 to +125
5.0V
8 Ld 3x3 TDFN L8.3x3I
ISL89163FRTCZ
163C
-40 to +125
VDD
8 Ld 3x3 TDFN L8.3x3I
ISL89164FRTAZ
164A
-40 to +125
3.3V
8 Ld 3x3 TDFN L8.3x3I
ISL89164FRTBZ
164B
-40 to +125
5.0V
8 Ld 3x3 TDFN L8.3x3I
inverting
ISL89164FRTCZ
164C
-40 to +125
ISL89165FRTAZ
165A
-40 to +125
ISL89165FRTBZ
165B
-40 to +125
ISL89165FRTCZ
165C
-40 to +125
ISL89163FBEAZ
89163 FBEAZ
-40 to +125
3.3V
8 Ld EPSOIC
M8.15D
ISL89163FBEBZ
89163 FBEBZ
-40 to +125
5.0V
8 Ld EPSOIC
M8.15D
ISL89163FBECZ
89163 FBECZ
-40 to +125
VDD
8 Ld EPSOIC
M8.15D
ISL89164FBEAZ
89164 FBEAZ
-40 to +125
3.3V
8 Ld EPSOIC
M8.15D
inverting + noninverting
non-inverting
inverting
VDD
8 Ld 3x3 TDFN L8.3x3I
3.3V
8 Ld 3x3 TDFN L8.3x3I
5.0V
8 Ld 3x3 TDFN L8.3x3I
VDD
8 Ld 3x3 TDFN L8.3x3I
ISL89164FBEBZ
89164 FBEBZ
-40 to +125
5.0V
8 Ld EPSOIC
M8.15D
ISL89164FBECZ
89164 FBECZ
-40 to +125
VDD
8 Ld EPSOIC
M8.15D
ISL89165FBEAZ
89165 FBEAZ
-40 to +125
3.3V
8 Ld EPSOIC
M8.15D
ISL89165FBEBZ
89165 FBEBZ
-40 to +125
5.0V
8 Ld EPSOIC
M8.15D
ISL89165FBECZ
89165 FBECZ
-40 to +125
VDD
8 Ld EPSOIC
M8.15D
inverting + noninverting
NOTES:
1. Add “-T”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Input Logic Voltage: A = 3.3V, B = 5.0V, C = VDD.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL89163, ISL89164, ISL89165. For more
information on MSL, please see Technical Brief TB363.
3
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD Relative to GND . . . . . . . . -0.3V to 18V
Logic Inputs (INA, INB, ENA, ENB) GND - 0.3v to VDD + 0.3V
Outputs (OUTA, OUTB). . . . . . . . . GND - 0.3v to VDD + 0.3V
Average Output Current (Note 7) . . . . . . . . . . . . . . . 150mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . 200V
Charged Device Model Class IV . . . . . . . . . . . . . . . . . 1000V
8 Ld TDFN Package (Notes 5, 6). . .
44
3
8 Ld EPSOIC Package (Notes 5, 6) .
42
3
Max Power Dissipation at +25°C in Free Air . . . . . . . . . 2.27W
Max Power Dissipation at +25°C with Copper Plane . . . 33.3W
Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temp Range . . . . . . . . . -40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Latch-Up
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Maximum Recommended Operating
Conditions
Junction Temperature. . . . . . . . . . . . .
Options A and B
Supply Voltage, VDD Relative to GND
Logic Inputs (INA, INB, ENA, ENB) . .
Outputs (OUTA, OUTB) . . . . . . . . . .
Option C
Supply Voltage, VDD Relative to GND
Logic Inputs (INA, INB, ENA, ENB) . .
Outputs (OUTA, OUTB) . . . . . . . . . .
. . . . -40°C to +125°C
. . . . . . . . 4.5V to 16V
. . . . . . . . 0V to VDD
. . . . . . . . 0V to VDD
. . . . . . . . 7.5V to 16V
. . . . . . . . 0V to VDD
. . . . . . . . 0V to VDD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output
current. The peak output currents of this driver are self limiting by transconductance or rDS(ON) and do not required any
external components to minimize the peaks. If the output is driving a non-capacitive load, such as an LED, maximum output
current must be limited by external means to less than the specified absolute maximum.
DC Electrical Specifications
VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.
Boldface limits apply over the operating junction temperature range,
-40°C to +125°C.
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
(Note 8)
MAX
(Note 8)
UNITS
POWER SUPPLY
Voltage Range (Option A
and B)
VDD
-
-
-
4.5
16
V
Voltage Range (Option C)
VDD
-
-
-
7.5
16
V
VDD Quiescent Current
IDD
ENx = INx = GND
-
5
-
-
-
mA
INA = INB = 1MHz, square wave
-
25
-
-
mA
-
3.3
-
-
UNDERVOLTAGE
VDD Undervoltage
Lock-out (Option A or B)
(Note 12)
VUV
VDD Undervoltage
Lock-out (Option C)
VUV
ENA = ENB = True
INA = INB = True (Note 9)
-
V
-
6.5
-
-
-
Hysteresis (Option A or B)
-
~25
-
-
-
mV
Hysteresis (Option C)
-
~0.95
-
-
-
V
4
V
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
DC Electrical Specifications
VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.
Boldface limits apply over the operating junction temperature range,
-40°C to +125°C. (Continued)
TJ = +25°C
PARAMETERS
SYMBOL
TJ = -40°C to +125°C
MIN
TYP
MAX
MIN
(Note 8)
MAX
(Note 8)
UNITS
Option A, B, or C
-
-
-
GND
VDD
V
Option A, nominally 37% x 3.3V
-
1.22
-
1.12
1.32
V
Option B, nominally 37% x 5.0V
-
1.85
-
1.70
2.00
V
Option C, nominally 20% x 12V
(Note 9)
-
2.4
-
2.00
2.76
V
Option A, nominally 63% x 3.3V
-
2.08
-
1.98
2.18
V
Option B, nominally 63% x 5.0V
-
3.15
-
3.00
3.30
V
Option C, nominally 80% x12V
(Note 9)
-
9.6
-
9.24
9.96
V
-
2
-
-
-
pF
-
-
-
-10
+10
µA
TEST CONDITIONS
INPUTS
Input Range for INA, INB
VIN
Logic 0 Threshold
for INA, INB, ENA, ENB
(Note 11)
VIL
Logic 1 Threshold
for INA, INB, ENA, ENB
(Note 11)
VIH
Input Capacitance of INA,
INB, ENA, ENB (Note 10)
CIN
Input Bias Current
for INA, INB, ENA, ENB
IIN
GND<VIN<VDD
OUTPUTS
High Level Output Voltage
VOHA
VOHB
-
-
-
VDD - 0.1
VDD
V
Low Level Output Voltage
VOLA
VOLB
-
-
-
GND
GND + 0.1
V
Peak Output Source
Current
IO
VO (initial) = 0V, CLOAD = 10nF
-
-6
-
-
-
A
Peak Output Sink Current
IO
VO (initial) =12V, CLOAD = 10nF
-
+6
-
-
-
A
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. The nominal 20% and 80% thresholds for option C are valid for any value of VDD.
10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated
by the PCB parasitic capacitance.
11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input
voltage for the inverted inputs is less than the logic 0 threshold voltage.
12. A 200µs delay further inhibits the release of the output state when the UV positive going threshold is crossed.
5
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
AC Electrical Specifications
VDD = 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface
limits apply over the operating junction temperature range,
-40°C to +125°C.
PARAMETERS
SYMBOL
TJ = +25°C
TEST
TJ = -40°C to +125°C
CONDITIONS
/NOTES
MIN TYP MAX
MIN
MAX
UNITS
Output Rise Time (see Figure 2)
tR
CLOAD = 10 nF,
10% to 90%
-
20
-
-
40
ns
Output Fall Time (see Figure 2)
tF
CLOAD = 10 nF,
90% to 10%
-
20
-
-
40
ns
Output Rising Edge Propagation Delay for
Non-Inverting Inputs (see Figure 1)
tRDLYn
No load
-
25
-
-
50
ns
Output Rising Edge Propagation Delay with
Inverting Inputs (see Figure 1)
tRDLYi
No load
-
25
-
-
50
ns
Output Falling Edge Propagation Delay with
Non-Inverting Inputs (see Figure 1)
tFDLYn
No load
-
25
-
-
50
ns
Output Falling Edge Propagation Delay with
Inverting Inputs (see Figure 1)
tFDLYi
No load
-
25
-
-
50
ns
Rising Propagation Matching (see Figure 1)
tRM
-
<1ns
-
-
-
ns
Falling Propagation Matching (see Figure 1)
tFM
-
<1ns
-
-
-
ns
Miller Plateau Sink Current
(See Test Circuit Figure 3)
-IMP
VDD = 10V,
VMILLER = 5V
-
6
-
-
-
A
-IMP
VDD = 10V,
VMILLER = 3V
-
4.7
-
-
-
A
-IMP
VDD = 10V,
VMILLER= 2V
-
3.7
-
-
-
A
IMP
VDD = 10V,
VMILLER = 5V
-
5.2
-
-
-
A
IMP
VDD = 10V,
VMILLER = 3V
-
5.8
-
-
-
A
IMP
VDD = 10V,
VMILLER = 2V
-
6.9
-
-
-
A
Miller Plateau Source Current
(See Test Circuit Figure 4)
6
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Test Waveforms and Circuits
INA,
INB
50%
3.3V*
50%
tRDLY
0V
tFDLY
90%
/OUTA
OUTA
tRDLY
tFDLY
OUTA
OR
OUTB
/OUTB
OUTB
tRM
10%
tR
tF
tFM
* LOGIC LEVELS: A OPTION = 3.3V, B OPTION = 5.0V,
C OPTION = VDD
FIGURE 1. PROP DELAYS AND MATCHING
FIGURE 2. RISE/FALL TIMES
10V
10V
ISL8916x
ISL8916x
0.1µF
10k
0.1µF
10k
VMILLER
VMILLER
10µF
200ns
10µF
200ns
10nF
+ISENSE
+ISENSE
10nF
50m
50m
-ISENSE
-ISENSE
FIGURE 3. MILLER PLATEAU SINK CURRENT TEST
CIRCUIT
10V
FIGURE 4. MILLER PLATEAU SOURCE CURRENT TEST
CIRCUIT
IMP
CURREN T THROUGH
0.1 Ω RESISTOR
0A
V M IL LER
V O UT
V M IL LER
-I M P
V O UT
CURREN T THROUGH
0.1Ω RESISTOR
0
0V
200 ns
FIGURE 5. MILLER PLATEAU SINK CURRENT
7
200ns
FIGURE 6. MILLER PLATEAU SOURCE CURRENT
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Typical Performance Curves
35
+125°C
+125°C
1MHz BIAS CURRENT (mA)
STATIC BIAS CURRENT (mA)
3.5
3.0
+25°C
-40°C
2.5
2.0
4
8
12
30
+25°C
25
-40°C
20
15
10
5
16
4
8
12
VDD
16
VDD
FIGURE 8. IDD vs VDD (1 MHz)
FIGURE 7. IDD vs VDD (STATIC)
50
1.1
16V
NO LOAD
10V
30
12V
20
5V
rDS(ON) (Ω)
IDD (mA)
40
VOUT LOW
1.0
10
0
0.9
VOUT HIGH
0.8
0.7
0.6
0
0.5
-45
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
-20
5
FREQUENCY (MHz)
FIGURE 9. IDD vs FREQUENCY (+25°C)
55
80
105
130
FIGURE 10. rDS(ON) vs TEMPERATURE
3.5
3.5
INPUT LOGIC THRESHOLDS (3.3V)
INPUT LOGIC THRESHOLDS (3.3V)
30
TEMPERATURE (°C)
3.0
2.5
2.0
POSITIVE THRESHOLD
1.5
NEGATIVE THRESHOLD
1.0
0.5
0.0
-45
-20
5
30
55
80
105
TEMPERATURE (°C)
FIGURE 11. OPTION A THRESHOLDS
8
130
POSITIVE THRESHOLD
3.0
2.5
2.0
NEGATIVE THRESHOLD
1.5
1.0
0.5
0.0
-45
-20
5
30
55
80
105
130
TEMPERATURE (°C)
FIGURE 12. OPTION B THRESHOLDS
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Typical Performance Curves (Continued)
25
30
PROPAGATION DELAY (ns)
RISE/FALL TIME (ns)
FALL TIME, CLOAD = 10nF
20
RISE TIME, CLOAD = 10nF
15
-45
-20
5
30
55
80
105
130
OUTPUT FALLING PROP DELAY
25
OUTPUT RISING PROP DELAY
20
15
5
7
9
TEMPERATURE (°C)
FIGURE 13. OUTPUT RISE/FALL TIME
Functional Description
Overview
The ISL89163, ISL89164, ISL89165 MOSFET drivers
incorporate several features optimized for Synchronous
Rectifier (SR) driver applications including precision input
logic thresholds, enable inputs, undervoltage lock-out,
and high output drive currents.
The precision input thresholds facilitate the use of an
external RC network to delay the rising or falling
propagation of the driver output. This is a useful feature
for adjusting when the SRs turn-on relative to the
primary side FETs. In a similar manner, these drivers can
also be used to control the turn-on/off timing of the
primary FETs.
The Enable inputs (ENA, ENB) are used to emulate diode
operation of the SRs by disabling the driver output when
it is necessary to prevent negative currents in the SRs.
An example is turning off the SRs when the power supply
output is turned off. This prevents the output capacitor
from being discharged through the output inductor. If
this is allowed to happen, the voltage across the output
capacitor will ring negative possibly damaging the
capacitor (if it is polarized) and probably damaging the
load. Another example is preventing circulating currents
between paralleled power supplies during no or light load
conditions. During light load conditions (expecially when
active load sharing is not active), energy will be
transfered from the paralled power supply that has a
higher voltage to the paralleled power supply with the
lower voltage. Consequently, the energy that is absorbed
by the low voltage output is then transfered to the
primary side causing the bus voltage to increase until the
primary side is damaged by excessive voltage.
To prevent unexpected glitches on the output of the
ISL89163, ISL89164, ISL89165 during power-on or
power-off when VDD is very low, the Undervoltage (UV)
lock-out prevents the outputs of the ISL89163,
9
11
VDD
13
15
FIGURE 14. PROPAGATION DELAY vs VDD
ISL89164, ISL89165 driver from turning on. The A and B
input threshold options force the driver outputs to be low
when VDD < ~3.2 VDC regardless of the input logic
states. The C option shuts down when VDD < ~ 6.5 VDC.
Application Information
Precision Thresholds for Time Delays
Three input logic voltage levels are supported by the
ISL89163, ISL89164, ISL89165. Option A is used for
3.3V logic, Option B is used for 5.0V logic, and Option C
is used for higher voltage logic when it is desired to have
voltage thresholds that are proportional to VDD. The A
and B options have nominal thresholds that are 37% and
63% of 3.3V and 5.0V respectively and the C option is
20% and 80% of VDD.
ENx
D
INx
Rdel
OUTx
cdel
FIGURE 15. DELAY USING RCD NETWORK
In Figure 15, Rdel and Cdel delay the rising edge of the
input signal. For the falling edge of the input signal, the
Diode shorts out the resistor resulting in a minimal falling
edge delay.
The 37% and 63% thresholds of options A and B were
chosen to simplify the calculations for the desired time
delays. When using an RC circuit to generate a time
delay, the delay is simply T (secs) = R (ohms) x C
(farads). Please note that this equation only applies if the
input logic voltage is matched to the 3.3V or 5V threshold
options. If the logic high amplitude is not equal to 3.3V or
5V, then the equations in Equation 1 can be used for
more precise delay calculations.
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
VH = 10V
High level of the logic signal into the RC
Vthres = 63% × 5V
Positive going threshold for 5V logic (B option)
VL = .3V
Low level of the logic signal into the RC
Rdel = 100Ω
C del = 1nF
Timing values
⎞
⎛ VL − Vthres
tdel = − Rdel C del × ln⎜
+ 1⎟
V H − VL
⎝
⎠
tdel = 34.788 ns
nominal delay time for this example
(EQ. 1)
In this example, the high logic voltage is 10V, the
positive threshold is 63% of 5V and the low level logic is
0.3V. Note the the rising edge propagation delay of the
driver must be added to this value.
The minimum recommended value of C is 100pF. The
parasitic capacitance of the PCB and any attached scope
probes will introduce significant delay errors if smaller
values are used. Larger values of C will further minimize
errors.
Acceptable values of R are primarily effected by the
source resistance of the logic inputs. Generally, 100Ω
resistors or larger are usable.
Power Dissipation of the Driver
The power dissipation of the ISL89163, ISL89164,
ISL89165 is dominated by the losses associated with the
gate charge of the driven bridge FETs and the switching
frequency. The internal bias current also contributes to
the total dissipation but is usually not significant as
compared to the gate charge losses.
Vgs GATE-SOURCE VOLTAGE (V)
12
10
VDS = 64V
8
VDS = 40V
6
4
2
0
0
2
4
6
8
10 12 14 16 18 20 22 24
Qg, GATE CHARGE (nC)
FIGURE 16. MOSFET GATE CHARGE vs GATE VOLTAGE
Figure 16 illustrates how the gate charge varies with
the gate voltage in a typical power MOSFET. In this
example, the total gate charge for Vgs = 10V is 21.5nC
when VDS = 40V. This is the charge that a driver must
source to turn-on the MOSFET and must sink to
turn-off the MOSFET.
Equation 2 shows calculating the power dissipation of
the driver:
R gate
P D = 2 • Q c • freq • V GS • --------------------------------------------- + I DD ( freq ) • V DD
R
+r
gate
DS ( ON )
(EQ. 2)
where:
freq = Switching frequency,
VGS = VDD bias of the ISL89163, ISL89164, ISL89165
Qc = Gate charge for VGS
IDD(freq) = Bias current at the switching frequency
(see Figure 7)
rDS(ON) = ON-resistance of the driver
Rgate = External gate resistance (if any).
Note that the gate power dissipation is proportionally
shared with the external gate resistor. Do not overlook
the power dissipated by the external gate resistor.
10
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Typical Application Circuits
PWM
L
R
L
/OUTLLN
Primary to Secondary
side self biasing,
Isolated SR drive
VBIAS
D9
/OUTLRN
OUTLLN
V1
V1
R27
V2
EL7212
LLN
OUTLRN
V3
LRN
Q100
C123
V2
ENABLE
U4
R28
V4
R-SR
ISL89163
Q101
LSR
U4
T6
V3
Red dashed lines point out
the turn-on delay of the
SRs when PWM goes low
V4
LRN
This drive circuit provides Primary to Secondary line
isolation. A controller, on the primary side, is the source
of the SR control signals OUTLLN and OUTLRN signals.
The secondary side signals, V1 and V2 are rectified by
the dual diode, D9, to generate the secondary side bias
for U4. V1 and V3 are also inverted by Q100 and Q101
and the rising edges are delayed by R27/C10 and
R28/C9 respectively to generate the SR drive signals,
LRN and LLN. For more complete information on this SR
drive circuit, and other applications for the
ISL89163/4/5, refer to AN1603 “ISL6752_54 Evaluation
Board Application Note”.
General PCB Layout Guidelines
The AC performance of the ISL89163, ISL89164,
ISL89165 depends significantly on the design of the PC
board. The following layout design guidelines are
recommended to achieve optimum performance:
• Place the driver as close as possible to the driven
power FET.
• Understand where the switching power currents flow.
The high amplitude di/dt currents of the driven
power FET will induce significant voltage transients
on the associated traces.
• Keep power loops as short as possible by paralleling
the source and return traces.
• Use planes where practical; they are usually more
effective than parallel traces.
• Avoid paralleling high amplitude di/dt traces with low
level signal lines. High di/dt will induce currents and
consequently, noise voltages in the low level signal lines.
• When practical, minimize impedances in low level
signal circuits. The noise, magnetically induced on a
10k resistor, is 10x larger than the noise on a 1k
resistor.
C9
C10
LLN
• Be aware of magnetic fields emanating from
transformers and inductors. Gaps in these structures
are especially bad for emitting flux.
• If you must have traces close to magnetic devices,
align the traces so that they are parallel to the flux
lines to minimize coupling.
• The use of low inductance components such as chip
resistors and chip capacitors is highly recommended.
• Use decoupling capacitors to reduce the influence of
parasitic inductance in the VDD and GND leads. To be
effective, these caps must also have the shortest possible
conduction paths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
• It may be necessary to add resistance to dampen
resonating parasitic circuits especially on OUTA and
OUTB. If an external gate resistor is unacceptable,
then the layout must be improved to minimize lead
inductance.
• Keep high dv/dt nodes away from low level circuits.
Guard banding can be used to shunt away dv/dt
injected currents from sensitive circuits. This is
especially true for control circuits that source the
input signals to the ISL89163, ISL89164, ISL89165.
• Avoid having a signal ground plane under a high
amplitude dv/dt circuit. This will inject di/dt currents
into the signal ground paths.
• Do power dissipation and voltage drop calculations of
the power traces. Many PCB/CAD programs have
built in tools for calculation of trace resistance.
• Large power components (Power FETs, Electrolytic
caps, power resistors, etc.) will have internal
parasitic inductance which cannot be eliminated.
This must be accounted for in the PCB layout and
circuit design.
• If you simulate your circuits, consider including
parasitic components especially parasitic inductance.
11
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
General EPAD Heatsinking
Considerations
The thermal pad is electrically connected to the GND
supply through the IC substrate. The epad of the
ISL89163, ISL89164, ISL89165 has two main functions:
to provide a quiet Gnd for the input threshold
comparators and to provide heat sinking for the IC. The
EPAD must be connected to a ground plane and no
switching currents from the driven FET should pass
through the ground plane under the IC.
Figure 17 is a PCB layout example of how to use vias to
remove heat from the IC through the EPAD.
For maximum heatsinking, it is recommended that a
ground plane, connected to the EPAD, be added to both
sides of the PCB. A via array, within the area of the EPAD,
will conduct heat from the EPAD to the gnd plane on the
bottom layer. The number of vias and the size of the gnd
planes required for adequate heatsinking is determined
by the power dissipated by the ISL89163, ISL89164,
ISL89165, the air flow and the maximum temperature of
the air around the IC.
12
EPAD GND
PLANE
COMPONENT
LAYER
EPAD GND
PLANE
BOTTOM
LAYER
FIGURE 17. TYPICAL PCB PATTERN FOR THERMAL VIAS
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
10/12/10
FN7707.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL89163, ISL89164, ISL89165
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/sear
13
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Package Outline Drawing
L8.3x3I
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1 6/09
2X 1.950
3.00
B
0.15
8
5
3.00
(4X)
6X 0.65
A
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
1
4
4
8X 0.30
8X 0.400 ± 0.10
TOP VIEW
0.10 M C A B
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
0.10 C
Max 0.80
C
0.08 C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
C
0 . 2 REF
5
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6.
14
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7707.0
October 12, 2010
ISL89163, ISL89164, ISL89165
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15D
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
TOP VIEW
L
SEATING PLANE
-A-
A
D
-C-
α
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
SIDE VIEW
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.059
0.067
1.52
1.72
-
A1
0.003
0.009
0.10
0.25
-
B
0.0138
0.0192
0.36
0.46
9
C
0.0075
0.0098
0.19
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.811
3.99
4
e
h x 45°
MIN
0.050 BSC
1.27 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.019
0.25
0.50
5
L
0.016
0.050
0.41
1.27
6
8°
0°
N
α
8
0°
8
7
8°
-
P
0.118
0.137
3.00
3.50
11
P1
0.078
0.099
2.00
2.50
11
Rev. 0 5/07
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
N
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
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15
FN7707.0
October 12, 2010