ISL99203 Features The ISL99203 is a fully integrated high efficiency class-D mono amplifier combined with a capfree headphone amplifier. It is designed to maximize performance for mobile phone applications while saving valuable board space. The application circuit requires a minimum requirement of external components and operates from a 2.4V to 5.5V input supply. • Operating Voltage 2.4V to 5.5V It is capable of delivering 1.5W of continuous output power with less than 10% THD+N driving a 8Ω load from a 5V supply. The speaker amplifier of the ISL99203 features a high-efficiency, low-noise modulation scheme. It operates with 85% efficiency at 400mW into 8Ω from 5V supply and has a signal-to-noise ratio (SNR) that is greater than 95dB. The architecture of the device allows it to achieve very low level pop and click. This minimizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. EMI suppression is achieved by SRC (Slew Rate Control). The amplifier passes FCC Radiated Emissions Standards with 24 inches of Cable and achieves greater than 20dB margin under FCC limits. The class-D amplifier is designed to operate without a low pass output filer thus saving cost and board space. The headphone amplifier is a GND-reference capfree amplifier. It can output up to 35mW into 32Ω at 3.3V. ISL99203 High Efficiency Audio Subsystem • Low Quiescent Current • Low Shutdown Current • Low RFI Susceptibility • Integrated Bypass Switch, I2C Controlled • I2C Control Interface • 40 Step Digital Volume Control • 3 Independent Volume Channels • 10 Distinct Output Modes • Speaker Amp Class-D • Protection for UV/TSD/OC • Independent Gain Boost for Headphone and Speaker • All Digital Interfaces 1.8V Compatible • Exposed Pad at Ground Voltage Applications*(see page 16) • Mobile Phones • PDAs • Portable Media Players • Portable Gaming Ordering Information PART NUMBER PART (Notes 1, 2, 3) MARKING ISL99203IIZ-T 203 TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # -40 to +85 20 Ball WLCSP W4x5.20 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free WLCSP and BGA packaged products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL99203. For more information on MSL please see tech brief TB363. December 17, 2009 FN7547.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL99203 Typical Application 8Ω 2 FN7547.0 December 17, 2009 ISL99203 Block Diagram 3 FN7547.0 December 17, 2009 ISL99203 Pin Configurations ISL99203 (20 BALL WLCSP) BOTTOM VIEW SCL SDA GND_CPK RIN ISL99203 (20 BALL WLCSP) TOP VIEW R_OUT R_OUT 4 MO+ SWI+ GND_CP VDD_CP GND_P VDD_P MI- VSS CN MO- SWI- MI+ LIN E D C B SCL VDD_CP GND_CP SWI+ MO+ GND_P CP VSS MI- VDD_P L_OUT LIN MI+ SWI- A B C D 2 L_OUT 1 SDA 3 CP 2 GND_CPK 4 CN 3 RIN MO- 1 A E Pin Descriptions 20 BUMP CSP PIN NAME C4 GND_CPK PIN DESCRIPTION Charge-Pump Ground A1 L_OUT B2 VSS A2 CP Charge-Pump Cap + A3 CN Charge-Pump Cap - A4 R_OUT B4 RIN B3 VDD_CP Charge-Pump Power Supply C3 GND_CP Charge-Pump Ground D4 SDA D3 SWI+ E4 SCL I2C Clock E3 MO+ Mono O/P Positive D2 VDD_P Power Supply E2 GND_P Power Ground E1 MO- Mono O/P Negative D1 SWI- Switch Input - C1 MI+ Mono Positive Input C2 MI- Mono Negative Input B1 LIN Left input Channel 4 Left Headphone Out Negative-Power Supply Right Headphone Out Right Input Channel I2C Data Switch Input + FN7547.0 December 17, 2009 ISL99203 Absolute Maximum Ratings (Reference to GND) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V LIN, RIN, MI+, MI -, SWI +, SWI - . . . . . -0.3V to VDD+0.3V ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 250V Charged Device Model . . . . . . . . . . . . . . . . . . . . . 1500V Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . -40°C to +85°C Operating Supply Voltage (VDD Pin). . . . . . . . . . 2.4V to 5.5V Thermal Information Thermal Resistance (Typical, Note 4) θJA (°C/W) WLCSP Package . . . . . . . . . . . . . . . . . . . . . 71 Maximum Junction Temperature (Plastic Package). . . . . . . . . . . . . . . . . . . -65°C to +150°C Maximum Storage Temperature Range . . . -65°C to +150°C Dissipation Ratings Derating Factor 20 Balls 4x5 Array WLCSP . . . . . . . . . . . . . . .10.1mW/°C Power Rating TA 20 Balls 4x5 Array WLCSP +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.76W +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12W +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.91W Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER VDD = 3.6V. Typical Values Are Tested at VDD = 3.6V and the Ambient Temperature at +25°C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. SYMBOL Output Power POUT Total Harmonic Distortion THD+N Output Offset Voltage VOS Quiescent Current Iqq Shutdown Current ISD Digital Volume Control Range TEST CONDITIONS MIN TYP MAX UNITS Mono, RL = 8Ω, THD = 1%, f = 1kHz, BTL, mode 1 740 mW Mono, RL = 8Ω, THD = 10%, f = 1kHz, BTL, mode 1 925 mW Headphone out RL = 32Ω, THD = 1%, f = 1kHz, mode 4 47 mW Headphone out RL = 32Ω, THD = 10%, f = 1kHz, mode 4 62 mW Mono, RL = 8Ω, f = 1kHz, BTL, POUT = 500mW, mode 1 0.05 % Headphone out, RL = 32Ω, f = 1kHz, POUT = 50mW, mode 4 0.01 % 2 mV VIN = 0V, mode 4 Headphones 0.2 mV O/P modes 2, 4, 6, VIN = 0V, no load 4.5 6 mA O/P modes 1, 3, 5, 7, VIN = 0V, no load 6.5 8 mA 0.01 0.5 μA A-weighted, grounded inputs and output referred VIN = 0V, mode 1, Mono Output mode 0 Max Gain HP Mute Attenuation Input Impedance (Mono and HP) Average Switching Frequency fSW Power Supply Rejection Ratio Output mode 1. VDD = 3.6V PSRR-Mono VRIPPLE = 200mV, f = 217Hz, RL = 8Ω, all inputs at GND, O/P mode 1 PSRR-HP Common Mode rejection Ratio 5 CMRR 250 18 dB 96 dB 12.5 kΩ 325 400 kHZ 75 dB VRIPPLE = 200mV, f = 217Hz, RL = 32Ω, all inputs at GND, O/P mode 4 85 dB f = 217Hz, Vcm = 1VP-P, 0dB, mode 1, RL = 8Ω 61 dB f = 217Hz, Vcm = 1VP-P, 0dB, mode 2, RL = 32Ω 66 dB FN7547.0 December 17, 2009 ISL99203 Electrical Specifications PARAMETER VDD = 3.6V. Typical Values Are Tested at VDD = 3.6V and the Ambient Temperature at +25°C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PROTECTION Thermal Shutdown 145 °C 30 °C Mono 1.3 A HP 200 mA Thermal Shutdown Hysteresis Overcurrent Shutdown Undervoltage Shutdown 2.4 Wake-up Time from Shutdown tWU V 3.5 ms Mono, mode 1 33 μV HP, mode 4, 7 12 μV NOISE PERFORMANCE Output Voltage Noise en Electrical Specifications PARAMETER VDD = 5V. Typical Values Are Tested at VDD = 5V and the Ambient Temperature at +25°C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. SYMBOL Output Power POUT TEST CONDITIONS Mono, RL = 8Ω, THD = 1%, f = 1kHz, BTL, mode 1 THD+N Output Offset Voltage VOS Iqq Shutdown Current ISD Digital Volume Control Range 1.375 W Headphone out RL=32Ω, THD = 1%, f = 1kHz, SE, mode 4 47 mW Headphone out RL=32Ω, THD = 10%, f = 1kHz, SE, mode 4 62 mW Mono, RL = 8Ω, f = 1kHz, BTL, POUT = 500mW, mode 1 0.05 % Headphone out, RL = 32Ω, f = 1kHz, POUT = 50mW, mode 4 0.01 % 2 mV 0.2 mV O/P modes 4 5 mA O/P modes 1 5.5 mA 0.01 μA 18 dB 96 dB 12.5 kΩ VRipple = 200mV, f = 217Hz, RL = 8Ω, all inputs at GND, O/P mode 1 75 dB VRipple = 200mV, f = 217Hz, RL = 32Ω, all inputs at GND, O/P mode 4, 7 85 dB f = 217Hz, Vcm = 1VP-P, 0dB, mode 1, RL = 8Ω 61 dB f = 217Hz, Vcm = 1VP-P, 0dB, mode 2, RL = 32Ω 66 dB A-weighted, grounded inputs and output referred VIN = 0V, mode 1, Mono Output mode 0 Max Gain HP Mute Attenuation Input Impedance (Mono and HP) Power Supply Rejection Ratio PSRRMono PSRR-HP Common Mode rejection Ratio 6 CMRR MAX UNITS W VIN = 0V, mode 4 Headphones Quiescent Current TYP 1 Mono, RL = 8Ω, THD = 10%, f = 1kHz, BTL, mode 1 Total Harmonic Distortion MIN FN7547.0 December 17, 2009 ISL99203 Electrical Specifications PARAMETER VDD = 5V. Typical Values Are Tested at VDD = 5V and the Ambient Temperature at +25°C. All Maximum and Minimum Values Are Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature, Unless Otherwise Noted. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PROTECTION Thermal Shutdown 145 °C 30 °C Mono 1.3 A HP 200 mA Thermal Shutdown Hysteresis Overcurrent Shutdown Undervoltage Shutdown 2.4 Wake-up time from Shutdown tWU V 3.5 ms Mono, mode 1 33 μV HP, mode 4, 7 12 μV NOISE PERFORMANCE Output Voltage Noise en SDA vs SCL Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) TABLE 1. CHIP ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 Chip Address 1 1 1 1 1 0 Pin Controlled 0 ID_ENB = 0 1 1 1 1 1 0 0 0 ID_ENB = 1 1 1 1 1 1 0 1 0 TABLE 2. CONTROL REGISTERS D7 D6 D5 D4 D3 D2 D1 D0 Mode Control 0 0 0/1 0 X/MC3 MC2 MC1 MC0 Boost Control 0 1 1 X Amp BYP GBM GBHPL GBHPR Mono Volume Control 1 0 0 MVC4 MVC3 MVC2 MVC1 MVC0 Extended Volume Control 1 0 1 0 0 RVC5 LVC5 MVC5 Left Volume Control 1 1 0 LVC4 LVC3 LVC2 LVC1 LVC0 Right Volume Control 1 1 1 RVC4 RVC3 RVC2 RVC1 RVC0 NOTE: GBM: Gain Boost on Mono Speaker; 0 = no boost, 1 = 3dB GBHP: Gain Boost on Headphone; 0 = no boost, 1 = 3dB Amp Bypass: 0 is no bypass (Switch OFF); 1 is bypass (Switch ON) 7 FN7547.0 December 17, 2009 ISL99203 TABLE 3. OUTPUT MODES OUTPUT MODE MC3 MC2 MC1 MC0 SPEAKER OUTPUT RIGHT HP OUTPUT LEFT HP OUTPUT 0 0 0 0 0 SD SD SD 1 0 0 0 1 GM x M SD SD 2 0 0 1 0 SD GM x M/2 GM x M/2 3 0 0 1 1 2 x (GL x L + GR x R) SD SD 4 0 1 0 0 SD GR x R GL x L 5 0 1 0 1 2 x (GL x L + GR x R) + GM x M SD SD 6 0 1 1 0 SD GM x M/2 + GR x R GM x M/2 + GL x L 7 0 1 1 1 2 x (GL x L + GR x R) GR x R GL x L 10 1 0 1 0 2 x (GL x L + GR x R) GM x M/2 GM x M/2 14 1 1 1 0 2 x (GL x L + GR x R) GM x M/2 + GR x R GM x M/2 + GL x L NOTE: Power On Default Mode 0 0 0 0 M = Mono, Phone in R = RIN L = LIN SD = Shutdown GM = Mono Volume Control gain GR = Right HP Volume Control Gain GL = Left HP Volume Control gain TABLE 4. VOLUME CONTROL VOLUME STEP VC5 VC4 VC3 VC2 VC1 VC0 GAIN (dB) 0 0 0 0 0 0 0 -82 1 0 0 0 0 0 1 -76 2 0 0 0 0 1 0 -70 3 0 0 0 0 1 1 -64.5 4 0 0 0 1 0 0 -58.5 5 0 0 0 1 0 1 -52 6 0 0 0 1 1 0 -46.5 7 0 0 0 1 1 1 -40.5 8 0 0 1 0 0 0 -34.5 9 0 0 1 0 0 1 -30 10 0 0 1 0 1 0 -26.5 11 0 0 1 0 1 1 -24 12 0 0 1 1 0 0 -21 13 0 0 1 1 0 1 -18 14 0 0 1 1 1 0 -15 15 0 0 0 1 1 1 -13.5 16 0 1 0 0 0 0 -11.5 17 0 1 0 0 0 1 -10 18 0 1 0 0 1 0 -8.5 19 0 1 0 0 1 1 -7 20 0 1 0 1 0 0 -6 8 FN7547.0 December 17, 2009 ISL99203 TABLE 4. VOLUME CONTROL (Continued) VOLUME STEP VC5 VC4 VC3 VC2 VC1 VC0 GAIN (dB) 21 0 1 0 1 0 1 -4.5 22 0 1 0 1 1 0 -3 23 0 1 0 1 1 1 -1.5 24 0 1 1 0 0 0 0 25 0 1 1 0 0 1 1.5 26 0 1 1 0 1 0 3 27 0 1 1 0 1 1 4.5 28 0 1 1 1 0 0 6 29 0 1 1 1 0 1 7.5 30 0 1 1 1 1 0 9 31 0 0 1 1 1 1 10.5 32 1 0 0 0 0 0 12 33 1 0 0 0 0 1 12.75 34 1 0 0 0 1 0 13.5 35 1 0 0 0 1 1 14.25 36 1 0 0 1 0 0 15 37 1 0 0 1 0 1 15.75 38 1 0 0 1 1 0 16.5 39 1 0 0 1 1 1 17.25 40 1 0 1 0 0 0 18 9 FN7547.0 December 17, 2009 ISL99203 Typical Performance Characteristics 100.000 VDD = 5V LOAD = 8Ω + 68μH 6kHz 1.000 1kHz 0.100 20Hz 1.000 VDD= 5V VDD= 4.2V VDD= 3.6V 0.0100 0.001 0.00 0.20 0.40 0.60 0.80 1.00 1.20 0.001 0 1.40 1.60 OUTPUT POWER (W) FIGURE 1. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (MONO) 6kHz 1.000 1kHz 0.100 20Hz 0.010 0.001 0.00 0.01 0.02 0.03 0.04 0.05 1.0 1.5 VDD = 5V LOAD = 16Ω 1.000 20Hz 6kHz 0.100 1kHz 0.010 0.001 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.06 0.07 0.08 OUTPUT POWER (W) OUTPUT POWER (W) FIGURE 4. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE) 10.000 10.000 VDD = 3.7V LOAD = 16Ω 6kHz 1.000 THD + N (%) THD + N (%) FIGURE 3. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE) VDD = 3.7V LOAD = 32Ω 20Hz 0.100 0.010 1kHz 0.001 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 OUTPUT POWER (W) FIGURE 5. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE) 10 2.0 FIGURE 2. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (MONO) 10.000 VDD = 5V LOAD = 32Ω 0.5 OUTPUT POWER (W) THD + N (%) THD +N (%) VDD= 3V 0.100 0.010 10.000 LOAD= 8Ω + 68μH 10.000 THD + N (%) THD + N (%) 10.000 1.000 6kHz 20Hz 0.100 0.010 1kHz 0.001 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 OUTPUT POWER (W) FIGURE 6. TOTAL HARMORNIC DISTORTION PLUS NOISE vs POWER (HEADPHONE) FN7547.0 December 17, 2009 ISL99203 Typical Performance Characteristics (Continued) 10.00 THD+ N(%) VDD = 3V LOAD = 32Ω 1.00 10mW 0.10 0.01 10 100 20mW 1k FREQUENCY (Hz) 10k FIGURE 7. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE) 10mW 20mW 0.10 100 1k FREQUENCY (Hz) 10k THD +N (%) 10.00 1k FREQUENCY (Hz) 10k 100k VDD = 3.7V LOAD = 32Ω 1.00 30mW 0.10 0.01 10 100k FIGURE 9. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE) 100 40mW FIGURE 8. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE) 10.00 1.00 100.00 0.01 10 VDD = 3V LOAD = 16Ω 0.01 10 20mW 0.10 THD+ N(%) THD+ N(%) 10.00 VDD = 3.7V LOAD = 32Ω 1.00 100k 100 16mW 1k FREQUENCY (Hz) 10k 100k FIGURE 10. TOTAL HARMORNIC DISTORTION PLUS NOISE vs FREQUENCY (HEADPHONE) 100.00 STEREO SINGLE-ENDED INPUTS OUT OF PHASE RL = 32Ω, GAIN = 0dB 10.00 VDD = 2.5V 1.00 VDD = 3.6V 0.10 0.01 0.00 VDD = 5.0V 0.01 0.02 0.03 0.04 0.05 0.06 0.07 OUTPUT POWER (W) FIGURE 11. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 11 THD +N (%) THD+ N(%) 10.00 STEREO SINGLE-ENDED INPUTS IN PHASE RL = 32Ω, GAIN = 0dB VDD = 2.5V 1.00 VDD = 3.6V VDD = 5.0V 0.10 0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 OUTPUT POWER (W) FIGURE 12. TOTAL HARMONIC DISTORTION + NOISE (HP) vs POWER FN7547.0 December 17, 2009 ISL99203 Typical Performance Characteristics (Continued) 100 9 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 10 SPEAKER AND HEADPHONES MODE 8 7 SPEAKER MODE 6 5 4 HEADPHONES MODE 3 2.0 2.5 3.0 3.5 4.0 4.5 5.0 STEREO SINGLE-ENDED INPUTS OUT OF PHASE RL = 16Ω, GAIN = 0dB VDD = 2.5V 10 VDD = 5.0V VDD = 3.6V 1 0.1 5.5 1 10 Po TOTAL POWER (mW) VDD SUPPLY VOLTAGE (V) FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE 500 SUPPLY CURRENT (mA) STEREO SINGLE-ENDED INPUTS OUT OF PHASE RL = 32Ω, GAIN = 0dB VDD = 2.5V 10 VDD = 5.0V VDD = 3.6V 1 0.1 1 10 Po TOTAL POWER (mW) OUTPUT POWER (W) 2.5 MONO INPUT MODE RL = 8Ω + 33μH, GAIN = 6dB 1.5 1.0 THD + N = 10 % 0.5 THD + N = 1% 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE(V) FIGURE 17. OUTPUT POWER (SPEAKER) vs SUPPLY VOLTAGE 12 400 MONO INPUT MODE RL = 8Ω + 33μH, GAIN = 6dB 300 200 VDD = 2.5V VDD = 5.0V 100 VDD = 3.6V 0 0 100 FIGURE 15. SUPPLY CURRENT (HEADPHONES) vs TOTAL OUTPUT POWER 2.0 FIGURE 14. SUPPLY CURRENT (HEADPHONES) vs TOTAL OUTPUT POWER 0.2 0.4 0.6 0.8 1.0 1.2 1.4 PO TOTAL OUTPUT POWER (W) 1.6 FIGURE 16. TOTAL POWER DISSIPATION (SPEAKER MODE) vs TOTAL OUTPUT POWER OUTPUT POWER PER CHANNE (mW) SUPPLY CURRENT (mA) 100 100 100 90 STEREO SINGLE-ENDED INPUT HEADPHONE R = 16Ω, GAIN = 0dB OUT OF PHASE 80 L 70 60 THD + N = 10% 50 40 30 THD + N = 1% 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 FIGURE 18. OUTPUT POWER PER CHANNEL (HEADPHONE) vs SUPPLY VOLTAGE FN7547.0 December 17, 2009 ISL99203 100 90 80 0 THD + N = 10% 70 60 50 40 30 THD + N = 1% 20 0 2.0 -60 -80 -100 -120 -140 10 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 100 1k 10k FIGURE 20. SPEAKER TO HEADPHONE CROSSTALK vs FREQUENCY 0 -10 -30 -30 PSRR (dB) -20 -40 -50 -60 -70 SPEAKER MODE RL = 8Ω + 33μH -40 -50 -60 VDD = 2.6V -70 VDD = 3.6V -80 -80 -90 1k 10k VDD = 5.0V -90 SERIES1 100 100k FREQUENCY (Hz) 0 -10 SPEAKER MODE, Rl = 8Ω + 33μH VIN = 0.2VP-P, GAIN = 12dB -20 -100 10 SERIES1 -160 10 FIGURE 19. OUTPUT POWER PER CHANNEL (HEADPHONE) vs SUPPLY VOLTAGE CMRR (dB) SPEAKER MODE Rl = 8Ω + 33μH -20 Po = 250mW -40 HEADPHONE RL = 32Ω STEREO SINGLE-ENDED INPUT HEADPHONE RL = 32Ω, GAIN = 0dB OUT OF PHASE CROSSTALK (dB) OUTPUT POWER PER CHANNE (mW) Typical Performance Characteristics (Continued) 100k -100 10 FREQUENCY (Hz) FIGURE 21. COMMON-MODE REJECTION RATIO vs FREQUENCY 100 1k 10k 100k FREQUENCY (Hz) FIGURE 22. POWER SUPPLY REJECTION RATIO (SPEAKER) vs FREQUENCY PSRR (dB) 0 -10 STEREO SINGLE-ENDED -20 INPUT HP MODE RL = 32Ω -30 -40 -50 -60 -70 VDD = 2.5V -80 -90 -100 VDD = 5.0V -110 VDD = 3.6V -120 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 23. POWER SUPPLY REJECTION RATIO (HEADPHONES) vs FREQUENCY 13 FN7547.0 December 17, 2009 ISL99203 Typical Performance Characteristics (Continued) SDA SDA SPEAKER OUTPUT FIGURE 24. SPEAKER OUTPUT - START-UP SDA SPEAKER OUTPUT FIGURE 25. SPEAKER OUTPUT - SHUTDOWN SDA HEADPHONE OUTPUT FIGURE 26. HEADPHONE OUTPUT - START-UP 14 HEADPHONE OUTPUT FIGURE 27. HEADPHONE OUTPUT - SHUTDOWN FN7547.0 December 17, 2009 ISL99203 Theory of Operation The ISL99203 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL99203 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 28). On power-up of the ISL99203, the SDA pin is in the input mode. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 28). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 29). The ISL99203 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL99203 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL99203 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 29). A START condition is ignored during the power-up of the device. SCL SDA START DATA STABLE DATA DATA CHANGE STABLE STOP FIGURE 28. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 SDA OUTPUT FROM TRANSMITTER 9 HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 29. ACKNOWLEDGE RESPONSE FROM RECEIVER 15 FN7547.0 December 17, 2009 ISL99203 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 12/17/09 FN7547.0 CHANGE Initial release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL99203 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN7547.0 December 17, 2009 ISL99203 Package Outline Drawing W4x5.20 4x5 Array 20 Ball Wafer Level Chip Scale Package (WLCSP) Rev 1 8/09 2.545 ± 0.02 X 2.00 20X 0.32 ± 0.03 Y 4 0.25 3 1.50 2.045 ± 0.02 2 1 0.50 0.10 PIN 1 (A1 CORNER) TOP VIEW E D C B A (4X) 0.50 BOTTOM VIEW PACKAGE OUTLINE 0.33 3 0.025 BSC 0.30 ± 0.015 0.23 ± 0.015 0.32 ± 0.03 SEATING PLANE 0.05 Z 0.10 M Z X Y 0.05 M Z 0.28 Z SIDE VIEW 0.50 4 NSMD TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994, and JESD 95-1 SPP-10. 17 3. Back side coat 0.25mm thick applied to CSP package top. 4. NSMD refers to non-solder mask defined pad design per Intersil tech brief www.intersil.com/data/tb/TB451.pdf FN7547.0 December 17, 2009