K4M51163LC - R(B)N/G/L/F Mobile SDRAM 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES GENERAL DESCRIPTION • VDD/VDDQ = 2.5V/2.5V The K4M51163LC is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25°C ~ 70°C). • Extended Temperature Operation (-25°C ~ 85°C). • 1 /CS Support. • 54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free). ORDERING INFORMATION Part No. Max Freq. K4M51163LC-R(B)N/G/L/F75 133MHz(CL3), 111MHz(CL2) K4M51163LC-R(B)N/G/L/F1H 111MHz(CL2) K4M51163LC-R(B)N/G/L/F1L 111MHz(CL=3)*1, 83MHz(CL2) Interface Package LVCMOS 54 FBGA Pb (Pb Free) - R(B)N/G : Low Power, Extended Temperature(-25°C ~ 85°C) - R(B)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. Address configuration Organization Bank Row Column Address 32M x16 BA0,BA1 A0 - A12 A0 - A9 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. 1 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 8M x 16 8M x 16 Output Buffer Sense AMP Row Decoder Row Buffer Refresh Counter ADD Address Register CLK 8M x 16 DQi 8M x 16 Col. Buffer LCBR LRAS Column Decoder Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE 2 L(U)DQM March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > E1 9 8 7 6 5 4 3 2 54Ball(6x9) FBGA 1 1 2 3 7 8 9 B A VSS DQ15 VSSQ VDDQ DQ0 VDD C B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 D C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 E D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 D D1 e A F G H J E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS RAS WE G A12 A11 A9 BA0 BA1 CS H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD E *2: Top View A A1 z b *1: Bottom View < Top View*2 > Pin Name Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A12 Address BA0 ~ BA1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQM Data Input/Output Mask DQ0 ~ 15 Data Input/Output VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground #A1 Ball Origin Indicator [Unit:mm] SEC Week XXXX K4M51163LC 3 Symbol Min Typ Max A - - 1.00 A1 0.25 - - E 11.4 11.5 11.6 E1 - 6.40 - D 9.9 10.0 10.1 D1 - 6.40 - e - 0.80 - b 0.45 0.50 0.55 z - - 0.10 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 3.6 V TSTG -55 ~ +150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Storage temperature NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial) Parameter Symbol Min Typ Max Unit Note VDD 2.3 2.5 2.7 V 1 VDDQ 2.3 2.5 2.7 V 1 Input logic high voltage VIH 0.8 x VDDQ - VDDQ + 0.3 V 2 Input logic low voltage VIL -0.3 0 0.3 V 3 Output logic high voltage VOH VDDQ -0.2 - - V IOH = -0.1mA Output logic low voltage VOL - - 0.2 V IOL = 0.1mA ILI -10 - 10 uA 4 Supply voltage Input leakage current NOTES : 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VIH (max) = 3.0V AC.The overshoot voltage duration is ≤ 3ns. 3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns. 4. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE (VDD = 2.5V, Pin TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV) Symbol Min Max Unit CCLK 1.5 3.0 pF CIN 1.5 3.0 pF Address CADD 1.5 3.0 pF DQ0 ~ DQ15 COUT 3.0 5.0 pF Clock RAS, CAS, WE, CS, CKE, DQM 4 Note March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial) Version Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol ICC1 ICC2P Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current Burst length = 1 tRC ≥ tRC(min) IO = 0 mA -75 -1H -1L 110 110 110 CKE ≤ VIL(max), tCC = 10ns ICC3NS CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 1 15 mA 5 CKE ≤ VIL(max), tCC = 10ns 8 mA 8 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 20 mA ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 115 95 95 mA 1 ICC5 tRC ≥ tRC(min) 180 180 180 mA 2 -N/L Self Refresh Current mA mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N Note 1.0 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ ICC2NS Input signals are stable ICC3P Unit 1.0 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N Precharge Standby Current in non power-down mode Test Condition ICC6 CKE ≤ 0.2V 800 uA Internal TCSR 45 *4 85/70 Full Array 500 800 1/2 of Full Array 450 700 1/4 of Full Array 425 625 °C 3 -G/F uA NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Internal TCSR can be supported. In commercial Temp : 45°C/70°C, In extended Temp : 45°C/85°C 4. It has +/-5 °C tolerance. 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ). 5 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM AC OPERATING TEST CONDITIONS(VDD = 2.5V ± 0.2V, TA = -25 to 85°C for Extended, Parameter AC input levels (Vih/Vil) -25 to 70°C for Commercial) Value Unit 0.9 x VDDQ / 0.2 V 0.5 x VDDQ V tr/tf = 1/1 ns 0.5 x VDDQ V Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Figure 2 VDDQ 500Ω Vtt=0.5 x VDDQ VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA Output VOL (DC) = 0.2V, IOL = 0.1mA 500Ω 50Ω 30pF Output Z0=50Ω 30pF Figure 1. DC Output Load Circuit Figure 2. AC Output Load Circuit 6 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Version Parameter Symbol -75 -1H -1L Unit Note Row active to row active delay tRRD(min) 15 18 18 ns 1 RAS to CAS delay tRCD(min) 18 18 24 ns 1 Row precharge time tRP(min) 18 18 24 ns 1 tRAS(min) 45 50 60 ns 1 Row active time tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to Active delay 100 63 68 us ns 1,6 2 CLK 2 tDAL(min) tRDL + tRP - 3 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 4 ea 5 Number of valid output data CAS latency=3 2 Number of valid output data CAS latency=2 1 Number of valid output data CAS latency=1 0 84 NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP). 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. 6. Maximum burst refresh cycle : 8 7 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM AC CHARACTERISTICS(AC operating conditions unless otherwise noted) -75 Parameter -1H -1L Symbol Min Max Min Max 9.0 Min Unit Note ns 1 ns 1,2 ns 2 Max CLK cycle time CAS latency=3 tCC 7.5 CLK cycle time CAS latency=2 tCC 9.0 CLK cycle time CAS latency=1 tCC - CLK to valid output delay CAS latency=3 tSAC 5.4 7 7 CLK to valid output delay CAS latency=2 tSAC 7 7 8 CLK to valid output delay CAS latency=1 tSAC - - 20 Output data hold time CAS latency=3 tOH 2.5 2.5 2.5 Output data hold time CAS latency=2 tOH 2.5 2.5 2.5 Output data hold time CAS latency=1 tOH - - 2.5 CLK high pulse width tCH 2.5 3.0 3.0 ns 3 CLK low pulse width tCL 2.5 3.0 3.0 ns 3 Input setup time tSS 2.0 2.5 2.5 ns 3 Input hold time tSH 1.0 1.0 1.0 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 1000 CAS latency=2 1000 - CAS latency=3 CLK to output in Hi-Z 9.0 9.0 tSHZ CAS latency=1 12 1000 25 5.4 7 7 7 7 8 - - 20 ns NOTES : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 8 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM SIMPLIFIED TRUTH TABLE COMMAND Register CKEn-1 CKEn Mode Register Set H Auto Refresh X Entry Self Refresh RAS CAS WE L L L L X OP CODE L L L H X X Exit 3 L L 3 L H H H H X X X H 3 X X 3 Bank Active & Row Addr. H X L L H H X V Read & Auto Precharge Disable Column Address Auto Precharge Enable H X L H L H X V Write & Auto Precharge Disable Column Address Auto Precharge Enable H X L H L L X V Burst Stop H X L H H L X H X L L H L X Exit Entry Column Address (A0~A8) H L All Banks Entry Row Address L Bank Selection Precharge Clock Suspend or Active Power Down 1, 2 H H Refresh DQM BA0,1 A10/AP A12, A11 Note A9 ~ A0 CS H L H H X X X L V V V L H H X V L X H 4, 5 4 4, 5 6 X X X X X X H X X X L H H H H X X X L V V V L Precharge Power Down Mode Column Address (A0~A8) 4 X X X X Exit L DQM H No Operation Command H H X X H X X X L H H H X V X X X 7 (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) NOTES : 1. OP Code : Operand Code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. Partial self refresh can be issued only after setting partial self refresh mode of EMRS. 4. BA0 ~ BA1 : Bank select addresses. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). 9 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM A. MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS Address Function BA0 ~ BA1 A12 ~ A10/AP A9*2 "0" Setting for Normal MRS RFU*1 W.B.L A8 A7 A6 Test Mode A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved A9 Length Mode Select BA1 BA0 0 0 Burst 1 1 0 Reserved 1 Single Bit 1 1 1 Reserved Mode Setting for Normal MRS 0 Full Page Length x16 : 256Mb(512) Register Programmed with Extended MRS Address BA1 Function BA0 A12 ~ A10/AP Mode Select A9 A8 A7 A6 A5 A4 DS RFU*1 A3 A2 A1 A0 PASR RFU*1 EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength) Mode Select Driver Strength PASR BA1 BA0 Mode A6 A5 Driver Strength A2 A1 A0 Size of Refreshed Array 0 0 Normal MRS 0 0 Full 0 0 0 Full Array 0 1 Reserved 0 1 1/2 0 0 1 1/2 of Full Array 1 0 EMRS for Mobile SDRAM 1 0 Reserved 0 1 0 1/4 of Full Array 1 1 Reserved 1 1 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Reserved Address A12~A10/AP A9 A8 A7 A4 A3 0 0 0 0 0 0 NOTES: 1.RFU(Reserved for future use) should stay "0" during MRS cycle. 2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 10 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM Partial Array Self Refresh 1. In order to save power consumption, Mobile SDRAM has PASR option. 2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array. BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 - Full Array - 1/4 Array - 1/2 Array Partial Self Refresh Area Internal Temperature Compensated Self Refresh (TCSR) 1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range ; 45 °C and 85 °C(for Extended), 70 °C(for Commercial). 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. 3. It has +/-5 °C tolerance. Self Refresh Current (Icc6) Temperature Range -G/F Unit -N/L 85/70 °C Full Array 1/2 of Full Array 1/4 of Full Array 800 700 625 500 450 425 800 45 °C *3 uA B. POWER UP SEQUENCE 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS. For operating with DS or PASR , set DS or PASR mode in EMRS setting stage. In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set. 11 March 2006 K4M51163LC - R(B)N/G/L/F Mobile SDRAM C. BURST SEQUENCE 1. BURST LENGTH = 4 Initial Address Sequential Interleave A1 A0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. BURST LENGTH = 8 Initial Address Sequential Interleave A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 12 March 2006