SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM 128Mb F-die SDRAM Specification Revision 1.2 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.2 May 2004 SDRAM 128Mb F-die (x4, x8, x16) CMOS SDRAM Revision History Revision 0.0 (Agust, 2003) - First release. Revision 0.1 (November, 2003) - completed DC characteristics. Revision 0.2 (November, 2003) - Preliminary spec release. Revision 1.0 (January, 2004) - Revision 1.0 spec release. - Modified ICC4 current from 110mA -> 140mA at x16 - Modified tSH from 0.8ns -> 1.0ns at 166MHz. Revision 1.1 (February, 2004) - Corrected typo. Revision 1.2 (May, 2004) • Added Note 5. sentense of tRDL parameter Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) 8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh • 64ms refresh period (4K Cycle) GENERAL DESCRIPTION The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Ordering Information Part No. Orgainization Max Freq. K4S280432F-TC(L)75 32M x 4 133MHz (CL=3) K4S280832F-TC(L)75 16M x 8 133MHz (CL=3) K4S281632F-TC(L)60/75 8M x 16 166MHz (CL=3) Interface Package LVTTL 54pin TSOP(II) Organization Row Address Column Address 32Mx4 A0~A11 A0-A9, A11 16Mx8 A0~A11 A0-A9 8Mx16 A0~A11 A0-A8 Row & Column address configuration Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) Package Physical Dimension 0~8°C #1 #27 10.16 0.400 0.125+0.075 -0.035 0.005+0.003 -0.001 22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.71 ) 0.028 +0.10 0.30 -0.05 0.012 +0.004 -0.002 ± 0.10 0.21 0.008 ± 0.004 ± 0.05 ± 0.002 1.00 0.039 0.80 0.0315 ± 0.10 ± 0.004 ( 0.50 ) 0.020 #28 11.76±0.20 0.463±0.008 #54 0.45~0.75 0.018~0.030 0.25 TYP 0.010 1.20 MAX 0.047 0.05 MIN 0.002 54Pin TSOP(II) Package Dimension Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Output Buffer 8M x 4 / 4M x 8 / 2M x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 8M x 4 / 4M x 8 / 2M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LDQM LWCBR Timing Register CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) PIN CONFIGURATION (Top view) x8 x16 x4 VDD VDD VDD DQ0 DQ0 N.C VDDQ VDDQ VDDQ DQ1 N.C N.C DQ2 DQ1 DQ0 VSSQ VSSQ VSSQ DQ3 N.C N.C DQ4 DQ2 N.C VDDQ VDDQ VDDQ DQ5 N.C N.C DQ6 DQ3 DQ1 VSSQ VSSQ VSSQ DQ7 N.C N.C VDD VDD VDD LDQM N.C N.C WE WE WE CAS CAS CAS RAS RAS RAS CS CS CS BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD x4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS x8 VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS 54Pin TSOP (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins. (x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No connection /reserved for future use This pin is recommended to be left No Connection on the device. Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Voltage on any pin relative to Vss Parameter VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Storage temperature Power dissipation PD 1 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Note Input logic high voltage VIH 2.0 3.0 VDD+0.3 V Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current 1 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Clock RAS, CAS, WE, CS, CKE, DQM Symbol Min Max Unit CCLK 2.5 3.5 pF CIN 2.5 3.8 pF Address CADD 2.5 3.8 pF (x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) COUT 4.0 6.0 pF Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P 75 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 90 CKE ≤ VIL(max), tCC = 10ns 2 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N ICC2NS ICC3P 20 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 CKE ≤ VIL(max), tCC = 10ns 5 ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N ICC3NS Note mA 1 mA mA 5 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 30 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 mA 110 mA 1 2 ICC4 IO = 0 mA Page burst Refresh current ICC5 tRC ≥ tRC(min) ICC6 Unit mA 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns Operating current (Burst mode) Self refresh current Version Test Condition CKE ≤ 0.2V 200 mA C 2 mA 3 L 800 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S2804(08)32F-TC 4. K4S2804(08)32F-TL 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ) Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 60 75 130 100 CKE ≤ VIL(max), tCC = 10ns 2 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N ICC2NS ICC3P 20 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 10 ICC3NS CKE ≤ VIL(max), tCC = 10ns 5 30 CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 25 IO = 0 mA Page burst Refresh current ICC5 tRC ≥ tRC(min) ICC6 CKE ≤ 0.2V mA 1 mA 5 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns ICC4 Note mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N Unit mA 2 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns Operating current (Burst mode) Self refresh current Version Test Condition 150 220 mA mA 140 mA 1 200 mA 2 C 2 mA 3 L 800 uA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S281632F-TC 4. K4S281632F-TL 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ) Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version 60 (x16 only) 75 Unit Note Row active to row active delay tRRD(min) 12 15 ns 1 RAS to CAS delay tRCD(min) 18 20 ns 1 tRP(min) 18 20 ns 1 tRAS(min) 42 45 ns 1 Row precharge time Row active time tRAS(max) 100 Row cycle time tRC(min) ns 1 Last data in to row precharge tRDL(min) 2 CLK 2,5 Last data in to Active delay tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 1 CLK 3 ea 4 Col. address to col. address delay Number of valid output data 60 us tCCD(min) CAS latency=3 CAS latency=2 65 2 - 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CLK cycle time Symbol CAS latency=3 tCC CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 Output data hold time CAS latency=2 60 (x16 only) Min 6 - tSAC CAS latency=3 tOH 75 Max Min 7.5 1000 10 Max 1000 5 5.4 - 6 2.5 3 - 3 Unit Note ns 1 ns 1,2 ns 2 CLK high pulse width tCH 2.5 2.5 ns 3 CLK low pulse width tCL 2.5 2.5 ns 3 Input setup time tSS 1.5 1.5 ns 3 Input hold time tSH 1 0.8 ns 3 CLK to output in Low-Z tSLZ 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ CAS latency=2 5 5.4 - 6 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Symbol Condition Min Output rise time trh Measure in linear region : 1.2V ~ 1.8V Output fall time tfh Output rise time Output fall time Typ Max Unit Notes 1.37 4.37 Volts/ns 3 Measure in linear region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3 trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6 Volts/ns 1,2 tfh Measure in linear region : 1.2V ~ 1.8V 2.0 2.9 5.0 Volts/ns 1,2 Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS. Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) IBIS SPECIFICATION 100MHz/133MHz Pull-up 0 IOH Characteristics (Pull-up) (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0 100MHz 133MHz Max I (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 0.5 1 1.5 2 2.5 3 3.5 0 -100 -200 mA Voltage 100MHz 133MHz Min I (mA) -300 -400 -500 -600 Voltage IOH Min (100MHz/133MHz) IOH Max (66 and 100MHz/133MHz) 100MHz/133MHz Pull-down IOL Characteristics (Pull-down) (V) 0.0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 100MHz 133MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHz 133MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 250 200 150 mA Voltage 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Voltage IOL Min (100MHz/133MHz) IOL Max (100MHz/133MHz) Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) Minimum VDD clamp current (Referenced to VDD) VDD Clamp @ CLK, CKE, CS, DQM & DQ I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 20 15 mA VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 10 5 0 0 1 2 3 Voltage I (mA) Minimum VSS clamp current VSS Clamp @ CLK, CKE, CS, DQM & DQ I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 -3 -2 -1 0 0 -10 -20 mA VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 -30 -40 -50 -60 Voltage I (mA) Rev. 1.2 May 2004 CMOS SDRAM SDRAM 128Mb F-die (x4, x8, x16) SIMPLIFIED TRUTH TABLE Command Register CKEn-1 Mode register set Auto refresh Refresh Entry Self refresh (V=Valid, X=Don′t care, H=Logic high, L=Logic low) H H CKEn CS RAS CAS WE DQM X L L L L X OP code L L L H X X X X H L L H H H H X X X X L L H H X V H X L H L H X V H X L H L L X V H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L Exit L H L H Bank active & row addr. H Read & column address Write & column address Exit Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable Burst stop Precharge Bank selection All banks Clock suspend or active power down BA0,1 Precharge power down mode DQM H No operation command H H X X X L H H H H X X X V V V L X X H X X X L H H H X A10/AP A0 ~ A9, A11, Note 1,2 3 3 3 3 Row address L Column address H L Column address H X V L X H 4 4,5 4 4,5 6 X X X X X X V X X X 7 Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 1.2 May 2004