PRELIMINARY K6R4008V1B-C/B-L, K6R4008V1B-I/B-P CMOS SRAM Document Title 512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with Design Target. Jan. 1st, 1997 Design Target Rev. 1.0 Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Jun. 1st, 1997 Preliminary Rev. 2.0 Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Add 30pF capacitive in test load. 2.3. Relax DC characteristics. Item Previous ICC 10ns 170mA 12ns 160mA 15ns 150mA ISB f=max. 40mA ISB1 f=0 10 / 1mA IDR VDR=3.0V 0.9mA Feb.11th.1998 Final Current 205mA 200mA 195mA 50mA 10 / 1.2mA 1.0mA Rev. 2.1 Change operating current at Industrial Temperature range. Previous spec. Changed spec. Items (10/12/15ns part) (10/12/15ns part) Icc 205/200/195mA 230/225/220mA Jun.27th 1998 Final Rev. 2.2 Add 44 pins plastic TSOP(II) forward Package. May. 4th 1999 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P 512K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES GENERAL DESCRIPTION • Fast Access Time 10,12,15ns(Max.) • Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS) : 10mA(Max.) 1.2mA(Max.)- L-Ver. Operating K6R4008V1B-10 : 205mA(Max.) K6R4008V1B-12 : 200mA(Max.) K6R4008V1B-15 : 195mA(Max.) • Single 3.3 ±0.3V Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • 2V Minimum Data Retention ; L-Ver. only • Center Power/Ground Pin Configuration • Standard Pin Configuration K6R4008V1B-J : 36-SOJ-400 K6R4008V1B-T: 36-TSOP2-400F K6R4008V1B-U: 44-TSOP2-400AF The K6R4008V1B is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. The K6R4008V1B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4008V1B is packaged in a 400 mil 36-pin plastic SOJ or TSOP(II) forward or 44-pin plastic TSOP(II) forward. FUNCTIONAL BLOCK DIAGRAM ORDERING INFORMATION Clk Gen. Pre-Charge Circuit K6R4008V1B-C10/C12/C15 Commercial Temp. K6R4008V1B-I10/I12/I15 Industrial Temp. A0 A2 A3 A4 A5 A6 Row Select A1 Memory Array 512 Rows 1024x8 Columns Data Cont. I/O Circuit Column Select A7 A8 I/O1~I/O8 PIN FUNCTION Pin Name CLK Gen. A0 - A18 A10 A12 A14 A16 A18 A9 A11 A13 A15 A17 WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O8 CS WE OE -2- Pin Function Address Inputs Data Inputs/Outputs VCC Power(+3.3V) VSS Ground N.C No Connection Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P PIN CONFIGURATION(Top View) N.C 1 44 N.C N.C 2 43 N.C 35 A18 A0 3 42 N.C 34 A17 A1 4 41 A18 33 A16 A2 5 40 A17 A3 6 39 A16 A4 7 38 A15 CS 8 37 OE 9 36 I/O8 A0 1 36 N.C A1 2 A2 3 A3 A4 4 5 32 A15 CS 6 31 OE I/O1 7 30 I/O8 I/O1 I/O2 8 29 I/O7 I/O2 10 Vcc 9 28 Vss Vcc 11 Vss 10 36-SOJ/ TSOP2 27 Vcc I/O3 11 26 I/O6 I/O4 12 25 I/O5 WE 13 A5 A6 A7 35 I/O7 44-TSOP2 34 Vss Vss 12 33 Vcc I/O3 13 32 I/O6 I/O4 14 31 I/O5 WE 15 30 A14 24 A14 A5 16 29 A13 14 23 A13 A6 17 28 A12 15 22 A12 A7 18 27 A11 A8 19 26 A10 A9 20 25 N.C N.C 21 24 N.C N.C 22 23 N.C 21 A11 16 A8 17 20 A10 A9 18 19 N.C PIN FUNCTION Pin Name A0 - A18 Pin Function Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O8 Data Inputs/Outputs VCC Power(+3.3V) VSS Ground N.C No Connection ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to V SS Voltage on VCC Supply Relative to VSS Symbol Rating Unit VIN, VOUT -0.5 to 4.6 V VCC -0.5 to 4.6 V Power Dissipation Storage Temperature Operating Temperature PD 1.0 W TSTG -65 to 150 °C Commercial TA 0 to 70 °C Industrial TA -40 to 85 °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -3- Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3*** V Input Low Voltage VIL -0.3** - 0.8 V * The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN=VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA - 205 mA Standby Current 10ns 12ns - 200 15ns - 195 - 50 mA Normal - 10 mA L-Ver. ISB Min. Cycle, CS=VIH ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤ 0.2V - 1.2 Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25°C, f=1.0MHz) Item Symbol Test Conditions MIN Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 7 pF * Capacitance is sampled and not 100% tested. -4- Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.) TEST CONDITIONS* Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below * The above test conditions are also applied at industrial temperature range. Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ Output Loads(A) +3.3V RL = 50Ω DOUT 319Ω VL = 1.5V DOUT 30pF* ZO = 50Ω 353Ω * Capacitive Load consists of all components of the test environment. 5pF* * Including Scope and Jig Capacitance READ CYCLE* Parameter Read Cycle Time Symbol tRC K6R4008V1B-10 K6R4008V1B-12 K6R4008V1B-15 Min Max Min Max Min Max 10 - 12 - 15 - Unit ns Address Access Time tAA - 10 - 12 - 15 ns Chip Select to Output tCO - 10 - 12 - 15 ns Output Enable to Valid Output tOE - 5 - 6 - 7 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 ns Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns Chip Selection to Power DownTime tPD - 15 - 12 - 15 ns * The above parameters are also guaranteed at industrial temperature range. -5- Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P WRITE CYCLE* Parameter K6R4008V1B-10 Symbol K6R4008V1B-12 K6R4008V1B-15 Min Max Min Max Min Max Unit Write Cycle Time tWC 10 - 12 - 15 - ns Chip Select to End of Write tCW 7 - 8 - 10 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 7 - 8 - 10 - ns Write Pulse Width(OE High) tWP 7 - 8 - 10 - ns Write Pulse Width(OE Low) tWP1 10 - 12 - 15 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 6 0 7 ns Data to Write Time Overlap tDW 5 - 6 - 7 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - ns * The above parameters are also guaranteed at industrial temperature range. TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tAA tOH Data Out Valid Data Previous Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOE tOHZ OE tOLZ tOH tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. -6- Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW (10) (9) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP(2) WE tDW Data in High-Z Valid Data tLZ Data out tDH High-Z tWHZ(6) High-Z(8) High-Z -7- Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * X means Don ′t Care. DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C) Parameter Symbol Test Condition Min. Typ. Max. Unit 2.0 - 3.6 V VCC for Data Retention VDR CS ≥ VCC - 0.2V Data Retention Current IDR VCC=3.0V, CS≥VCC - 0.2V VIN≥VCC - 0.2V or VIN≤ 0.2V - - 1.0 mA VCC = 2.0V, CS≥VCC - 0.2V VIN≥VCC - 0.2V or VIN≤0.2V - - 0.7 mA See Data Retention Wave form(below) 0 - - ns 5 - - ms Data Retention Set-Up Time tSDR Recovery Time tRDR * The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0V VIH VDR CS≥VCC - 0.2V CS GND -8- Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P Units:millimeters/Inches PACKAGE DIMENSIONS 36-SOJ-400 #19 10.16 0.400 #36 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 +0.10 -0.05 0.008 +0.004 -0.002 #18 0.69 MIN 0.027 23.90 MAX 0.941 23.50 ±0.12 0.925 ±0.005 1.19 ) 0.047 1.27 ( ) 0.050 ( 0.43 ( 0.95 ) 0.0375 3.76 MAX 0.148 0.10 MAX 0.004 +0.10 -0.05 0.017 +0.004 -0.002 1.27 0.050 0.71 +0.10 -0.05 0.028 +0.004 -0.002 36-TSOP2-400F 0~8° #19 0.45 ~0.75 0.018 ~ 0.030 11.76 ±0.20 0.463 ±0.008 #1 10.16 0.400 #36 (0.50) (0.020) #18 0.15 +0.10 -0.05 0.006 +0.004 -0.002 18.81 0.741 MAX 18.41 ±0.10 0.725 ±0.004 1.00 ±0.10 0.039 ±0.004 (0.705) (0.028) 0.40 ±0.10 0.016 ±0.004 1.00 0.039 TYP -9- 1.20 0.047 MAX 0.10 MAX 0.075 MAX 0.05 0.002MIN Rev 2.2 May 1999 PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P 44-TSOP2-400AF 0~8° 0.25 ( ) 0.010 #23 0.45 ~0.75 0.018 ~ 0.030 11.76 ±0.20 0.463 ±0.008 10.16 0.400 #44 0 + 0.1 0.05 0.15 - .00 4 0 + 02 .006 - 0.0 #22 #1 18.81 MAX. 0.741 18.41 ±0.10 0.725 ±0.004 0 1.00 ±0.10 0.039 ±0.004 ( 0.805 ) 0.032 0.35 ±0.10 0.014 ±0.004 ( 0.50 ) 0.020 0.80 0.0315 1.20 MAX. 0.047 0.10 0.004 MAX 0.05 MIN. 0.002 - 10 Rev 2.2 May 1999