K6T2008V2A, K6T2008U2A Family CMOS SRAM Document Title 256Kx8 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Design target May 26, 1998 Advance 1.0 Finalize October 8, 1998 Final 2.0 Revised - Add FBGA type package July 21, 1999 Final 2.01 Errata correction - Removed T ’ TL Compatible’from Features October 24, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices. Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM 256Kx8 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: TFT • Organization: 256Kx8 • Power Supply Voltage K6T2008V2A Family: 3.0V~3.6V K6T2008U2A Family: 2.7V~3.3V • Low Data Retention Voltage: 2V(Min) • Three State Outputs • Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F 48-FBGA-6.00x7.00 The K6T2008V2A and K6T2008U2A families are fabricated by SAMSUNG′s advanced CMOS process technology. The family support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery backup operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family K6T2008V2A-B Operating Temperature Vcc Range Commercial(0~70°C) K6T2008U2A-B K6T2008V2A-F Speed 3.0~3.6V 70/85ns 2.7~3.3V 1) K6T2008U2A-F Operating (ICC2,Max) 10µA 70 /85/100ns 3.0~3.6V Industrial(-40~85°C) Standby (ISB1, Max) 30mA2) 15µA 701)/85/100ns PKG Type 32-TSOP1-0820F 32-TSOP1-0813.4F 48-FBGA-6.00x7.00 2.7~3.3V 1. The parameters are tested with 30pF test load 2. K6T2008V2A Family = 35mA PIN DESCRIPTION A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-TSOP1 32-sTSOP1 Type - Forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 FUNCTIONAL BLOCK DIAGRAM OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 1 2 3 4 5 6 A A0 A1 CS2 A3 A6 A8 B I/O5 A2 WE A4 A7 I/O1 C I/O6 NC A5 D Vss Vcc E Vcc Vss F I/O7 G I/O8 H A9 Clk gen. Precharge circuit. A16 A15 I/O2 A14 A13 A12 A11 Memory array 1024 rows 256×8 columns Row select A10 NC A17 OE CS1 A16 A15 I/O4 A10 A11 A12 A13 A14 A9 I/O3 A8 A7 I/O1 I/O8 48-FBGA: Top View (Ball Down) Name Function CS1,CS2 Chip Select Inputs Name Function I/O Circuit Column select Data cont I/O1~I/O8 Data Inputs/Outputs OE Output Enable Input Vcc Power WE Write Enable Input Vss Ground Address Inputs NC No Connection A0~A17 Data cont A0 A1 A17 A6 A5 A4 A3 A2 CS 1 CS 2 WE Control logic OE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name Industrial Temperature Products(-40~85°C) Function Part Name K6T2008V2A-TB70 K6T2008V2A-TB85 32-TSOP1-F, 70ns, 3.3V,LL 32-TSOP1-F, 85ns, 3.3V,LL K6T2008U2A-TB70 K6T2008U2A-TB85 K6T2008U2A-TB10 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL K6T2008V2A-YB70 K6T2008V2A-YB85 32-sTSOP1-F, 70ns, 3.3V,LL 32-sTSOP1-F, 85ns, 3.3V,LL K6T2008U2A-YB70 K6T2008U2A-YB85 K6T2008U2A-YB10 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL Function K6T2008V2A-TF70 K6T2008V2A-TF85 K6T2008V2A-TF10 32-TSOP1-F, 70ns, 3.3V, LL 32-TSOP1-F, 85ns, 3.3V, LL 32-TSOP1-F, 100ns, 3.3V, LL K6T2008U2A-TF70 K6T2008U2A-TF85 K6T2008U2A-TF10 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL K6T2008V2A-YF70 K6T2008V2A-YF85 K6T2008V2A-YF10 32-sTSOP1-F, 70ns, 3.3V, LL 32-sTSOP1-F, 85ns, 3.3V, LL 32-sTSOP1-F, 100ns, 3.3V, LL K6T2008U2A-YF70 K6T2008U2A-YF85 K6T2008U2A-YF10 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL K6T2008V2A-FF70 K6T2008V2A-FF85 48-FBGA, 70ns, 3.3V, LL 48-FBGA, 85ns, 3.3V, LL K6T2008U2A-FF70 K6T2008U2A-FF85 48-FBGA, 70ns, 3.0V, LL 48-FBGA, 85ns, 3.0V, LL FUNCTIONAL DESCRIPTION CS1 CS2 OE WE I/O Mode Power 1) X 1) X High-Z Deselected Standby X1) X1) High-Z Deselected Standby H H H High-Z Output Disabled Active H L H Dout Read Active H X1) L Din Write Active H X X1) L L L L 1) 1. X means don′t care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit Remark VIN,VOUT -0.5 to VCC+0.5 V - VCC -0.3 to 4.6 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C K6T2008V2A-B, K6T2008U2A-B -40 to 85 °C K6T2008V2A-F, K6T2008U2A-F TA 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit Supply voltage Vcc K6T2008V2A Family K6T2008U2A Family 3.0 2.7 3.3 3.0 3.6 3.3 V Ground Vss All Family 0 0 0 V Input high voltage VIH K6T2008V2A, K6T2008U2A Family 2.2 - Vcc+0.3 V Input low voltage VIL K6T2008V2A, K6T2008U2A Family -0.33) - 0.6 V Note: 1. Commercial Product: TA=0 to 70°C, otherwise specified Industrial Produc t: TA=-40 to 85°C, otherwise specified 2. Overshoot: Vcc+2.0V in case of pulse width≤30ns 3. Undershoot: -2.0V in case of pulse width≤30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Input leakage current Symbol Test Conditions Min Typ Max Unit µA ILI VIN=Vss to Vcc -1 - 1 Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS1=VIL, CS 2=VIH, VIN=VIH or VIL - - 5 mA ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2 ≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V - - 4 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN =VIH or VIL - 25 301) mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS1=VIH, CS 2=VIL, Other inputs = VIH or VIL - - 0.3 mA Standby Current(CMOS) ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc - 0.2 102) µA Average operating current 1. K6T2008V2A Family = 35mA 2. Industrial product = 15µA Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (K6T2008V2A Family: VCC=3.0~3.6V, K6T2008U2A Family: VCC=2.7~3.3V Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C) Speed Bins Parameter List Symbol Units 100ns Min Max Min Max Min Max 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO1, tCO2 - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns tOLZ 5 - 5 - 5 - ns Output enable to low-Z output Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns tOHZ 0 25 0 25 0 30 ns Output hold from address change tOH 10 - 15 - 15 - ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 55 - 60 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 30 0 30 ns Data to write time overlap tDW 30 - 35 - 40 - ns Output disable to high-Z output Write 85ns tRC Read cycle time Read 70ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS1≥Vcc-0.2V1) Data retention current IDR Vcc=3.0V, CS1≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR 1) See data retention waveform Min Typ Max Unit 2.0 - 3.6 V - 0.2 10 0 - - 5 - - 2) µA ms 1. CS1 ≥Vcc-0.2V, CS2 ≥Vcc-0.2V(CS1 controlled) or CS2 ≤0.2V(CS2 controlled) 2. Industrial Products = 15µA Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE OE Data out High-Z tOHZ tOLZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family TIMING WAVEFORM OF WRITE CYCLE(1) CMOS SRAM (WE Controlled) tWC Address tWR(4) tCW(2) CS 1 tAW CS 2 tCW(2) tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS 1 tAW CS 2 tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS1 tAW CS2 tCW(2) tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS 2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1 or WE going high. t WR2 is applied in case a write ends with CS2 going low. DATA RETENTION WAVE FORM CS1 controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7V 1) 2.2V VDR CS1≥VCC - 0.2V CS1 GND CS2 controlled Data Retention Mode VCC 3.0/2.7V1) CS 2 tSDR tRDR VDR 0.4V CS2≤0.2V GND 1. 3.0V for K6T2008V2A Family, 2.7V for K6T2008U2A Family Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeter(inch) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 +0.004 0.008-0.002 0.20 20.00±0.20 0.787±0.008 #1 #32 8.40 0.331MAX 0.50 0.0197 #17 #16 1.00±0.10 0.039±0.004 1.20 0.047MAX 18.40±0.10 0.724±0.004 0.25 0.010 TYP 0.25 ) 0.010 8.00 0.315 ( +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.10 MAX 0.004MAX 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) +0.10 -0.05 0.008+0.004 -0.002 0.20 13.40±0.20 0.528±0.008 #1 #32 8.40 0.331 MAX #17 #16 0.25 0.010 TYP 1.00±0.10 0.039±0.004 1.20 0.047 MAX 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 0.05 0.002 MIN ( 1.10 MAX 0.004 MAX 0.50 0.0197 0.25 ) 0.010 8.00 0.315 ( 0.50 ) 0.020 Revision 2.01 October 2001 K6T2008V2A, K6T2008U2A Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters 48 BALL FINE PITCH BALL GRID ARRAY(6.00X7.00) Top View Bottom View B A1 INDEX MARK 0.50 B1 B 6 5 4 3 2 0.50 1 A B #A1 C C C C1 D C1/2 E F G H B/2 Detail A Side View Y 0.85/Typ. E1 E 0.25/Typ. E2 0.30 A D C Min Typ Max A - 0.75 - B 5.90 6.00 6.10 1. Bump counts: 48(8 row x 6 column) B1 - 3.75 - 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) C 6.90 7.00 7.10 C1 - 5.25 - D 0.30 0.35 0.40 E - 1.10 1.20 E1 - 0.85 - E2 0.20 0.25 0.30 Y - - 0.08 Notes. 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max) Revision 2.01 October 2001