KM416C4000C, KM416C4100C CMOS DRAM 4M x 16bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -5 or -6) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. • Fast Page Mode operation FEATURES • 2CAS Byte/Word Read/Write operation • Part Identification • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability - KM416C4000C(5.0V, 8K Ref.) - KM416C4100C(5.0V, 4K Ref.) • Fast parallel test mode capability • TTL(5.0V) compatible inputs and outputs • Early Write or output enable controlled write • Active Power Dissipation Unit : mW • JEDEC Standard pinout Speed 8K 4K • Available in Plastic TSOP(II) package -5 495 660 • +5.0V±10% power supply -6 440 605 • Refresh Cycles Refresh cycle KM416C4000C* 8K KM416C4100C 4K Refresh time FUNCTIONAL BLOCK DIAGRAM Normal 64ms * Access mode & RAS only refresh mode : 8K cycle/64ms CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms RAS UCAS LCAS W Control Clocks Refresh Timer Refresh Counter Speed tRAC tCAC tRC tPC -5 50ns 13ns 90ns 35ns -6 60ns 15ns 110ns 40ns A0~A12 (A0~A11)*1 Row Address Buffer A0~A8 (A0~A9)*1 Col. Address Buffer Lower Data in Buffer Row Decoder Refresh Control • Performance Range Vcc Vss VBB Generator Memory Array 4,194,304 x 16 Cells Column Decoder Note) *1 : 4K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sense Amps & I/O Part NO. Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer DQ0 to DQ7 OE DQ8 to DQ15 KM416C4000C, KM416C4100C CMOS DRAM PIN CONFIGURATION (Top Views) • KM416C40(1)00CS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product Pin Name Pin function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+5.0V) N.C No Connection KM416C4000C, KM416C4100C CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Units VIN,VOUT -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 °C PD 1 W IOS Address 50 mA Voltage on any pin relative to VSS Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Symbol Min Typ Max Units Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 Input High Voltage VIH 2.6 - VIL -1.0 *2 - Input Low Voltage V *1 VCC+1.0 0.7 V V *1 : VCC+2.0V at pulse width≤20ns which is measured at VCC *2 : -2.0 at pulse width≤20ns which is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤VIN≤VCC+0.5V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V KM416C4000C, KM416C4100C CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Max Symbol Power Speed Units KM416C4000C KM416C4100C ICC1 Don′t care -5 -6 90 80 120 110 mA mA ICC2 Normal Don′t care 2 2 mA ICC3 Don′t care -5 -6 90 80 120 110 mA mA ICC4 Don′t care -5 -6 60 50 70 60 mA mA ICC5 Normal Don′t care 1 1 mA ICC6 Don′t care -5 -6 120 110 120 110 mA mA ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min) *Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC. KM416C4000C, KM416C4100C CMOS DRAM CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] CIN1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition : VCC=5.0V±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.4/0.6V Parameter -5 Symbol Min -6 Max Min Units Note Max Random read or write cycle time tRC 90 110 ns Read-modify-write cycle time tRWC 133 153 ns Access time from RAS tRAC 50 60 ns 3,4,10 Access time from CAS tCAC 13 15 ns 3,4,5 Access time from column address tAA 25 30 ns 3,10 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay tOFF 0 13 0 13 ns 6 Transition time (rise and fall) tT 1 50 1 50 ns 2 RAS precharge time tRP 30 RAS pulse width 0 40 10K 60 ns tRAS 50 RAS hold time tRSH 13 15 10K ns ns CAS hold time tCSH 50 60 ns CAS pulse width tCAS 13 10K 15 10K ns RAS to CAS delay time tRCD 20 37 20 45 ns 4 RAS to column address delay time tRAD 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns 13 Column address hold time tCAH 10 10 ns 13 Column address to RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold time referenced to CAS tRCH 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 ns 8 Write command hold time tWCH 10 10 ns Write command pulse width tWP 10 10 ns Write command to RAS lead time tRWL 15 15 ns Write command to CAS lead time tCWL 13 15 ns 16 Data set-up time tDS 0 0 ns 9,19 Data hold time tDH 10 10 ns 9,19 KM416C4000C, KM416C4100C CMOS DRAM AC CHARACTERISTICS (Continued) Parameter -5 Symbol Min -6 Max Min Units Note Max Refresh period (4K, Normal) tREF 64 64 ms Refresh period (8K, Normal) tREF 64 64 ms Write command set-up time tWCS 0 0 ns 7 CAS to W delay time tCWD 36 38 ns 7,15 RAS to W delay time tRWD 73 83 ns 7 Column address to W delay time tAWD 48 53 ns 7 CAS precharge W delay time tCPWD 53 60 ns CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 ns 17 CAS hold time (CAS -before-RAS refresh) tCHR 10 10 ns 18 RAS to CAS precharge time tRPC 5 5 ns Access time from CAS precharge tCPA Fast Page mode cycle time tPC 35 40 ns Fast Page mode read-modify-write cycle time tPRWC 76 85 ns CAS precharge time (Fast Page cycle) tCP 10 10 ns RAS pulse width (Fast Page cycle) tRASP 50 RAS hold time from CAS precharge tRHCP 30 OE access time tOEA OE to data delay tOED 13 Output buffer turn off delay time from OE tOEZ 0 OE command hold time tOEH 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 ns 11 Write command hold time (Test mode in) tWTH 15 15 ns 11 W to RAS precharge time (C-B-R refresh) tWRP 10 10 ns W to RAS hold time (C-B-R refresh) tWRH 10 10 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 us 20,21,22 RAS precharge time (C-B-R self refresh) tRPS 90 110 ns 20,21,22 CAS hold time (C-B-R self refresh) tCHS -50 -50 ns 20,21,22 30 200K 35 60 200K 35 13 15 0 3 14 ns ns 13 13 ns ns ns 13 ns 6 KM416C4000C, KM416C4100C CMOS DRAM TEST MODE CYCLE Parameter ( Note 11 ) -5 Symbol Min -6 Max Min Units Note Max Random read or write cycle time tRC 95 115 ns Read-modify-write cycle time tRWC 138 160 ns Access time from RAS tRAC 55 65 ns 3,4,10,12 Access time from CAS tCAC 18 20 ns 3,4,5,12 Access time from column address tAA 30 35 ns 3,10,12 RAS pulse width tRAS 55 10K 65 10K ns CAS pulse width tCAS 18 10K 20 10K ns RAS hold time tRSH 18 20 ns CAS hold time tCSH 55 65 ns Column Address to RAS lead time tRAL 30 35 ns CAS to W delay time tCWD 41 43 ns 7 RAS to W delay time tRWD 78 88 ns 7 Column Address to W delay time tAWD 53 58 ns 7 Fast Page mode cycle time tPC 40 45 ns Fast Page mode read-modify-write cycle time tPRWC 81 90 ns RAS pulse width (Fast Page cycle) tRASP 55 Access time from CAS precharge tCPA OE access time tOEA OE to data delay tOED 18 18 ns OE command hold time tOEH 18 20 ns 200K 65 200K ns 35 40 ns 18 20 ns 3 KM416C4000C, KM416C4100C CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. 10. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. These specifications are applied in the test mode. 11. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters 12. should be specified in test mode cycles by adding the above value to the specified value in this data sheet. KM416C40(1)00C Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - KM416C4000C, KM416C4100C CMOS DRAM 13. tASC, tCAH are referenced to the earlier CAS falling edge. 14. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. 16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to the earlier CAS falling edge before RAS transition low. 18. tCHR is referenced to the later CAS rising edge after RAS transition low. RAS LCAS UCAS tCSR tCHR 19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge. LCAS UCAS tDS DQ0 ~ DQ15 tDH Din 20. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP. 21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 22. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM416C4000C, KM416C4100C CMOS DRAM WORD READ CYCLE tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tCRP tRSH VIH - tCAS VIL - tCSH tCRP LCAS tRP VIH - tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tAA OE VIH - tOEA VIL - DQ0 ~ DQ7 VOH VOL - tRAC tCAC tCLZ OPEN tOFF tOEZ DATA-OUT tOFF tCAC DQ8 ~ DQ15 VOH VOL - tRAC OPEN tCLZ tOEZ DATA-OUT Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM LOWER BYTE READ CYCLE NOTE : DIN = OPEN tRC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCSH tCRP LCAS tRSH tCAS VIH VIL - tRAD tASR A tRCD VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEA VIL - DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tOEZ tRAC tCAC tCLZ OPEN DATA-OUT OPEN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM UPPER BYTE READ CYCLE NOTE : DIN = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD tCRP tRSH tCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEA VIL - DQ0 ~ DQ7 VOH - OPEN VOL DQ8 ~ DQ15 VOH VOL - tOEZ tCAC tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRAS RAS VIL - tCSH tRCD tRSH VIH - tCRP tCAS VIL - tCSH tCRP LCAS tRP VIH - tCRP UCAS tRC tRCD tRSH VIH - tCRP tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH - tDS DATA-IN VIL - DQ8 ~ DQ15 VIH VIL - tDH tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCRP UCAS tRPC VIH VIL - tCSH tCRP LCAS tRCD tRSH VIH - tCRP tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRAS RAS VIL - tCSH tRCD tCRP tRSH VIH - tCAS VIL - tCRP LCAS tRP VIH - tCRP UCAS tRC tRPC VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tRSH VIH - tCRP tCAS VIL - tCSH tCRP LCAS tRP VIH - tRCD tRSH VIH - tCRP tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH - tOEH tOED tDS DATA-IN VIL - DQ8 ~ DQ15 VIH VIL - tDH tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCRP UCAS tRPC VIH VIL - tCSH tCRP LCAS tRP VIH - tRCD tRSH VIH - tCRP tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - tOEH tOED tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD tCAS VIL - tCRP LCAS tCRP tRSH VIH - tRPC VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL W OE tRWL VIH - tWP VIL - VIH VIL - tOEH tOED DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM WORD READ - MODIFY - WRITE CYCLE tRWC tRAS RAS VIL - tCRP UCAS tRCD tCAS VIL - tRCD tRSH VIH - tCAS VIL - tRAD tASR A tRSH VIH - tCRP LCAS tRP VIH - VIH VIL - tRAH ROW ADDR tASC tCSH tCAH COLUMN ADDRESS tRWL tAWD tCWL tCWD W OE VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC tAA DQ0 ~ DQ7 VI/OH - tRAC tOED tOEZ VALID DATA-OUT VI/OL - tDS tDH VALID DATA-IN tCLZ tCAC DQ8 ~ DQ15 VI/OH VI/OL - tAA tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM LOWER-BYTE READ - MODIFY - WRITE CYCLE tRWC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCRP LCAS tRCD tRSH VIH - tCAS VIL - tRAD tCSH tASR A VIH VIL - tRAH ROW ADDR tASC tCAH COLUMN ADDRESS tRWL tAWD tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN OPEN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM UPPER-BYTE READ - MODIFY - WRITE CYCLE tRWC tRP tRAS RAS VIH VIL - tCRP UCAS tRCD tRSH VIH - tCAS VIL - tCRP LCAS VIH VIL - tRAD tASR A tRPC VIH VIL - tRAH ROW ADDR tASC tCSH tCAH COLUMN ADDRESS tRWL tAWD tCWL tCWD W OE VIH - tWP VIL - tRWD tOEA VIH VIL - DQ0 ~ DQ7 VI/OH - OPEN VI/OL - tCLZ tCAC DQ8 ~ DQ15 VI/OH VI/OL - tAA tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE WORD READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tRHCP tCSH tPC tCRP UCAS tRCD tPC tCP tCAS VIH - tPC tCP tCAS tCP tCAS tRPC tCAS VIL - tRAL tCRP LCAS tRCD tCAS tCP tCAS VIH VIL - tRAD tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tASC tCAH tASC COLUMN ADDRESS tRCH tCAH tASC COLUMN ADDR tRCS tRCH tCAH COLUMN ADDRESS tRCS tRCH tRCS tRRH tRCH VIH VIL - tCAC tAA OE tRPC tCAS VIL - tRCS W tCP tCAS VIH - tASR A tCP tAA tOEA VIH - tCAC tCAC tAA tAA tCPA tOEA tCPA tOEA tCPA tOEA tOFF tOFF VIL - tCAC DQ0 ~ DQ7 VOH - tRAC tOEZ VALID DATA-OUT VOL - tCLZ tCAC DQ8 ~ DQ15 VOH - VALID DATA-OUT VOL - tOEZ tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT VALID DATA-OUT tOFF tOEZ tRAC tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tCLZ Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE LOWER BYTE READ CYCLE tRASP RAS tRP VIH VIL - ¡ó tRHCP tCRP UCAS tRPC VIH VIL - tPC tCRP LCAS tRCD VIH VIL - VIH VIL - tRAD tRAH tASC tCAH ROW ADDR tPC tCP tCAS tASC tCAH COLUMN ADDRESS tASC tCAH tCAH COLUMN ADDRESS tRRH tRCS tRCH VIH VIL - tCAC tCAC tAA OE tASC tRCS tRCH tRCH tRPC tCAS COLUMN ADDR COLUMN ADDRESS tRCH tCP tCAS tRCS tRCS W tPC tCP tCAS tASR A tRAL tCSH tAA tOEA VIH - tCAC tAA tAA tCPA tOEA tCPA tOEA tCPA tOEA tOFF tOEZ tOFF tOEZ VIL - DQ0 ~ DQ7 VOH - tCAC tRAC VALID DATA-OUT VOL - VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tCLZ DQ8 ~ DQ15 VOH VOL - OPEN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE UPPER BYTE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tCSH tCRP UCAS tRHCP tPC tRCD tPC tCP tCAS VIH - tPC tCP tCAS tCP tCAS tRPC tCAS VIL - tCRP LCAS tRPC VIH - tRAL VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tCAH tASC COLUMN ADDRESS tCAH tRCH tCAH COLUMN ADDRESS tRCS tRCH tRCH tRCS tRRH tRCH VIH VIL - tCAC tCAC tAA OE tASC COLUMN ADDR tRCS tRCS W tASC tAA tOEA VIH - tCPA tOEA tCAC tAA tAA tCPA tOEA tCPA tOEA VIL - DQ0 ~ DQ7 VOH - OPEN VOL - DQ8 ~ DQ15 VOH - tCAC tRAC tOFF tOEZ VALID DATA-OUT VOL - tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tCLZ Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRHCP VIL - ¡ó tPC tCRP UCAS tRCD tPC tCP VIH - tRSH tCP tCAS tCRP tCAS VIL - tCAS ¡ó tPC tCRP LCAS tRP VIH - VIH - tRSH tPC tCP tRCD tCP tCAS tCAS VIL - tCAS ¡ó tRAD tRAL tCSH tASR A VIH VIL - tRAH ROW ADDR tASC tCAH OE VIH - tWCH tCAH COLUMN ADDRESS COLUMN ADDRESS tWCS W tASC tWCS tWP tASC ¡ó ¡ó tWCH tWP tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - VIH - ¡ó VIL - ¡ó DQ0 ~ DQ7 VIH - tDS VIL - tDS tDH tDS tDH ¡ó VALID DATA-IN VIL - DQ8 ~ DQ15 VIH - tDH tDS tDH VALID DATA-IN tDS ¡ó tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRP VIH - tRHCP VIL - ¡ó tRPC tCRP UCAS ¡ó VIH VIL - tPC tCRP LCAS tRCD tPC tCP VIH - tCAS VIL - tRSH tCP tCAS tCAS ¡ó tRAD tRAL tCSH tASR A VIH VIL - tRAH ROW ADDR tASC tCAH COLUMN ADDRESS tWCS W OE VIH - tASC tWCH tCAH COLUMN ADDRESS tWCS tWP tASC ¡ó ¡ó tWCH tWP tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - VIH - ¡ó VIL - ¡ó DQ0 ~ DQ7 VIH VIL - tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRHCP VIL - ¡ó tPC tCRP UCAS tRP VIH - tRCD tPC tCP VIH - tRSH tCP tCAS tCAS VIL - tCAS ¡ó tRPC tCRP LCAS VIH VIL - tRAD tRAL tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH VIH - tWCH tCAH COLUMN ADDRESS COLUMN ADDRESS tWCS W tASC tWCS tWP tASC ¡ó ¡ó tWCH tWP COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - VIH - ¡ó VIL - ¡ó DQ0 ~ DQ7 VIH - ¡ó OE tCAH VIL - DQ8 ~ DQ15 VIH VIL - ¡ó tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tCRP UCAS tRSH tCRP tCP VIH - tCAS tCAS VIL - tCRP LCAS tPRWC tRCD tRCD tCRP tCP VIH - tCAS tCAS VIL - tRAD tRAH tASR A VIH VIL - tRAL tCAH tCAH tASC tASC ROW ADDR COL. ADDR COL. ADDR tRWL tCWL tRCS tCWL W OE tRCS VIH - tWP VIL - tWP tCWD tAWD tRWD VIH - tCWD tAWD tCPWD tOEA tOEA VIL - tOED tCAC tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL - tDS tRAC tCLZ VALID DATA-IN tOED tAA tRAC tOEZ VALID DATA-OUT tCAC tCAC VI/OL - tDS tOEZ tCLZ VALID DATA-OUT DQ8 ~ DQ15 VI/OH - tDH tAA tDH tOEZ tOED tDH tCLZ tOED tDH tAA tDS VALID DATA-IN tDS tOEZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE tRP tRASP RAS tCSH VIH VIL - tCRP UCAS VIH VIL - tCRP LCAS tRPC tPRWC tRCD VIH - tRSH tCP tCAS tCAS VIL - tRAD tRAH tASR A VIH VIL - tRAL tCAH OE tCAH tASC tASC ROW ADDR COL. ADDR COL. ADDR tRCS W tCRP tCWL VIH - tWP VIL - tWP tCWD tAWD tRWD VIH - tCWD tAWD tCPWD tOEA tOEA VIL - tOED tCAC tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL - tRAC tOEZ tDH tCLZ VI/OL - tOED tDH tAA tDS tDS tOEZ tCLZ VALID DATA-OUT DQ8 ~ DQ15 VI/OH - tRWL tCWL tRCS VALID DATA-IN VALID DATA-OUT VALID DATA-IN OPEN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE tRP tRASP RAS tCSH VIH VIL - tCRP UCAS tPRWC tRCD VIH - tRSH tCP tCAS tCRP tCAS VIL - tRPC tCRP LCAS VIH VIL - tRAD tRAH tASR A VIH VIL - tRAL tCAH tASC tASC COL. ADDR ROW ADDR COL. ADDR tRCS W OE tCAH tCWL tRWL tCWL tRCS tWP VIH VIL - tWP tCWD tAWD tRWD VIH - tCWD tAWD tCPWD tOEA tOEA VIL - DQ0 ~ DQ7 VI/OH - OPEN VI/OL - tOED tOED tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tCAC tDH tOEZ tAA tDS tDH tOEZ tDS tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRC VIH - RAS tRP tRAS VIL - tRPC tCRP VIH - UCAS VIL - tCRP VIH - LCAS VIL - tASR VIH - A VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care tRC tRP VIH - RAS VIL - tRP tRAS tCRP tRPC tCP UCAS tCSR VIH - tCHR VIL - tCP LCAS tCSR VIH - tCHR VIL - DQ0 ~ DQ7 VOH - tOFF OPEN VOL DQ8 ~ DQ15 VOH VOL W OPEN tWRP tWRH VIH VIL Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRSH tCHR tRCD tRSH tCHR VIL - VIH VIL - tRAD tASR A tRCD VIH - tCRP LCAS VIH VIL - tRAH tRAL tASC tCAH ROW ADDRESS COLUMN ADDRESS tWRH tRCS W tRP tRAS VIL - tCRP UCAS tRC tRP VIH VIL - tAA OE VIH - tOEA VIL - tOFF tCAC tCLZ DQ0 ~ DQ7 VOH VOL - DQ8 ~ DQ15 VOH VOL - tRAC tOEZ OPEN DATA-OUT OPEN DATA-IN DATA-OUT Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS VIL - tRCD tRSH tCHR tRCD tRSH tCHR VIH VIL - tCRP LCAS tRP tRAS tRAS VIH - tCRP UCAS tRC tRP VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tWRH W OE VIH - tWRP tWCS tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH - tDS DATA-IN VIL DQ8 ~ DQ15 VIH VIL - tDH tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care tRP tRASS tRPS VIH - RAS VIL - tRPC tRPC tCP UCAS VIH - tCSR tCHS tCSR tCHS VIL - tCP LCAS VIH VIL - DQ0 ~ DQ7 VOH - tOFF OPEN VOL DQ8 ~ DQ15 VOH - OPEN VOL - tWRP tWRH VIH - W VIL - TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRC tRP RAS tRP tRAS VIH VIL - tCRP tRPC tCP UCAS tCSR VIH - tCP LCAS W tCHR VIL VIH - tCSR tCHR VIL - tWTS VIH - tWTH VIL - DQ0 ~ DQ15 VOH VOL - tOFF OPEN Don′t care Undefined KM416C4000C, KM416C4100C CMOS DRAM PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 50 TSOP(II) 400mil 0.400 (10.16) 0.455 (11.56) 0.471 (11.96) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.034 (0.875) 0.0315 (0.80) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O