Preliminary CMOS SDRAM KM44S32030 8M x 4Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply The KM44S32030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clcok cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS Latency (2 & 3) -. Burst Length (1, 2, 4, 8) -. Burst Type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst Read Single-bit Write operation ORDERING INFORMATION • DQM for masking • Auto & self refresh Part NO. • 64ms refresh period (4K cycle) MAX Freq. KM44S32030T-G/F8 125MHz KM44S32030T-G/FH 100MHz KM44S32030T-G/FL 100MHz KM44S32030T-G/F10 100MHz Interface Package LVTTL 54pin TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 8M x 4 8M x 4 8M x 4 Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 8M x 4 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 PIN CONFIGURATION (TOP VIEW) VDD N.C VDDQ N.C DQ0 VSSQ N.C N.C VDDQ N.C DQ1 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS 54PIN TSOP (II) (400mil x 875mil) (0.8 mm PIN PITCH) PIN FUNCTION DESCRIPTION PIN NAME INPUT FUNCTION CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, column address : CA0 ~ CA9, CA11 BA0 ~ BA1 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM Data Input/Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0 ~ 3 Data Input/Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No Connection/ Reserved for Future Use This pin is recommended to be left No Connection on the device. REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Symbol Min Typ Max Unit Note VDD, VDDQ 3.0 3.3 3.6 V Input logic high votlage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA Input leakage current(Inputs) IIL -5 - 5 uA 3 Input leakage current (I/O pins) IIL -5 - 5 uA 3,4 Note : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ, Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Parameter Symbol Min Max Unit Clock CCLK 2.5 4 pF RAS, CAS, WE, CS, CKE, DQM CIN 2.5 5 pF Address CADD 2.5 5 pF DQ0 ~ DQ3 COUT 4 6.5 pF REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol ICC1 Active Standby Current in non power-down mode (One Bank Active) CAS Latency Burst Length =1 tRC ≥ tRC(min) IOL = 0 mA Version -8 -H -L -10 120 110 110 105 Unit Note mA 1 ICC2P CKE ≤ VIL(max), tCC = 15ns 1 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 1 ICC2N CKE ≥ VIH(min),CS ≥ VIH(min),tCC=15ns Input signals are changed one time during 30ns 15 ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 7 ICC3P CKE ≤ VIL(max), tCC = 15ns 5 ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 5 ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns. 30 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 20 mA Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Test Condition IOL = 0 mA Page Burst tCCD = 2CLKs Operating Current (Burst Mode) ICC4 Refresh Current ICC5 tRC ≥ tRC(min) Self Refresh Current ICC6 CKE ≤ 0.2V mA mA mA 3 140 115 115 115 2 105 115 105 105 mA 1 mA 2 1 mA 3 600 uA 4 200 165 Note : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. KM44S32030T-G** 4. KM44S32030T-F** REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Input levels (Vih/Vil) Value Unit 2.4 / 0.4 V 1.4 V tr / tf = 1 / 1 ns 1.4 V Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt=1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Output Z0=50Ω 50pF 870Ω 50pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol Row active to row active delay tRRD(min) -8 -H -L -10 16 20 20 20 Unit Note ns 1 RAS to CAS delay tRCD(min) 20 20 20 24 ns 1 Row precharge time tRP(min) 20 20 20 24 ns 1 tRAS(min) 48 50 50 50 ns 1 Row active time tRAS(max) 100 us Row cycle time tRC(min) 68 70 70 80 ns 1 Last data in to row precharge tRDL(min) 8 10 10 12 ns 2 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Number of valid output data CAS latency=3 2 CAS latency=2 1 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 AC CHARACTERISTICS Parameter (AC operating conditions unless otherwise noted) -8 Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to valid output delay Output data hold time CAS latency=3 8 Max 1000 12 tSAC CAS latency=2 CAS latency=3 -H tOH CAS latency=2 Min 10 -L Max 1000 10 Min 10 -10 Max 1000 12 Min 10 Unit Note ns 1 ns 1, 2 ns 2 Max 1000 13 6 6 6 7 6 6 7 7 3 3 3 3 3 3 3 3 CLK high pulse width tCH 3 3 3 3.5 ns 3 CLK low pulse width tCL 3 3 3 3.5 ns 3 Input setup time tSS 2 2 2 2.5 ns 3 Input hold time tSH 1 1 1 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 6 6 6 7 6 6 7 7 ns Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 IBIS Specification 66Mhz and 100Mhz Pull-Up 0 IOH Characteristics(Pull-up) (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 100Mhz min I(mA) 0 -21.1 -34.1 -58.7 -67.3 -73 -77.9 -80.8 -88.6 -93 100Mhz max I(mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197 -226.2 -248 -269.7 -284.3 -344.5 -502.4 -0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93 0.5 1 1.5 2 2.5 3 3.5 3 3.5 0 66Mhz min I(mA) -100 -200 ma Voltage -300 -400 -500 -600 voltage Ioh min(100Mhz) Ioh min(66Mhz) Ioh max(66 and 100Mhz) 66Mhz and 100Mhz Pull-Down IOL Characteristics(Pull-Down) (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 100Mhz min I(mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100Mhz max I(mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66Mhz min I(mA) 0.0 17.7 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9 250 200 150 ma Voltage 100 50 0 0 0.5 1 1.5 2 2.5 voltage Iol min(100Mhz) Iol min(66Mhz) Iol max(100Mhz) REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 Minimum VDD Clamp Current (referenced to VDD) VDD Clamp @CLK,CKE, CS,DQM & DQ I(mA) 0.0mA 0.0mA 0.0mA 0.0mA 0.0mA 0.0mA 0.0mA 0.23mA 1.34mA 3.02mA 5.06mA 7.35mA 9.83mA 12.48mA 15.30mA 18.31mA 20 15 I(ma) VDD 0.0V 0.2V 0.4V 0.6V 0.7V 0.8V 0.9V 1.0V 1.2V 1.4V 1.6V 1.8V 2.0V 2.2V 2.4V 2.6V 10 5 0 0 1 2 3 Voltage I(ma) Minimum VSS Clamp Current VSS Clamp @CLK,CKE, CS,DQM & DQ I(mA) -57.23mA -45.77mA -38.26mA -31.22mA -24.58mA -18.37mA -12.56mA -7.57mA -3.37mA -1.75mA -0.58mA -0.05mA 0.0mA 0.0mA 0.0mA 0.0mA -3 -2 -1 0 0 -10 -20 I(ma) VSS -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 -30 -40 -50 -60 Voltage I(ma) REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE KM44S32030T-8 (Unit : number of clock) CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 68ns 48ns 20ns 16ns 20ns 8ns 8ns 8ns 125MHz (8.0ns) 3 9 6 3 2 3 1 1 1 100MHz (10.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 4 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 5 4 2 2 2 1 1 1 Frequency (Unit : number of clock) KM44S32030T-H CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (10.0ns) 2 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 5 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 3 2 2 2 1 1 1 Frequency (Unit : number of clock) KM44S32030T-L CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100MHz (10.0ns) 3 7 5 2 2 2 1 1 1 83MHz (12.0ns) 2 6 5 2 2 2 1 1 1 75MHz (13.0ns) 2 6 4 2 2 2 1 1 1 66MHz (15.0ns) 2 5 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 3 2 2 2 1 1 1 Frequency (Unit : number of clock) KM44S32030T-10 Frequency CAS Latency tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL 80ns 50ns 24ns 20ns 24ns 10ns 10ns 12ns 100MHz (10.0ns) 3 8 5 3 2 3 1 1 2 83MHz (12.0ns) 3 7 5 2 2 2 1 1 1 75MHz (13.0ns) 2 7 4 2 2 2 1 1 1 66MHz (15.0ns) 2 6 4 2 2 2 1 1 1 60MHz (16.7ns) 2 5 3 2 2 2 1 1 1 REV. 2 Mar. '98 Preliminary CMOS SDRAM KM44S32030 SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X H Entry Self Refresh Exit H H Bank Active & Row Addr. H X Read & Column Address Auto Precharge Disable H X Write & Column Address Auto Precharge Disable L H H H H X X X L L H H X V L H L H X V X X L H L L H X X L L H L H H L L X H L Exit L H Entry H L Precharge Power Down Mode Exit L V Column Address (A0~A9,A11) L X X All Banks Entry L DQM H No Operation Command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row Address Column Address (A0~A9,A11) H H Clock Suspend or Active Power Down 3 3 Auto Precharge Enable Bank Selection 1, 2 X H H Note 3 Auto Precharge Enable Burst Stop A10/AP L L Precharge BA0,1 A11, A9 ~ A0 CKEn-1 X V L X H 4 4, 5 4 4, 5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) REV. 2 Mar. '98