SAMSUNG KM684002

KM684002, KM684002E, KM684002I
PRELIMINARY
CMOS SRAM
Document Title
512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial, Extended and Industrial Temperature Range.
Revision History
Rev No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Preliminary.
Jun. 1th, 1991
Preliminary
Rev. 1.0
Release to final Data Sheet.
1.1. Delete Preliminary
Oct. 4th, 1993
Final
Rev. 2.0
2.1. Delete 15ns part
2.2. Add 17ns part.
2.3.Add the test condition for Voh1 with Vcc=5V±5% at 25°C
Apr. 2th, 1994
Final
Rev. 3.0
3.1.Delete Low power product with Data Retention Mode.
3.1.1. Delete Data Retention Characteristics
3.2.Add Industrial and Extended Temperature Range parts with the
same parameters as Commercial Temperature Range parts.
3.2.1 Add KM684002I for Industrial Temperature Range.
3.2.2.Add KM684002E for Extended Temperature Range.
3.2.3.Add ordering information.
3.2.4. Add the condition for operating at Industrial and Extended
Temperature Range.
3.3.Add timing diagram to define tWP as ″(Timing Wave Form of
Write Cycle(CS=Controlled)″
Jun. 17th, 1997
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
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GENERAL DESCRIPTION
Fast Access Time 17,20,25§À(Max.)
Low Power Dissipation
Standby (TTL)
: 60§Ì(Max.)
(CMOS) : 10§Ì(Max.)
Operating KM684002 - 17 : 180§Ì(Max.)
KM684002 - 20 : 170§Ì(Max.)
KM684002 - 25 : 160§Ì(Max.)
Single 5.0V±10% Power Supply
TTL Compatible Inputs and Outputs
I/O Compatible with 3.3V Device
Fully Static Operation
- No Clock or Refresh required
Three State Outputs
Center Power/Ground Pin Configuration
Standard Pin Configuration
KM684002J : 36-SOJ-400
The KM684002 is a 4,194,304-bit high-speed Static Random
Access Memory organized as 524,288 words by 8 bits. The
KM684002 uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung's
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM684002 is packaged in
a 400 mil 36-pin plastic SOJ.
PIN CONFIGURATION(Top View)
ORDERING INFORMATION
A0
1
36 N.C
A1
2
35 A18
A2
3
34 A17
A3
4
33 A16
KM684002 -17/20/25
Commercial Temp.
A4
5
32 A15
KM684002E -17/20/25
Extended Temp.
CS
6
31 OE
Industrial Temp.
I/O1
7
30 I/O8
I/O2
8
KM684002I -17/20/25
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A7
A8
A9
A13
A14
Pre-Charge Circuit
Row Select
Clk Gen.
Memory Array
1024 Rows
512x8 Columns
Data
Cont.
I/O Circuit
Column Select
SOJ
29 I/O7
Vcc
9
28 Vss
Vss
10
27 Vcc
I/O3 11
26 I/O6
I/O4 12
25 I/O5
WE
13
24 A14
A5
14
23 A13
A6
15
22 A12
A7
16
21 A11
A8
17
20 A10
A9
18
19 N.C
PIN FUNCTION
I/O1 ~ I/O8
Pin Name
A0 - A18
CLK
Gen.
A6
A5
A10
Write Enable
CS
Chip Select
I/O1 ~ I/O8
CS
WE
Address Inputs
WE
OE
A11
A15
A17
A12
A16 A18
Pin Function
Output Enable
Data Inputs/Outputs
VCC
Power(+5.0V)
VSS
Ground
N.C
No Connection
OE
-2-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Rating
Unit
VIN, VOUT
-0.5 to 7.0
V
Voltage on VCC Supply Relative to VSS
VCC
-0.5 to 7.0
V
Power Dissipation
PD
1.0
W
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Extended
TA
-25 to 85
°C
Industrial
TA
-40 to 85
°C
Voltage on Any Pin Relative to VSS
Storage Temperature
Operating Temperature
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and functional operation of the device at these at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input Low Voltage
VIH
2.2
-
VCC+0.5**
V
Input Low Voltage
VIL
-0.5*
-
0.8
V
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
* VIL(Min) = -2.0V a.c(Pulse Width ≤10ns) for I≤20§Ì
** VIH(Max) = V CC + 2.0V a.c (Pulse Width ≤10ns) for I≤20§Ì
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc= 5.0V±10%, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCC
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT = VSS to VCC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA
ISB
Min. Cycle, CS=VIH
Standby Current
Output Low Voltage Level
Output High Voltage Level
17ns
-
180
20ns
-
170
25ns
-
160
-
60
§Ì
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-
10
§Ì
VOL
IOL=8mA
-
0.4
V
IOH=-4mA
2.4
-
V
-
3.95
V
VOH
VOH1*
IOH1=-0.1mA
§Ì
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
* VCC=5.0V±5% Temp. = 25°C
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
6
pF
* NOTE : Capacitance is sampled and not 100% tested .
-3-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3§À
Input and Output timing Reference Levels
1.5V
Output Loads
See below
NOTE: Above test conditions are also applied at industrial temperature ranges.
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
+5.0V
480Ω
480Ω
DOUT
255Ω
DOUT
255Ω
30pF*
5pF*
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
Symbol
KM684002-17
KM684002-20
KM684002-25
Min
Max
Min
Max
Min
Max
Unit
Read Cycle Time
tRC
17
-
20
-
25
-
§À
Address Access Time
tAA
-
17
-
20
-
25
§À
Chip Select to Output
tCO
-
17
-
20
-
25
§À
Output Enable to Valid Output
tOE
-
8
-
10
-
12
§À
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
§À
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
§À
Chip Disable to High-Z Output
tHZ
0
7
0
8
0
10
§À
Output Disable to High-Z Output
tOHZ
0
7
0
8
0
10
§À
Output Hold from Address Change
tOH
3
-
4
-
5
-
§À
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
§À
Chip Selection to Power DownTime
tPD
-
17
-
20
-
25
§À
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
-4-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
WRITE CYCLE
Parameter
Symbol
KM684002-17
KM684002-20
KM684002-25
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
17
-
20
-
25
-
§À
Chip Select to End of Write
tCW
12
-
13
-
15
-
§À
Address Set-up Time
tAS
0
-
0
-
0
-
§À
Address Valid to End of Write
tAW
12
-
13
-
15
-
§À
Write Pulse Width(OE High)
tWP
12
-
13
-
15
-
§À
Write Pulse Width(OE Low)
tWP1
17
-
20
-
25
-
§À
Write Recovery Time
tWR
0
-
0
-
0
-
§À
Write to Output High-Z
tWHZ
0
8
0
8
0
10
§À
Data to Write Time Overlap
tDW
8
-
9
-
10
-
§À
Data Hold from Write Time
tDH
0
-
0
-
0
-
§À
End Write to Output Low-Z
tOW
3
-
4
-
5
-
§À
NOTE: Above parameters are also guaranteed at extended and industrial temperature ranges.
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, WE=VIH)
tRC
ADD
tAA
tOH
Data Out
Previous Data Valid
Data Valid
-5-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
TIMING WAVE FORM OF READ CYCLE(2)(WE=VIH)
tRC
ADD
tAA
tCO
tHZ(3,4,5)
CS
tOHZ
tOE
OE
tOLZ
tOH
tLZ(4,5)
Data Valid
Data Out
tPU
Vcc
Icc
Current
ISB
tPD
50%
50%
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels.
4. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ (Min.) both for a given device and from device to device.
5. Transition is measured ±200§Æ from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
TIMING WAVE FORM OF WRITE CYCLE(1)(OE=Clock)
tWC
ADD
tWR(5)
tAW
OE
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDW
Data In
High-Z
tDH
Data Valid
tOHZ(6)
High-Z(8)
Data Out
-6-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
TIMING WAVE FORM OF WRITE CYCLE(2)(OE=Low Fixed)
tWC
ADD
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tOH
tWP1(2)
WE
tDW
Data In
High-Z
tDH
Data Valid
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data Out
TIMING WAVE FORM OF WRITE CYCLE(3)(CS=Controlled)
tWC
ADD
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDW
Data In
High-Z
tLZ
Data Out
tWHZ(6)
High-Z
Data Valid
tDH
High-Z
High-Z(8)
-7-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. t WP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output mus t not
be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
L
H
X*
Not Select
High-Z
ISB, ISB1
H
Output Disable
High-Z
ICC
L
L
H
L
Read
DOUT
ICC
L
X
Write
DIN
ICC
* NOTE : X means Don't Care.
-8-
Rev 3.0
June -1997
PRELIMINARY
CMOS SRAM
KM684002, KM684002E, KM684002I
PACKAGE DIMENSIONS
36-SOJ-400
Units : Inches (millimeters)
#36
10.16
0.400
#19
11.18±0.12
0.440±0.005
9.40±0.25
0.370±0.010
0.20
+0.10
-0.05
0.008 +0.004
-0.002
#1
#18
0.69
MIN
0.027
23.90 MAX
0.941
23.50±0.12
0.925±0.005
( 1.19 )
0.047
3.76
MAX
0.148
0.10 MAX
0.004
( 0.95 )
0.0375
0.43 +0.10
-0.05
0.017 +0.004
-0.002
0.71 +0.10
-0.05
0.028 +0.004
-0.002
1.27
0.050
-9-
(
1.27
)
0.050
Rev 3.0
June -1997