ETC L64780

L64780
DVB-T COFDM
Demodulator
Technical Manual
February 2000
®
Order No. I14027
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000113-00, First Edition (February 2000)
This document describes LSI Logic Corporation’s L64780 DVB-T COFDM
Demodulator and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design and G10 are registered trademarks of LSI Logic
Corporation. All other brand and product names may be trademarks of their
respective companies.
Copyright © 1999, 2000 by LSI Logic Corporation. All rights reserved.
ii
Preface
This book is the primary reference and technical manual for the L64780
DVB-T COFDM Demodulator. It contains a complete functional
description as well as complete physical and electrical specifications for
the LSI Logic L64780.
Audience
This document assumes you are familiar with digital video broadcasting,
terrestrial television transmission and reception,
modulation/demodulation, error control coding, digital signal processing,
microprocessors, and related support devices. The people who benefit
from this book are:
•
engineers and managers evaluating the L64780 for use in a receiver
for digital TV or cable data transmissions.
•
engineers designing the L64780 into a system.
Organization
This document has the following chapters and appendixes:
•
Chapter 1, Introduction, provides a brief overview of the L64780
and lists its features and benefits.
•
Chapter 2, Architectural Overview, describes the architecture of the
L64780 and gives a functional description of its main components.
•
Chapter 3, Interfaces, describes the interfaces of the L64780 and
gives a functional description of each.
•
Chapter 4, Register Descriptions, provides a description of the
registers that determine the functionality of the L64780.
Preface
iii
•
Chapter 5, Signal Descriptions, provides a description of the
signals used and generated by the L64780.
•
Chapter 6, Specifications, describes the specifications for the
L64780 electrical and mechanical characteristics.
•
Appendix A, Programming the L64780 Using The Serial Bus
Interface, describes how to program the L64780 using the Serial
Bus.
Related Publications
ETSI Specification ETS 300 744. 1997. “Digital broadcasting systems for
television, sound and data services; Framing structure, channel coding
and modulation for digital terrestrial television.”
Stott, J.H., 1996. The DVB Terrestrial (DVB-T) Specification and its
Implementation In a Practical Modem. International Broadcasting
Convention 1996.
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” (for example,
0x32CF). Binary numbers are indicated by the prefix “0b” (for example,
0b0011.0010.1100.1111).
iv
Preface
Contents
Chapter 1
Chapter 2
Introduction
1.1
Overview
1.2
Using the L64780 in a Receiver
1.3
RF Tuner Block Functions
1.4
Modes of Operation
1.5
Features
1.6
Typical Performance
Architectural Overview
2.1
Demodulator Module Functional Description
2.2
Analog-to-Digital Converter (ADC)
2.3
Automatic Gain Control (AGC)
2.3.1
AGC Target RMS Value
2.3.2
AGC External Loop Filter
2.3.3
AGC Loop Gain Ks
2.4
Real-to-Complex Conversion
2.5
Fast Fourier Transform (FFT) Block
2.6
Time Synchronization
2.6.1
Timing Loop Gain
2.6.2
TIM_CLK_INIT Register Definition
2.6.3
TIM External Loop Filter
2.7
Automatic Frequency Control (AFC)
2.7.1
Analog Frequency Synchronization
2.7.2
Digital Frequency Synchronization
2.7.3
AFC Loop Gain
2.7.4
AFC_INIT_FREQ Register Definition
2.7.5
AFC External Loop Filter
2.8
TPS Decoding and Frame Synchronization
2.9
Mode Control Logic
Contents
1-1
1-3
1-4
1-6
1-6
1-7
2-2
2-4
2-4
2-4
2-5
2-6
2-7
2-8
2-8
2-8
2-9
2-9
2-10
2-10
2-10
2-11
2-12
2-12
2-13
2-14
v
2.10
2.11
2.12
2.13
Chapter 3
Chapter 4
vi
Channel Estimation and Equalization
Viterbi Metric Assignment and Quantization
Symbol Deinterleaver
Bit Deinterleaver
2-15
2-16
2-17
2-17
Interfaces
3.1
Output Interface
3.1.1
Output Format in Nonhierarchical Mode
3.1.2
Output Format in Hierarchical Mode
3.2
MUXIN Interface
3.2.1
Access to Timing and DDFS Blocks
3.2.2
Access to the AFC Block
3.2.3
Access to the FFT Block
3.2.4
Access to the CSI Block
3.2.5
Access to the SDI Block
3.3
MUXOUT Interface
3.3.1
DDFS Output
3.3.2
FFT Output
3.3.3
AFC Output
3.3.4
Channel Equalizer (CE) Output
3.3.5
CSI Output
3.3.6
ADC Output
3.4
Microprocessor Interface
3-1
3-1
3-5
3-8
3-10
3-10
3-11
3-11
3-12
3-13
3-14
3-14
3-14
3-15
3-15
3-16
3-16
Register Descriptions
4.1
Memory Map
4.2
Interrupt Registers
4.2.1
Address Line 0x00
4.2.2
Interrupt Mask Register, Address Line 0x01
4.3
TPS Registers
4.3.1
Address Line 0x02
4.3.2
Address Line 0x03
4.3.3
Address Line 0x04
4.4
Parameter Registers
4.4.1
Address Line 0x05
4.4.2
Address Lines 0x06, 0x07, 0x08
4.4.3
Address Line 0x09
4-2
4-7
4-7
4-9
4-11
4-11
4-12
4-14
4-16
4-16
4-19
4-20
Contents
4.5
4.6
4.7
4.8
Chapter 5
Chapter 6
4.4.4
Address Line 0x0A
4.4.5
Address Line 0x0B
4.4.6
Address Line 0x0C
4.4.7
Address Line 0x0D
4.4.8
Address Line 0x0E
4.4.9
Address Lines 0x0F, 0x10
4.4.10 Address Line 0x11
4.4.11 Address Line 0x12
4.4.12 Address Line 0x13
4.4.13 Address Line 0x14
Mux Register Address Line 0x15
Performance Monitoring Registers Address Line 0x16
4.6.1
Address Line 0x17
4.6.2
Address Line 0x18
Mode Register Address Line 0x19
3-Wires Register Address Line 0x1A
4-23
4-24
4-25
4-27
4-27
4-28
4-29
4-30
4-31
4-31
4-32
4-34
4-35
4-35
4-36
4-38
Signal Descriptions
5.1
Overview
5.2
Microprocessor Interface
5.3
Main Signals
5.4
Sigma-Delta Outputs
5.5
MUX Signals
5.6
3-Wires Signals
5.7
JTAG Signals
5.8
Test Pins
5.9
ASIC Pins
5.10 PLL Pins
5.11 Tester Pins
5-1
5-3
5-4
5-6
5-6
5-7
5-7
5-8
5-8
5-8
5-9
Specifications
6.1
Electrical Specifications
6.2
AC Timing
6.2.1
Input Data Interface
6.2.2
Output Data Interface
6.2.3
Reset Timing
6.3
Signal Specifications
6-1
6-4
6-4
6-5
6-5
6-6
Contents
vii
6.4
6.5
Appendix A
Pinouts
6.4.1
Pin List
6.4.2
Pin Layout
Mechanical Drawing
Programming the L64780 Using The Serial Bus Interface
A.1 Serial Bus Protocol Overview
A.2 Programming the Slave Address Using the Serial Bus
A.2.1
Write Cycle Using the Serial Bus
A.2.2
Read Cycle Using the Serial Bus
6-11
6-11
6-14
6-15
A-2
A-3
A-3
A-4
Customer Feedback
Figures
1.1
1.2
1.3
1.4
1.5
1.6
2.1
2.2
2.3
2.4
2.5
2.6
3.1
3.2
3.3
3.4
3.5
3.6
3.7
viii
Typical Terrestrial-Only Receiver
UHF Tuner Example
Receiver Architecture for Satellite and Terrestrial
Reception
Performance with Additive Write Gaussian
Noise (AWGN)
DVB-T Carrier to Co-channel PAL-I Interference
Ratio for Failure
Maximum Level of a Single Echo for Failure of QPSK,
Rate 1/2, Guard Interval 7
DTTV Demodulator Architecture
Structure of 9-Bit AGC_TARGET Register
AGC Loop Pass Filter
External Low-Pass Loop Filter
AFC Loop Pass Filter
Scattered Pilot Structure
Output Interface in Nonhierarchical and Serial Modes
Nonhierarchical, Serial Mode, 64 QAM Constellation
Nonhierarchical, Serial Mode, 16 QAM Constellation
Nonhierarchical, Serial Mode, QPSK Constellation
Output Interface in Nonhierarchical and Parallel Modes
Nonhierarchical, Parallel Mode, 64 QAM Constellation
Nonhierarchical, Parallel Mode, 16 QAM Constellation
Contents
1-3
1-4
1-5
1-7
1-8
1-8
2-3
2-4
2-5
2-9
2-12
2-15
3-2
3-2
3-3
3-3
3-3
3-4
3-4
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28
4.1
4.2
4.3
4.4
5.1
6.1
6.2
6.3
6.4
6.5
6.6
A.1
A.2
Nonhierarchical, Parallel Mode, QPSK Constellation
Output Interface in Hierarchical and Two FECs Modes
Hierarchical, Two FEC Decoders, 16 QAM
Constellation
Hierarchical, Two FEC Decoders, 64 QAM
Constellation
Output Interface in Hierarchical and One FEC Mode
Hierarchical, One FEC Decoder Mode With 16 QAM
(HP or LP Selected) or 64 QAM (LP Selected only)
Hierarchical, One FEC Decoder Mode With 64 QAM
(HP Selected Only)
MUXIN Signals Interface
Timing and DDFS Input Mapping
AFC Input Mapping
FFT Input Mapping
CSI Input Mapping
SDI Input Mappings
D[23:0] Bus Mapping in Three-Bit Soft Decision
D[23:0] Bus Mapping in Four-Bit Soft Decision
DDFS Output Mapping
FFT Output Mapping
AFC Output Mappings
CE Output Mappings
CSI Output Mappings
ADC Output Mapping
Graphical View of the L64780 Register Address Space 1
Graphical View of the L64780 Register Address Space 2
Graphical View of the L64780 Register Address Space 3
Interrupt Generation
L64780 Logic Symbol
Input Data AC Timing
Output Data AC Timing
Reset Timing
Package Pin Layout
160 PQFP Mechanical Drawing: Top and Side Views
160 PQFP Mechanical Drawing: Detail
Serial Bus Overview
General Call Address
Contents
3-4
3-5
3-5
3-6
3-6
3-7
3-7
3-8
3-10
3-10
3-11
3-11
3-12
3-12
3-12
3-14
3-14
3-14
3-15
3-15
3-16
4-4
4-5
4-6
4-9
5-2
6-4
6-5
6-5
6-14
6-15
6-16
A-2
A-3
ix
Tables
2.1
3.1
3.2
3.3
3.4
4.1
4.2
4.3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
x
Approximate and Exact Frequencies for Real to
Complex Conversion
MUXINBUS Mapping
MUXIN Conifguration
MUXOUT_select Word Definition
Mode Selection Using the P_S Input Signal
L64780 Registers and Internal Memory Map
DDFS Block Modes
MUXIN Signal Settings and MUXIN Clock
Absolute Maximum Ratings
Recommended Operating Conditions
DC Characteristics
Input Data AC Timing Parameters
Output Data AC Timing Parameters
Reset AC Timing Parameters
Signal Summary List
Contents
2-7
3-8
3-9
3-13
3-16
4-2
4-21
4-33
6-1
6-2
6-2
6-4
6-5
6-5
6-6
Chapter 1
Introduction
This chapter provides an overview of the LSI Logic L64780 DVB-T
COFDM Demodulator. It also lists this chip’s features and benefits, and
provides an illustrated description of its typical performance. This chapter
contains the following sections:
•
Section 1.1, “Overview,” page 1-1
•
Section 1.2, “Using the L64780 in a Receiver,” page 1-3
•
Section 1.3, “RF Tuner Block Functions,” page 1-4
•
Section 1.4, “Modes of Operation,” page 1-6
•
Section 1.5, “Features,” page 1-6
•
Section 1.6, “Typical Performance,” page 1-7
1.1 Overview
The L64780 is part of a digital terrestrial television receiver for signals
transmitted in accordance with the Digital Video BroadcastingTerrestrial/European Telecommunications Standards Institute
(DVB-T/ETSI) specification. These signals convey digital information
using Coded Orthogonal Frequency Division Multiplexing (COFDM), as
well as concatenated Reed-Solomon and convolutional forward error
correction (FEC) techniques. This information payload takes the form of
an MPEG-2 transport stream that conveys picture, sound, and data
information. This MPEG-2 transport stream format is used also in related
specifications for the transmission of digital television signals by satellite
or cable.
L64780 DVB-T OFDM Demodulator
1-1
The concatenated coding used in the DVB-T/ETSI specification is
identical to that in the DVB-S specification for satellite transmissions. The
FEC decoder can take the same form in receivers for satellite as well as
terrestrial transmissions. Thus, the L64780 chip provides all the
necessary demodulation functions except for FEC decoding, which is
done by a separate chip, such as the L64724 or the L64705. The L64780
I/O format and pinouts simplify its connection to the L64724/L64705.
The DVB-T/ETSI specification incorporates many modes, providing a
wide range of capacity/performance trade-off options. The L64780
demodulates all these modes.
Terrestrial transmission paths are prone to multipath, which can result in
“ghosting” on analog television pictures. With conventional methods of
digital transmission, multipath causes inter-symbol interference. This
becomes increasingly problematic as the bit rate increases.
The DVB-T/ETSI specification uses a special form of modulation that
uses Coded Orthogonal Frequency Division Multiplexing, which is
well-suited to channels with significant multipath. It can tolerate signals
with long delay and high relative amplitude. Consequently, the L64780
can accommodate natural multipath (from terrain, buildings, etc.) and it
can be used in a Single Frequency Network (SFN). In an SFN, many
transmitters operate on the same frequency with the same modulation
(used in Digital Audio Broadcasting, which also uses COFDM).
In the frequency domain, multipath can be seen as channel frequency
selectivity. COFDM applies concatenated FEC coding, then distributes
the coded data over many carriers (1705 or 6817 in this case, depending
on the mode). At the receiver, the frequency selectivity of the channel
causes some carriers to be degraded or suppressed. However, the
receiver can determine how much each carrier is affected by noise, then
pass this information to the inner-code Viterbi decoder by means of
soft-decision bits. This allows the Viterbi decoder to decode the data
more efficiently. A second decoder, for the Reed-Solomon FEC,
completes the process.
1-2
Introduction
1.2 Using the L64780 in a Receiver
The L64780 provides those parts of a receiver for DVB-T signals that are
exclusive to the terrestrial specification for COFDM demodulation and
inner interleaving. This includes synchronization, channel-equalization,
and derivation of channel-state information.
The combination of the LSI Logic L64780 and L64724 (or L64705) chips
forms the core of a receiver design for DVB-T, supporting two possible
approaches: exclusively DVB-T reception, and dual DVB-T/DVB-S
reception (see Figure 1.1).
Figure 1.1
Typical Terrestrial-Only Receiver
VCXO
AGC
fCLK18
L64780
Tuner
TS
L64724
MPEG
TS Demux
MPEG
A/V Decoder
L64005
AFC
System CPU
L64118
AGC (automatic gain control)
AFC (automatic frequency control)
Figure 1.1 shows the basic structure for a terrestrial-only receiver. The
UHF (or, possibly, VHF) signal from the antenna passes through a Tuner
module that delivers a low intermediate frequency (IF) signal to the
L64780 chip by means of an analog-to-digital converter (ADC). The
L64780 chip performs all the essential functions for COFDM
demodulation, excluding the final steps of error correction. It requires a
sampling-frequency clock oscillator (at fCLK18 MHz), for which it provides
the control voltage to lock its frequency to the desired value. The L64780
chip delivers soft-decision information to the L64705 or L64724 chip,
Using the L64780 in a Receiver
1-3
which then completes the error correction, delivering an MPEG-2
Transport Stream. Other MPEG-standard LSI Logic chips (for example,
L64118 and L64005) can then be used to demultiplex the MPEG-2
Transport Stream into its coded audio, coded video, and data
components, handle Conditional Access, and decode the audio and
video signals for presentation to the display and loudspeakers. In
Figure 1.1, the microprocessor is embedded in the L64118. It controls
RF-channel selection, mode selection for the L64780 chip, and program
selection for the MPEG demultiplexer.
1.3 RF Tuner Block Functions
Figure 1.2 indicates the functions performed within the RF Tuner block.
The example uses a double-conversion approach, in which the RF Tuner
converts the UHF signal to a first IF (IF1, where filtering, amplification,
and gain control are done) followed by another conversion to the second
low IF, (IF2), required at the input of the L64780.
Figure 1.2
UHF Tuner Example
Tracking
RF Filter
IF 2
Filter
IF 1
Filter
L64780
LO 1
1-4
Introduction
LO 2
Figure 1.3 illustrates how terrestrial and satellite reception can be
combined in one unit. For satellite reception, the IF signal (for example,
from 1 to 2 GHz) from the dish unit is fed into a satellite tuner. This tuner:
1. Selects one RF signal from the 1 to 2 GHz range
2. Converts the signal to one or more intermediate frequencies
3. Down-converts the signal to base band
4. Feeds its I and Q components into the L64724 single-chip DVB-S
satellite receiver
The L64724:
1. Samples the I and Q baseband signals
2. Demodulates the QPSK
3. Processes the error correction functions
The L64724 also implements a bypass of the ADC and demodulation
functions. Thus, it can accept the soft decisions delivered by L64780 and
feed them directly to the Viterbi decoder. This architecture implements a
cost-effective solution for mixed satellite and terrestrial front-ends.
Figure 1.3
Receiver Architecture for Satellite and Terrestrial Reception
UHF/VHF
Terrestrial Tuner
L64780
L-band
Satellite Tuner
L64724
RF Tuner Block Functions
MPEG Transport Stream
1-5
1.4 Modes of Operation
The L64780 supports all the modes of the DVB-T specification, including:
•
2 K and 8 K FFT sizes
•
Nonhierarchical QPSK, 16 QAM, and 64 QAM constellations
•
Hierarchical 16 QAM and 64 QAM constellations
•
Constellation scale factors α = 1, 2, and 4
•
Code rates of 1/2, 2/3, 3/4, 5/6, and 7/8
•
Guard intervals of 1/4, 1/8, 1/16, and 1/32
1.5 Features
The L64780 features include:
1-6
•
DVB-T compliance
•
Internal or external DAC
•
Digital real-to-complex conversion
•
Spectrum inversion
•
2 K or 8 K FFT size
•
Rapid time synchronization
•
Rapid frequency synchronization
•
Common phase error correction
•
High-order filter for frequency interpolation
•
Automatic mode switching
•
Automatic frame detection
•
Use of channel state information for protection against multipath and
interference
•
3- or 4-bit soft decision outputs
•
Analog or digital AFC
•
AGC
Introduction
•
Stand-alone FFT mode (forward or inverse)
•
Easy connection to the L64705 or L64724 for FEC
•
160-pin PQFP package
1.6 Typical Performance
Figure 1.4 illustrates the target performance of the L64780 compared to
the simulation results in the ETSI specification for all the nonhierarchical
modes in a Gaussian channel. Differences between the target
performance and the simulations are accounted for as follows:
•
About 1.5 dB for the noisy reference effect in the channel equalizer
•
0.1–0.3 dB for noise on the channel state measurement
It is not possible to be specific about the source of the remaining small
difference (about 0.4 dB) because we do not have enough information
about the conditions under which the simulations were performed.
The two losses (in the channel equalizer and channel state information)
are compromises made in the interests of the speed of tracking of a
time-varying channel. Sacrificing the tracking ability reduces the losses.
Figure 1.4
Performance with Additive Write Gaussian Noise
(AWGN)
25
CIN (dB)
20
15
10
5
0
1/2 2/3 3/4 5/6 7/8
QPSK
1/2 2/3 3/4 5/6 7/8
16 QAM
1/2 2/3 3/4 5/6 7/8
64 QAM
Measured QEF
Simulated QEF from specification
Typical Performance
1-7
Figure 1.5 illustrates the target protection ratio of PAL-I into DVB-T. The
point indicated by “carriers coincident about here” shows the point where
the vision carrier of the PAL-I signal lines up directly with one of the
carriers on the ODFM frequency raster.
Figure 1.5
DVB-T Carrier to Co-channel PAL-I Interference Ratio
for Failure
2
0
CIN (dB)
−2
Less Robust
−4
Carriers coincident
about here
−6
More Robust
−8
−10
−12
−2500
−1500
−500
500
Normal Frequency Offset (Hz)
64 QAM Rate 2/3
16 QAM Rate 3/4
QPSK Rate 1/2
1500
2500
Figure 1.6 illustrates the maximum level of echo acceptable to the
demodulator. The graph shows that in the selected mode, the
demodulator works without failure inside the guard interval and without
failure significantly outside it.
Relative Level
Figure 1.6
0
−2
−4
−6
−8
Maximum Level of a Single Echo for Failure of QPSK,
Rate 1/2, Guard Interval 7
No failure for echo here.
−10
0 10 20 30 40 50 60 70 80 90 100
Delay (µs)
1-8
Introduction
Chapter 2
Architectural Overview
This chapter describes the L64780 architecture and provides a functional
description of each of its components. It contains the following sections:
•
Section 2.1, “Demodulator Module Functional Description,” page 2-2
•
Section 2.2, “Analog-to-Digital Converter (ADC),” page 2-4
•
Section 2.3, “Automatic Gain Control (AGC),” page 2-4
•
Section 2.4, “Real-to-Complex Conversion,” page 2-7
•
Section 2.5, “Fast Fourier Transform (FFT) Block,” page 2-8
•
Section 2.6, “Time Synchronization,” page 2-8
•
Section 2.7, “Automatic Frequency Control (AFC),” page 2-10
•
Section 2.8, “TPS Decoding and Frame Synchronization,” page 2-13
•
Section 2.9, “Mode Control Logic,” page 2-14
•
Section 2.10, “Channel Estimation and Equalization,” page 2-15
•
Section 2.11, “Viterbi Metric Assignment and Quantization,”
page 2-16
•
Section 2.12, “Symbol Deinterleaver,” page 2-17
•
Section 2.13, “Bit Deinterleaver,” page 2-17
L64780 DVB-T OFDM Demodulator
2-1
2.1 Demodulator Module Functional Description
The components of the L64780 are integrated to provide a complete
system solution for demodulation of terrestrial and satellite originated
signals. Figure 2.1 shows the components of the L64780 and indicates
their interaction. These components are described in the following
sections.
2-2
Architectural Overview
Figure 2.1
DTTV Demodulator Architecture
Analog AFC Control
AGC Control
AGC
Detect
SD
Demodulator Module Functional Description
Digital
AFC Control Frequency
Sync
CSI
Low IF
Input
ADC
Real
to
Complex
Frequency
Shift
FFT
Time
Sync
CPE
Correction
Channel
Estimation
& Equalization
TPS
Decoder
Viterbi
Metrics
Quantize
Symbol
Deintlv.
Frame Pulse
Configuration Information
Guard Interval Configuration
and FFT Size
SD
VCXO
FFT = Fast Fourier Transform
ADC = Analog-to-digital converter
VCXO = Voltage-controlled crystal oscillator
SD = Sigma-Delta
CSI = Channel state information
Microprocessor
Interface
Bit
Deintlv.
To
Output FEC
Interface.
2-3
2.2 Analog-to-Digital Converter (ADC)
Features of the L64780 analog-to-digital converter include:
•
low-IF center frequency input: 4.57 MHz
•
input bandwidth: 8 MHz
•
sampling clock: 18.29 MHz
•
resolution: 8-bit
The L64780 also offers a 10-bit parallel port for connection to an
external, 10-bit ADC.
2.3 Automatic Gain Control (AGC)
The Tuner AGC Amplifier amplifies the signal. The resulting signal has
an RMS value of σ 0 . The AGC amplifies this signal so that its variance
allows the FFT to work properly. To do this, the input signal power must
be 10.95 dB down on the maximum ADC input range, normalized to 1.0.
This means the RMS value of the input to the L64780 is: σ 0 = 0.283 .
2.3.1 AGC Target RMS Value σ T
Figure 2.2 defines The nine-bit AGC_TARGET register.
Figure 2.2
Structure of 9-Bit AGC_TARGET Register
AGC_TARGET_MSB[5:0]
b8
2
-1
b7
2
-2
AGC_TARGET_LSB[5:0]
b6
b5
b4
-3
-4
-5
2
2
2
b3
2
-6
b2
2
-7
b1
2
-8
b0
2
-9
For the FFT to perform correctly, the input level of the COFDM signal
must be 10.95 dB down on the normalized 1.0 Input Range. Thus, the
target RMS value, σ, of the input signal must be 0.283, as shown in
Equation 2.1.
Equation 2.1
2-4
σT =
Architectural Overview
2
512 --- ⋅ σ
π
Since the recommended RMS value is σ = 0.283, the recommended σ T
value is σ = 0.226, resulting in an AGC_TARGET initial value of 0x74
(0b0111.0100). Thus:
•
AGC_TARGET_LSB = 0x4 (0b100)
•
AGC_TARGET_MSB = 0x0E (0b01110)
Also see the description in Section 4.4.4, “Address Line 0x0A,”
page 4-23.
2.3.2 AGC External Loop Filter
The input power control signal drives the Sigma Delta modulated output,
AGCOUT. Use the AGCOUT signal to drive an external passive RC filter
that feeds the gain control stage, as shown in Figure 2.3.
Figure 2.3
AGC Loop Pass Filter
5V
R= 5.6 kΩ
RAGC= 56 kΩ
AGCOUT
CAGC= 10 nF
The R and C values for the low-pass filter must meet the following
requirement:
Equation 2.2
RAGC • CAGC = 560 µs
See Figure 2.3 for the recommended values.
Automatic Gain Control (AGC)
2-5
2.3.3 AGC Loop Gain Ks
The gain of the loop, Ks, must obey the following rule:
–5
Equation 2.3
8.5 × 10
K s = -------------------------F ⋅ σT
where:
•
F is the slope of the tuner AGC characteristics in dB/V.
•
σ T is the target value for the input signal.
With an RMS value of σ = 0.283 , and a tuner characteristic of 50 dB/V,
the loop gain is:
Equation 2.4
K s = 7.5 × 10
–6
To code Ks, LSI Logic uses an approximation to the nearest power of 2.
LSI Logic uses the AGC_GAIN[2:0] register, with the following
correspondence:
Equation 2.5
Ks ≈ 2
– 8 – 2 ⋅ AGC_GAIN
Because the number of values AGC_GAIN can have is limited, so are
those of Ks. Thus,
Equation 2.6
log K s
AGC_GAIN ≈ --------------- – 4
2 log 2
In our example, AGC_GAIN = 4 is the most appropriate value, giving a
value of:
Equation 2.7
K s ≈ 1.52 × 10
–5
The real-to-complex block takes the input samples from the ADC output
and converts them into a complex baseband representation for input to
the FFT block.
2-6
Architectural Overview
2.4 Real-to-Complex Conversion
The DVB-T signal occupies a bandwidth of approximately 7.61 MHz; the
signal is symmetrically disposed in extent about a notional center carrier.
As radiated, this normally lies in the UHF range; however, its spectrum
is not symmetrical, because its upper and lower sidebands are different
(a double-sideband modulated signal does have a symmetrical
spectrum). Thus, a complex representation is needed to describe it at
baseband. This spectrum can be derived using the in-phase I and
quadrature-phase Q demodulators, but each would have to be sampled
separately, using two ADCs and many well-matched components.
The L64780 chip avoids the complexity and expensive matching of
analog components. It uses a single ADC, and derives the complexbaseband representation by internal digital processing. The ADC
samples the DVB-T signal at a low IF, then the real-to-complex block
digitally shifts the samples to complex baseband form, centered on zero
frequency. It is fundamental to the operation of this conversion
processing that the nominal center frequency (fLIF) of the low IF is related
to the sampling frequency, fCLK18, used by the ADC (see Table 2.1, which
shows that fCLK18 = 4 fLIF almost exactly). The AFC circuitry of the
L64780 ensures that this is the case. The output of the block is complex
numbers at the rate of fCLK18/2.
The frequencies in Table 2.1 apply for the normal version of the DVB-T
specification for use with UHF channels spaced by 8 MHz. To adopt the
DVB-T specification for use with 7 MHz or 6 MHz channel spacing, scale
the clock frequency and all other frequencies within the system (including
the bit-rate capacity and low IF) by factors of 7/8 and 6/8, respectively.
Table 2.1
Approximate and Exact Frequencies for Real to Complex Conversion
Symbol
Approx. Frequency, MHz Exact Frequency, MHz
ADC sampling frequency
fCLK18
18.28
128/7
Low-IF center frequency
fLIF
4.57
32/7
Real-to-Complex Conversion
2-7
2.5 Fast Fourier Transform (FFT) Block
The FFT block converts from the temporal to the frequency domain
representation. It has the following modes of operation:
•
FFT and Inverse FFT
•
2 k (2048 points) and 8 k (8192 points) mode
2.6 Time Synchronization
This block finds the optimum timing for the start of the FFT window, and
synchronizes the frequency of the clock, fCLK18, to the received signal
The options for the duration of the symbol and the duration of the guard
interval are given in paragraph 4.4 of the DVB-T/ETSI Specification.
The block takes the sequence of complex numbers from the real-tocomplex conversion block and, to synchronize the clock, produces a
control signal for the voltage-controlled oscillator. The control voltage of
the VCXO is converted into a Sigma-Delta (Σ/∆) Modulated signal and
output as a single wire signal. This signal requires external low-pass
filtering to extract its mean value, which represents the control voltage of
the oscillator.
The transmitter repeats a segment of the signal during the guard interval.
This block detects the repeated portion of the signal. The signal
processing resists impairment from high levels of echoes or interference.
2.6.1 Timing Loop Gain
In 2 k mode, the optimal IIRGAIN is 0b01, or α ≈ 3.125 × 10
–2
This leads to KI and KP values of:
Equation 2.8
1.69
K I = -----------------K VCXO
K P = 512 × K I
In 8 k mode, the optimal IIRGAIN is 0b11, or α ≈ 7.8 × 10
2-8
Architectural Overview
–3
.
.
This leads to KI and KP values equal to:
0.1
K I = -----------------K VCXO
Equation 2.9
K P = 512 × K I
2.6.2 TIM_CLK_INIT Register Definition
The TIM_CLK_INIT register is defined as a two’s complement 15-bit
register that has the following meaning:
5K VCXO × TIM_CLK_INIT
W i = W 0 + ------------------------------------------------------------------15
2
Equation 2.10
where W0 is the central frequency of the VCXO.
2.6.3 TIM External Loop Filter
The control voltage signal of the VCXO drives the Sigma Delta
modulated output, VCXOUT. Use the VCXOUT to drive an external
passive RC filter that feeds the timing clock control stage. See
Figure 2.4.
Figure 2.4
External Low-Pass Loop Filter
5V
R= 1 kΩ
RTIM= 10 kΩ
VCXOUT
CTIM= 75 nF
The −3 dB cutoff frequency of this system is f0 = 212 Hz, giving an
estimate of the TIM Loop Bandwidth and resulting in a low-pass filter
time constant T1 = RC = 750 µs.
The R and C values for the low-pass filter must meet the following
requirement: RTIM • CTIM = 750 µs.
Time Synchronization
2-9
2.7 Automatic Frequency Control (AFC)
The two methods for applying the correction required to achieve
frequency synchronization are analog and digital. The method used
depends on the design of the analog tuner. The L64780 allows both
options, which are described in the following subsections.
2.7.1 Analog Frequency Synchronization
This block adjusts the frequency of the local oscillator in the tuner so that
the center frequency of the low IF is equal to its nominal value of fLIF.
The adjustment must be accurate to within a small fraction of the carrier
spacing, so that intercarrier interference is kept to an acceptably low level
and the tracking ability of the channel estimation is not absorbed in
correcting for the error in the frequency of the local oscillator.
The block takes the sequence of complex numbers from the output of the
FFT block and produces a control signal for the local oscillator. This
control signal is delivered as a single-wire Sigma-Delta (Σ/∆) signal.
The initial error in the frequency of the local oscillator can be several
times the carrier spacing; the measurement of the frequency error relies
on the continual pilot carriers. The measurement range is ± 51.7 kHz in
the 8k mode and ± 143 kHz in the 2k mode. The oscillator control signal
is derived from the measured frequency error.
The value of the control signal can also be read and initialized through
the microprocessor interface, which allows a previously stored value to
be used when a channel is selected, making acquisition faster.
2.7.2 Digital Frequency Synchronization
This block uses digital signal processing (DSP) to correct for the
tolerance in the frequency of the local oscillator in the tuner. The DSP
shifts the frequency of the complex baseband signal so that its center
frequency is zero. The shift needs to be accurate to within a small
fraction of the carrier spacing so that intercarrier interference is kept to
an acceptably low level and so the tracking ability of the channel
estimation is not absorbed in correcting for the error in the frequency of
the local oscillator.
2-10
Architectural Overview
The block takes the sequence of complex numbers from the output of the
FFT block and produces a numerical control signal. It also takes the
sequence of complex numbers from the real-to-complex conversion block
and applies the frequency shift to the numbers according to the
numerical control signal. Then, it passes the data on to the FFT block.
The digital frequency synchronization block comprises two parts: one to
shift the frequency of the complex baseband signal, and one to measure
the error in the center frequency of the complex baseband signal as
presented to the FFT block.
Multiplying the signal by a rotating vector shifts the frequency of the
complex baseband signal. A number-controlled oscillator (NCO) with sine
and cosine outputs generates the rotating vector. The frequency range
of the NCO is ± 143 kHz.
The error in the frequency of the local oscillator translates directly into
an error in the center frequency of the complex baseband signal. The
range of measurement is ± 51.7 kHz in the 8 k mode, and ± 143 kHz in
the 2 k mode. The numerical control signal is derived from the measured
frequency error.
Use the microprocessor interface to read and initialize the value of the
control signal. This allows a previously stored value to be used when a
channel is selected, thus making acquisition faster.
2.7.3 AFC Loop Gain
In digital AFC mode, the optimal sensitivity (KSENS) is when the
AFC_SENSITIVITY field in the Parameter Registers (see page 4-18) is
set to 0b110:
Equation 2.11
K SENS ≈ 1.56 × 10
–2
In analog AFC mode, the optimal AFC_SENSITIVITY is defined as:
Equation 2.12
74.4
K SENS = ----------------K VCXO
Automatic Frequency Control (AFC)
2-11
2.7.4 AFC_INIT_FREQ Register Definition
In AFC digital loop mode, the AFC_INIT_FREQ register is defined as a
two’s complement 24-bit register with the following usage:
 143 × 10 3

W i = W 0 +  ------------------------× AFC_INIT_FREQ
23


2
Equation 2.13
where W0 is the central frequency of the VCXO.
In AFC analog loop mode, the AFC_INIT_FREQ register is defined as a
two’s complement 24-bit register and in the L64780 has the following
usage:
 5K vcxo

× AFC_INIT_FREQ
W i = W 0 +  -----------------20
 2

Equation 2.14
where W0 is the frequency of the VCXO.
2.7.5 AFC External Loop Filter
The control signal of the frequency loop drives the Sigma-Delta
modulated output AFCOUT. Use the AFCOUT signal to drive an external
passive RC filter that feeds the timing clock control stage, as shown in
Figure 2.5.
Figure 2.5
AFC Loop Pass Filter
5V
R= 10 kΩ
RAFC = 100 kΩ
AFCOUT
CAFC = 3.3 nF
The −3 dB cutoff frequency of this circuit is f0 = 482 Hz, giving a rough
estimate of the Frequency Loop Bandwidth and resulting in a low-pass
filter time constant:
Equation 2.15
2-12
T 1 = RC = 300 µs
Architectural Overview
The R and C values for the low-pass filter must meet the requirement
shown in Equation 2.16:
Equation 2.16
R AFC ⋅ C AFC = 330 µs
2.8 TPS Decoding and Frame Synchronization
This block takes the sequence of complex numbers from the output of
the FFT block and recovers the Transmission Parameter Signalling (TPS)
data defined in paragraph 4.6 of the DVB-T/ETSI specification. The block
passes the resulting data to the control logic of the L64780; it thus
configures the mode of operation of much of the demodulator’s circuitry.
The TPS data contains information on:
•
The modulation system
•
Whether the transmission is hierarchical
•
What the value of α is (if the transmission is hierarchical)
•
The inner code rate(s)
•
The guard interval
•
The mode: 2 k or 8 k
The guard interval and mode interaction cannot be used for acquisition,
but assist the receiver in handling a reconfiguration of the transmission.
By implication, the TPS also indicates the phase of the four-symbol
sequence of insertion of scattered pilots.
The TPS Decoder extracts the data bits from the TPS carriers and
retains the most recent 67 bits. The decoder detects the start of the
frame and carries out the Bose-Chaudhuri-Hocque (BCH) error check on
the block of 67 bits, so that data containing errors can be discarded. All
the data in the list above are passed to the control logic along with two
flags: one indicates the start of a frame; the other indicates whether the
error check detects errors. If there were no errors, the control logic uses
the data to configure the demodulator, discarding any previous settings.
The settings can be read and initialized through the microprocessor
interface, which allows previously stored settings to be used when a
channel is selected, making acquisition faster.
TPS Decoding and Frame Synchronization
2-13
2.9 Mode Control Logic
If previously stored mode data are available, they are used when a
channel is selected or when the signal strength rises after a period of
signal loss. This is done by the means of an external microprocessor and
makes acquisition faster. When the Mode Control Logic becomes an
error-free TPS block, mode data from that TPS block replaces any
previously determined mode data.
In this context, the mode data consists of:
•
2 k or 8 k mode
•
Length of the guard interval
•
Modulation system
•
Hierarchy information
•
Inner code rate
The mode control logic configures all the demodulator blocks whose
operation is affected by these parameters. Acquisition of the demodulator
is outlined in the following steps:
1. Achieve full synchronization of the FFT start and the clock frequency.
2. Make coarse and fine automatic frequency control (AFC) corrections,
and achieve frequency synchronization.
3. Equalize the channel frequency response, once the Symbol Number
is zero.
4. Wait up to one frame for the start of a TPS block, and wait another
frame for the complete TPS block to be received. There is a wait of
one or more additional frames, if necessary, until a TPS block is
received without errors.
5. The modulation system, hierarchy information, and code rate from
the TPS data are used to configure the Viterbi metric assignment
block, and, by means of the microprocessor interface, the external
Viterbi decoder(s).
2-14
Architectural Overview
2.10 Channel Estimation and Equalization
The output from the FFT block is a sequence of complex numbers, each
describing the signal received on one of the COFDM carriers. The
numbers correspond to the values, chosen from the points of the current
constellation, which were used to modulate each carrier at the modulator.
However, each carrier is received with unknown amplitude and phase
due to the combined effects of:
•
The channel through which the RF signal has passed (which, in
general, is frequency selective)
•
Any minor error in the FFT timing window
The purpose of the channel estimation and equalization block is to
correct these effects so that the complex numbers at its output would, if
plotted on an Argand diagram, correspond to points of the transmitted
constellation (for example, QPSK, 16 QAM, or 64 QAM) except for any
superimposed noise or interference.
The transmitted DVB-T signal contains “scattered pilots,” which are
distributed among the data cells in a regular pattern (see Figure 2.6).
These are transmitted with known values: the imaginary part is always
zero, while the real part has a fixed amplitude. The sign of the real part,
however, is determined by the carrier number (according to a pseudorandom function that also is used in a similar way to determine the real
part of continual pilots).
Figure 2.6
Scattered Pilot Structure
Kmin= 0
Kmax= 1704 if 2K
Kmax= 6816 if 8K
Symbol 67
Symbol 0
Symbol 1
Symbol 2
Symbol 3
The Channel Estimation and Equalization Block compares each received
scattered-pilot cell with the known transmitted value (derived from a
Channel Estimation and Equalization
2-15
PRBS generator) to obtain a snapshot of the response of the “channel”
(including any timing uncertainty) for the corresponding carrier at that
time instant.
The data cells that must be corrected lie between the scattered pilots, in
both frequency and time. This allows for appropriately generated
corrections for each data cell by using a suitable form of interpolation
applied to the measured values of the scattered pilots. As well as
obtaining “in-between” values of the channel response, the interpolator
also slightly reduces the effects of thermal noise on the scattered-pilot
measurements. The reduction in noise and the fact that scattered pilots
are transmitted with a power approximately 2.5 dB greater than data
cells, keeps the inevitable loss of performance due to scattered-pilot
noise within acceptable bounds.
2.11 Viterbi Metric Assignment and Quantization
This block takes in the sequence of complex numbers, each describing
the signal received on one of the COFDM carriers, after equalization.
These are the received versions of the complex numbers chosen at the
modulator from the points of the current constellation, according to the
coded bits to be sent. This block forms Viterbi metrics (“soft decisions”)
for each of the received bits. These metrics are quantized and passed
on, after reordering in the deinterleaver stages, to the associated Viterbi
convolutional decoder. The use of “soft” rather than “hard” decisions is
vital to obtaining the rugged properties of COFDM.
The associated Viterbi convolutional decoder, which resides on a
separate chip (for example, the LSI Logic L64724), is capable of
accepting soft decisions that are quantized to either three or four bits.
Three bits are required for acceptable performance, while four bits
improve the performance for higher-order modulation options of the DVBT specification, especially with non-uniform constellations. Decoder chips
designed primarily for QPSK or BPSK modulation commonly use three
bits because the advantage of using four bits is minimal.
The L64780 chip provides 4-bit soft decisions, but it also can be used to
drive 3-bit decoders.
2-16
Architectural Overview
2.12 Symbol Deinterleaver
From each received constellation point, the Viterbi metric assignment
block extracts up to six soft decisions. The symbol deinterleaver accepts
one COFDM symbol containing soft decisions and reorders them
according to an algorithm defined in the DVB-T specification. It then
passes this reordered data to the bit deinterleaver.
Echoes cause minima (“holes”) in the received spectrum, leading to
groups of carriers on which the data is unreliable. For optimum operation
of the Viterbi decoder, these groups of unreliable carriers must be split
up. The symbol deinterleaver fulfills part of this function; the remainder
is done by the bit deinterleaver.
In 2 k mode, there are 1705 COFDM carriers, of which 1512 in each
symbol carry data. Each of these carriers yields either 2 (QPSK), 4 (16
QAM), or 6 (64 QAM) soft decisions. Each of these soft decisions
consists of four bits of information. The effect of the operation of the
symbol deinterleaver is to write the possible 1512 24-bit words into a
RAM using one address sequence, and to read them using a different
address sequence. This means there is a delay of one COFDM symbol
between the input and the output. In the 8 k case, there are 6048 (out
of a total of 6817) COFDM carriers that convey data; thus, the L64780
provides a 6048 by 24-bit RAM.
2.13 Bit Deinterleaver
In the presence of multipath or interference, some COFDM carriers
convey data less ruggedly than others. Each COFDM carrier supplies
either two, four, or six soft decisions; these would be impaired if the
carrier they came from were impaired. For optimum operation of the
Viterbi decoder, it is best if groups of unreliable soft decisions are
maximally spaced. The purpose of the bit deinterleaver is to split up
unreliable soft decisions caused by a single unreliable COFDM carrier.
The symbol deinterleaver separates groups of unreliable COFDM
carriers.
The bit deinterleaver accepts groups of 3-bit or 4-bit soft decisions
generated from the same COFDM carrier from the symbol deinterleaver.
Symbol Deinterleaver
2-17
The bit deinterleaver rearranges these groups of soft decisions to
separate soft decisions generated from the same carrier. The bit
deinterleaver passes these soft decisions to the output interface of the
L64780 for external decoding.
There are 6-bit deinterleavers, I0 to I5. For QPSK, one COFDM carrier
provides two soft decisions: one from the real part, and one from the
imaginary part. I0 deinterleaves the soft decision extracted from the real
part; I1 deinterleaves the soft decision from the imaginary part. In this
case, I2 to I5 are not used.
For 16 QAM (both hierarchical and nonhierarchical), one COFDM carrier
provides four soft decisions: two from the real part, and two from the
imaginary part. Ten deinterleaves the MSB soft decision extracted from
the real part; I1 deinterleaves the MSB from the imaginary part. I2
deinterleaves the LSB from the real part; I3 deinterleaves the LSB from
the imaginary part. In this case, I4 and I5 are not used.
For 64 QAM (both hierarchical and nonhierarchical), one COFDM carrier
provides six soft decisions: three from the real part, three from the
imaginary part. I0 deinterleaves the MSB soft decision extracted from the
real part; I1 deinterleaves the MSB from the imaginary part. I2
deinterleaves the CSB from the real part; I3 deinterleaves the CSB from
the imaginary part. I4 deinterleaves the LSB from the real part; I5
deinterleaves the LSB from the imaginary part.
2-18
Architectural Overview
Chapter 3
Interfaces
This chapter describes the interfaces for the LSI Logic L64780 DVB-T
COFDM Demodulator. It consists of the following sections:
•
Section 3.1, “Output Interface,” page 3-1
•
Section 3.2, “MUXIN Interface,” page 3-8
•
Section 3.3, “MUXOUT Interface,” page 3-13
•
Section 3.4, “Microprocessor Interface,” page 3-16
3.1 Output Interface
The output interface formats the soft decisions for presentation to the
downstream Viterbi decoder. The input to this block is a stream of fourbit or 3-bit Viterbi soft decisions from the inner bit deinterleaver. The
output from this block connects to a Viterbi decoder that is external to
the L64780. The output from soft decisions is in a format suitable for
direct connection to the L64724 or L64705.
This block operates differently in nonhierarchical and hierarchical modes,
and can have a serial or parallel output format. This block’s operational
modes are described in the following subsections.
3.1.1 Output Format in Nonhierarchical Mode
In nonhierarchical mode, the output format can be serial or parallel.
L64780 DVB-T OFDM Demodulator
3-1
3.1.1.1 Serial Output Format
In serial output mode, the output port of the L64780 is configured as
shown in Figure 3.1.
Figure 3.1
Output Interface in Nonhierarchical and Serial Modes
4
4
L64780
SD0
DVOUT
SD1 (not used *)
DVOUT_LP (not used*)
CLKOUT54
* When not used, the signal is deasserted LOW.
The output interface passes 4-bit or 3-bit soft decisions to the Viterbi
decoder through the SD0 signal accompanied by the assertion of
DVOUT. All outputs from the output interface are clocked at 54 MHz by
CLKOUT54.
With a 64 QAM constellation, the L64780 extracts six soft decisions from
every constellation point at 9 MHz; for example, one soft decision is
presented every 54 MHz clock cycle. See Figure 3.2.
Figure 3.2
Nonhierarchical, Serial Mode, 64 QAM Constellation
CLKOUT54
SD0[3:0]
SD00 SD01
SD02
SD03
SD04 SD05
SD06
SD07
SD08
SD09 SD010
DVOUT
Every time a set of soft decisions is received from the bit deinterleaver,
the DVOUT signal stays asserted for six 54 MHz clock cycles. The
DVOUT signal is deasserted only during the scattered pilots, unused
carriers, or guard interval.
3-2
Interfaces
For a 16 QAM constellation, during which four soft decisions are
extracted every 9 MHz, the DVOUT signal stays asserted over four out
of six 54 MHz clock cycles. See Figure 3.3.
Figure 3.3
Nonhierarchical, Serial Mode, 16 QAM Constellation
CLKOUT54
SD0[3:0]
SD00
SD01
SD02
SD03
SD04
SD05
SD06
SD07
DVOUT
For the QPSK constellation, only two soft decisions are extracted every
9 MHz, resulting in DVOUT being asserted over two out of six 54 MHz
clock cycles. See Figure 3.4.
Figure 3.4
Nonhierarchical, Serial Mode, QPSK Constellation
CLKOUT54
SD0[3:0]
SD00
SD01
SD02
SD03
DVOUT
3.1.1.2 Parallel Output Format
In this mode, soft decisions are output in parallel, and the output
interface of the L64780 is configured. See Figure 3.5.
Figure 3.5
Output Interface in Nonhierarchical and Parallel Modes
4
L64780
4
SD0
DVOUT
SD1
DVOUT_LP (not used*)
CLKOUT54
* When not used, the signal is deasserted LOW.
The output interface passes two soft decisions to the Viterbi decoder in
parallel through SD0 and SD1, accompanied by a data valid indicator.
Output Interface
3-3
Because soft decisions are presented in parallel in 64 QAM, the soft
decisions are presented in three consecutive 54 MHz clock cycles over
a six 54 MHz clock cycle period (Figure 3.6). The DVOUT signal is
deasserted during the scattered pilots, unused carriers, and guard
interval.
Figure 3.6
Nonhierarchical, Parallel Mode, 64 QAM Constellation
CLKOUT54
SD0[3:0]
SD00
SD01
SD02
SD03
SD04 SD05
SD1[3:0]
SD10
SD11
SD12
SD13
SD14
SD15
DVOUT
When a 16 QAM constellation is used, DVOUT is asserted for two
54 MHz clock cycles in six clock cycles (Figure 3.7). When QPSK is
used, it is asserted for only one out of six clock cycles (Figure 3.8).
Figure 3.7
Nonhierarchical, Parallel Mode, 16 QAM Constellation
CLKOUT54
SD0[3:0]
SD00
SD01
SD02
SD03
SD1[3:0]
SD10
SD11
SD12
SD13
DVOUT
Figure 3.8
Nonhierarchical, Parallel Mode, QPSK Constellation
CLKOUT54
SD0[3:0]
SD00
SD01
SD1[3:0]
SD10
SD11
DVOUT
3-4
Interfaces
3.1.2 Output Format in Hierarchical Mode
The following subsections describe the decoding of High-Priority and
Low-Priority data streams in hierarchical mode.
3.1.2.1 Decoding of HP and LP Streams
In hierarchical mode, the output port of the L64780 is configured
(Figure 3.9). The High- and Low-Priority streams are delivered on SD0
and SD1, respectively. DVOUT validates the High-Priority data stream;
DVOUT_LP validates the Low-Priority data stream.
Figure 3.9
Output Interface in Hierarchical and Two FECs Modes
4
L64780
4
SD0 (High-Priority Stream)
DVOUT
SD1 (Low-Priority Stream)
DVOUT_LP
CLKOUT54
When in 16 QAM mode, two soft decisions are transmitted on SD0 and
SD1. DVOUT and DVOUT_LP stay asserted for two of six 54 MHz clock
cycles. See Figure 3.10.
Figure 3.10 Hierarchical, Two FEC Decoders, 16 QAM Constellation
CLKOUT54
SD0[3:0]
SD00 SD01
SD02 SD03
SD1[3:0]
SD10 SD11
SD12 SD13
DVOUT
DVOUT_LP
Output Interface
3-5
When in 64 QAM mode, two soft decisions are transmitted on SD0 and
four soft decisions are transmitted on SD1. The DVOUT signal stays
asserted during two 540 MHz clock cycles over six 54 MHz clock cycles
and the DVOUT_LP signal stays asserted for four of six 54 MHz clock
cycles. See Figure 3.11.
Figure 3.11 Hierarchical, Two FEC Decoders, 64 QAM Constellation
CLKOUT54
SD0[3:0]
SD00 SD01
SD02
SD03
SD14
SD15
DVOUT
SD1[3:0]
SD10
SD11
SD12 SD13
SD16 SD17
DVOUT_LP
3.1.2.2 Decoding Only One Stream (HP or LP)
In this mode, the output port of the L64780 is configured (Figure 3.12).
The DOF_HPLP signal selects between the HP and LP output streams.
The data stream in this output format is the same as for the
nonhierarchical case.
Figure 3.12 Output Interface in Hierarchical and One FEC Mode
4
L64780
4
SD0 (HP/LP Stream)
DVOUT
SD1 (not used *)
DVOUT_LP (not used*)
CLKOUT54
* When not used, the signal is deasserted LOW.
3-6
Interfaces
When a set of soft decisions is received from the Bit Deinterleaver block
in 16 QAM (HP or LP selected) or in 64 QAM (only HP selected), two
soft decisions are transmitted over SD0. The result is that DVOUT is
asserted for two of six 54 MHz clock cycles. See Figure 3.13.
Figure 3.13 Hierarchical, One FEC Decoder Mode With 16 QAM (HP or LP Selected) or
64 QAM (LP Selected only)
CLKOUT54
SD0[3:0]
SD00
SD01
SD02
SD03
DVOUT
When a set of soft decisions is received from the Bit Deinterleaver block,
and the DOF function is configured in 64 QAM with the LP data stream
selected, four consecutive soft decisions must be transmitted over SD0.
Thus, DVALIDOUT is asserted for four of six 54 MHz clock cycles.
See Figure 3.14.
Figure 3.14 Hierarchical, One FEC Decoder Mode With 64 QAM (HP Selected Only)
\
CLKOUT54
SD0[3:0]
SD00 SD01 SD02
SD03
SD04
SD05
SD06
SD07
DVOUT
Output Interface
3-7
3.2 MUXIN Interface
The MUXIN bus lets you enter data (or test vectors) into the device at
specific locations, which lets you bypass some front functional blocks and
test an internal functional block.
Important:
This interface is used for LSI Logic internal testing and is
not intended for use in customer production receivers.
The MUXIN bus (MUXINBUS) is a 27-bit wide bus, multiplexed with the
bypass ADC bus (DIGADCIN[9:0]). Table 3.1 shows the bus mapping.
Table 3.1
MUXINBUS Mapping
MUXINBUS[26:10]
MUXINBUS[9:0]
MUXIN[16:0]
DIGADCIN[9:0]
Clocking data into the chip is very simple because the L64780 offers a
clock output (CLKMUXIN) that automatically has the correct phase and
frequency. CLKMUXIN automatically selects the correct internal clock,
depending on the block selected. Figure 3.15 shows how to connect
external logic that brings the data to the MUXINBUS.
Figure 3.15 MUXIN Signals Interface
CLK
TEST_VECTOR
DATA GENERATOR
3-8
Interfaces
CLKMUXIN
27
MUXINBUS[26:0]
L64780
The MUXINBUS is software controlled and provides six testing
possibilities. The control word is MUXIN_select[2:0], located at address
0x15, mapped on bits 3 to 5. Table 3.2 defines the MUXIN_select[2:0]
word.
Table 3.2
MUXIN Conifguration
MUXIN_select[2:0]
Definition
0
Normal mode
1
Access to Timing and DDFS block
2
Access to AFC block
3
Access to FFT block
4
Access to CSI block
5
Input to SDI block
6
Reserved
7
Reserved
MUXIN Interface
3-9
3.2.1 Access to Timing and DDFS Blocks
When selecting access to the Timing and DDFS blocks, the CLKMUXIN
signal is configured as an 18 MHz clock (more precisely, four times the
low IF). The DDFS block is the digital rotator that performs the carrier
frequency compensation.
The signals on the bus are I and Q data (in two’s complement format),
a start pulse (START), and a data valid signal (DV). These signals are
mapped on the MUXINBUS. See Figure 3.16.
Figure 3.16 Timing and DDFS Input Mapping
26
0
25
24 23
START DV
21 20
11 10 9
0
Q[9:0]
0
0
I[9:0]
In this mode, you can select whether the start pulse comes from the
MUXINBUS or from the Timing recovery unit. The start pulse delimits
every COFDM symbol. This selection is done through the DDFS_MODE
bit (address 0x9, bit 1). If DDFS_MODE = 0, the start pulse comes from
the test bus (test mode); otherwise, the Timing block delivers the start
pulse. Note that this mode could correspond to an external downconverter that feeds the I and Q data directly into the Timing and DFFS
blocks.
3.2.2 Access to the AFC Block
The AFC block performs the estimation of the carrier frequency drift and
produces an analog or digital feedback control signal to compensate for
this drift. In this mode, the CLKMUXIN signal is configured as a 36 MHz
clock (more precisely, eight times the low IF).
The signals on the bus are I and Q data (in two’s complement format),
a start pulse (START), a data valid (DV) signal, and the COFDM symbol
number (S_NB). These signals are mapped on the MUXINBUS.
See Figure 3.17.
Figure 3.17 AFC Input Mapping
26
25
24
0
START
DV
3-10
23
22
S_NB
Interfaces
21
0
20
11
Q[9:0]
10
0
9
0
I[9:0]
In this mode, you can select whether the COFDM symbol number comes
from the TPS informations (Frame Number) or from the MUXINBUS
(S_NB). This selection is done through the AFC_MODE bit (address 0x5,
bit 6). If AFC_MODE = 0, the COFDM symbol number comes from the
MUXINBUS (S_NB) or full MUXIN mode; otherwise, it comes from the
TPS register (partial MUXIN mode).
3.2.3 Access to the FFT Block
In this mode, the CLKMUXIN signal is configured as a 36 MHz clock
(more precisely, eight times the low IF).
The signals on the bus are I and Q data (in two’s complement format)
and a start pulse (START). These signals are mapped on the
MUXINBUS. See Figure 3.18.
Figure 3.18 FFT Input Mapping
26
25
24
0
START
21
20
0
11 10 9
Q[9:0]
0
0
I[9:0]
In this mode, the L64780 can be used as a stand-alone FFT processor
in forward mode (FFT_DIR = 0) or in inverse mode (FFT_DIR = 1). The
FFT_DIR register is located at address 0x11, bit 2.
3.2.4 Access to the CSI Block
The CSI block performs the Channel State Information (CSI) processing,
which builds the soft decisions for the Viterbi decoder using a priori
information from the Channel Equalizer (CE). In this mode, CLKMUXIN
is configured as an 18 MHz clock (more precisely: four times the low IF).
The signals on the bus are I and Q data (in twos complement format), a
start pulse (START), a data valid (DV) signal, the COFDM symbol
number (S_NB), and a marker (or data valid) on scattered pilots (DVSP).
These signals are mapped on the MUXINBUS. See Figure 3.19.
Figure 3.19 CSI Input Mapping
26
DVSP
25
24 23 22 21
START DV S_NB
MUXIN Interface
11 10
Q[10:0]
0
I[10:0]
3-11
3.2.5 Access to the SDI Block
The SDI block performs Symbol Deinterleaving (SDI) as specified in the
ETSI specification. In this mode, the CLKMUXIN signal is configured as
an 18 MHz clock (more precisely, four times the low IF).
The signals on the 24-bit data bus (D) contain up to six soft decisions,
up to four bits per soft decision, a start pulse (START), a data valid (DV)
signal, and the symbol parity (S_P). An odd symbol number is marked
by S_P = 1; even symbol numbers are marked by S_P = 0. These
signals are mapped on the MUXINBUS. See Figure 3.20.
Figure 3.20 SDI Input Mappings
26
25
24 23
0
S_P START DV
D[23:0]
The data bus (D) is mapped in 3-bit and 4-bit soft decision modes, as
shown in Figure 3.21 and Figure 3.22, respectively. The MSB is at the
highest weight position. Note that X means reserved.
Figure 3.21 D[23:0] Bus Mapping in Three-Bit Soft Decision
23
21
QSPK I
20
X
19
17
QPSK Q
16
X
15
13
16 QAM I
12
11
9
8
7
5
4
3
1
0
X
16 QAM Q
X
64 QAM I
X
64 QAM Q
X
7
4
3
0
Figure 3.22 D[23:0] Bus Mapping in Four-Bit Soft Decision
23
20
QSPK I
3-12
19
16
QPSK Q
Interfaces
15
12
16 QAM I
11
8
16 QAM Q
64 QAM I
64 QAM Q
3.3 MUXOUT Interface
The MUXOUT bus lets you probe any point in the device while receiving
a transport stream (TS).
Important:
This interface is used for LSI Logic internal test purposes
and is not intended for customer production receivers.
MUXOUTBUS is 27 bits wide. For each probed point, data and control
signals are available on this bus (including the clock). The clock has the
same aspect ratio as CLKMUXIN; it is not a 50% duty cycle type.
Software controls the MUXOUTBUS, which provides five test
possibilities. The control word is MUXOUT_select[2:0], located at
address 0x15 (bits 2 to 0). Table 3.3 define the MUXOUT_select word.
Table 3.3
MUXOUT_select Word Definition
MUXIN_select[2:0]
Definition
0
DDFS output
2
AFC output
3
CE output
4
CSI output
5
ADC output
6
Reserved
7
Reserved
Note that the MUXOUT bus can be 3-stated by asserting the
MUX_CTRL bit (bit 3 of the Mode Register Address Line), at address
0x19. The bus is active when MUX_CTRL is set to 0.
MUXOUT Interface
3-13
3.3.1 DDFS Output
The DDFS output lets you probe signals after carrier frequency
compensation and prior to FFT processing. The signals are I and Q data
(in two’s complement format), a start pulse that delimits the COFDM
symbols (START), a data valid (DV) signal that accompanies valid data,
and an 18 MHz clock. These signals are mapped on the MUXOUTBUS.
See Figure 3.23.
Figure 3.23 DDFS Output Mapping
26
25
24 23 22 21
18 MHz CLK START DV
12 11 10 9
0
Q[9:0]
0
0
I[9:0]
3.3.2 FFT Output
The FFT output lets you probe data prior to Common Phase Error (CPE)
correction and Channel Equalization (CE). The signals are I and Q data
(in two’s complement format), a start pulse that delimits the COFDM
symbols (START), a data valid (DV) signal that accompanies valid data,
and a 36 MHz clock. These signals are mapped on the MUXOUTBUS.
See Figure 3.24.
Figure 3.24 FFT Output Mapping
26
25
24 23 22 21
36 MHz CLK START DV
12 11 10 9
0
Q[9:0]
0
0
I[9:0]
3.3.3 AFC Output
The AFC output lets you probe data after Common Phase Error (CPE)
correction and prior to Channel Equalization (CE). The signals are I and
Q data (in two’s complement format), a start pulse that delimits the
COFDM symbols (START), a data valid (DV) signal that accompanies
valid data, and a 36 MHz clock. These signals are mapped on the
MUXOUTBUS. See Figure 3.25.
Figure 3.25 AFC Output Mappings
26
25
24 23
36 MHz CLK START DV
3-14
Interfaces
12 11
Q[11:0]
0
I[11:0]
3.3.4 Channel Equalizer (CE) Output
The Channel Equalizer (CE) output lets you probe data after channel
equalization or the frequency response of the channel. After channel
equalization, you can display the constellation by feeding I and Q data
into two DACs. For constellation display purposes, the DACs require only
8-bit resolution.
The signals at this point are I and Q data in two’s complement format, a
start pulse that delimits the COFDM symbols (START), a data valid (DV)
signal that accompanies valid data, and a 36 MHz clock. These signals
are mapped on the MUXOUTBUS. See Figure 3.26.
Figure 3.26 CE Output Mappings
26
25
24 23
36 MHz CLK START DV
12 11
Q[11:0]
0
I[11:0]
The I and Q data available on the bus represent either the equalized data
or frequency response of the channel depending upon the CE_SELECT
bit (address 0x11, bit 3). When CE_SELECT = 0, equalized data are
present on the MUXOUT bus; otherwise, the MUXOUT bus contains the
channel response in the frequency domain.
3.3.5 CSI Output
The CSI output provides an averaged measure per carrier on the
confidence to be placed on the hard decision.
The signals present at this point are the degree of confidence (CSI), a
start pulse that delimits the COFDM symbols (START), a data valid (DV)
signal that accompanies valid data, and an 18 MHz clock. These signals
are mapped on the MUXOUTBUS. See Figure 3.27.
Figure 3.27 CSI Output Mappings
26
18 MHz CLK
25
24 23
START DV
11 10
0
0
CSI[10:0]
A high value on the CSI bus indicates a low level of confidence, and viceversa. The CSI word is nonsigned data, which can be used to drive a
bar graph representing the quality of reception in a channel.
MUXOUT Interface
3-15
3.3.6 ADC Output
The ADC output lets you probe the internal ADC. The signals are the
digitized input samples (ADC) and the 18 MHz clock. These signals,
which are in two’s complement format, are mapped on the
MUXOUTBUS. See Figure 3.28.
Figure 3.28 ADC Output Mapping
26
25
8
18 MHz CLK
7
0
0
ADC[7:0]
3.4 Microprocessor Interface
The microprocessor interface operates in Serial Mode.
Important:
A Parallel mode interface is provided for test purposes. This
interface is used for LSI Logic internal testing and is not
intended for use in customer production receivers.
The Serial Bus mode interface is a serial interface operating in slave
mode. Its protocol is compatible with I2C specifications. For a more
detailed description of the Serial Bus, see Appendix A. The P_S input
signal selects either the serial or parallel mode. Table 3.4 summarizes
the different modes.
Table 3.4
Mode Selection Using the P_S Input Signal
P_S
Mode
Notes
Low
Parallel
LSI Internal use only
High
Serial
L64780 Serial Interface
When in Serial interface mode, D0 is used as a serial data signal, and
A0 is used as a serial clock signal. D[7:1] are used to set the serial bus
slave address. When using the serial bus, D[7:1] must be hardwired to
set the appropriate device slave address.
3-16
Interfaces
Chapter 4
Register Descriptions
This chapter provides an overview of the L64780 register space and
gives a detailed description of its registers. This chapter consists of the
following sections:
•
Section 4.1, “Memory Map,” page 4-2
•
Section 4.2, “Interrupt Registers,” page 4-7
•
Section 4.3, “TPS Registers,” page 4-11
•
Section 4.4, “Parameter Registers,” page 4-16
•
Section 4.5, “Mux Register Address Line 0x15,” page 4-32
•
Section 4.6, “Performance Monitoring Registers Address Line 0x16,”
page 4-34
•
Section 4.7, “Mode Register Address Line 0x19,” page 4-36
•
Section 4.8, “3-Wires Register Address Line 0x1A,” page 4-38
L64780 DVB-T OFDM Demodulator
4-1
4.1 Memory Map
Table 4.1 lists all L64780 registers and provides the DTTV demodulator
internal memory map. A description of each of these registers groups is
provided in the following sections.
Table 4.1
Space
1
4-2
L64780 Registers and Internal Memory Map
Address
Register name
Register
Width (Bits)
Type
0x00
Interrupt register
2
R
0x01
Interrupt Mask register
2
R/W
0x02
TPS register 1
4
R/W
0x03
TPS register 2
6
R/W
0x04
TPS register 3
7
R/W
0x05
Parameters register 1
8
R/W
0x06
Parameters register 2
8
R/W
0x07
Parameters register 3
8
R/W
0x08
Parameters register 4
8
R/W
Register Descriptions
Table 4.1
Space
2
L64780 Registers and Internal Memory Map (Cont.)
Address
Register name
Register
Width (Bits)
Type
0x09
Parameters register 5
8
R/W
0x0A
Parameters register 6
8
R/W
0x0B
Parameters register 7
8
R/W
0x0C
Parameters register 8
8
R/W
0x0D
Parameters register 9
8
R/W
0x0E
Parameters register 10
8
R/W
0x0F
Parameters register 11
8
R/W
0x10
Parameters register 12
8
R/W
0x11
Parameters register 13
8
R/W
0x12
Parameters register 14
3
R/W
0x13
Parameters register 15
6
R/W
0x14
Parameters register 16
6
R/W
0x15
MUX register
6
R/W
0x16
Performance Monitoring
register 1
6
R/W
0x17
Performance Monitoring
register 2
8
R
0x18
Performance Monitoring
register 3
8
R
0x19
Mode register
6
R/W
0x1A
3 Wires register
6
RW
3
Figure 4.1 through Figure 4.3 give a graphical view of the register
address space. Shaded parts in these figures denote reserved bits.
Memory Map
4-3
Figure 4.1
ddress
Graphical View of the L64780 Register Address Space 1
7
6
5
4
3
2
1
0
0x00
TPS
Sync
Into
Change
Change
Interrupt
Register
0x01
Sync
Change
TPS
Into
Change
Interrupt
Mask
Register
1
0
1
2
1
0x03
0
1
AFC
Clipping
7
2
1
6
5
1
0
2
AFC
Stall
4
AFC
Polarity
3
0
HP Code Rate
1
Hierarchy Info
AFC
Fine
Mode
AFC
Mode
Guard
TPS
Registers
0
QAM Type
1
0
AFC Sensitivity
2
1
0
1
0
1
0
AFC_INIT_FREQ [LSB]
7
6
5
0x07
4
3
2
AFC_INIT_FREQ [CSB]
7
4-4
2
Frame Number
0x06
0x08
0
LP Code Rate
0x04
0x05
0
FFT Mode
0x02
6
5
4
3
2
AFC_INIT_FREQ [MSB]
Register Descriptions
Parameter
registers
Figure 4.2
7
6
5
Soft
Decision
Width
BDI
Disable
SDI
Disable
Address
0x09
Graphical View of the L64780 Register Address Space 2
4
3
DOF Out
Format
2
1
0
DDFS
Disable
DDFS
Mode
ADC
On
Chip
2
0x0A
AGC
Disable
AGC Target[LSB]
5
0x0B
ADC
Format
2
0
6
2
0
AGC Gain
2
1
0
1
2
1
0
TIM IIRgain
TIM_LOOP_P
5
0x0D
4
3
2
1
0
Timing Offset Position[LSB]
TIM
STALL
0x0E
7
TIM
Polarity
6
Parameter
Registers
Timing Offset Position[MSB]
5
4
0x0F
3
2
1
0
1
0
Timing CLK INIT [LSB]
7
6
5
0x10
0x11
1
AGC target[MSB]
TIM_LOOP_I
7
3
R2C
SI
1
0x0C
4
AGC
Polarity
4
3
2
Timing CLK INIT [MSB]
CPE
Disable
CE
Disable
Disable
ETS
TEMPO
Type
CE
Select
0x12
5
4
3
0x13
FFT
Direction
FFT Gain setting
CSI Out
Format
CSI IIrate
2
1
0
1
0
HP_OFFSET
5
0x14
4
3
2
LP_OFFSET
Memory Map
4-5
Figure 4.3
Address
Graphical View of the L64780 Register Address Space 3
7
6
5
4
2
0x15
Frame
Sync
OK
7
6
0x17
5
7
6
4
0
0
MUXOUT Select
Freq
Sync
OK
TPS
OK
1
1
3
TIM
TIM
Start
Clock
Sync OK Sync OK
2
1
5
4
3
2
1
MUX
Register
Sync
OK
0
0
Performance
Monitoring
Registers
Peak Channel State Information Indication
Odrain
Ctrl
Wires3
Ctrl
2
4-6
2
2
Average Channel State Information Indication
0x18
0x1A
3
0
MUXIN Select
0x16
0x19
1
SD
Ctrl
1
MUX
Ctrl
0
WIRES3_IN
Register Descriptions
Soft
Reset
2
Auto
Mode
Enable
1
Change
Mode
0
WIRES3_OUT
Mode
Register
3 Wires
Register
4.2 Interrupt Registers
The DTTV demodulator generates interrupts based on events in specific
functional blocks of the chip. These events are reported to the Interrupt
register. Two types of events might be of interest to an external
microcontroller:
•
Events relating to severe impairments. The external microcontroller
must evaluate the severity of these events and take the necessary
corrective action.
•
Events relating to changes in the operation of the DTTV
demodulator. These occur during normal operation and are made
available to the external microcontroller for monitoring.
The Interrupt register at address 0x00 provides the microprocessor with
events on the DTTV demodulator that can cause an internal interrupt.
This read-only register contains a bitmap indicating which events took
place. It is associated with the Interrupt Mask register.
4.2.1 Address Line 0x00
7
2
0x00
RES
RES
1
0
SYNC_CHANGE TPS_INFO_CHANGE
Reserved
These bits are reserved.
[7:2]
SYNC_CHANGE
Synchronization Change Interrupt
R1
This bit indicates if one or more aspects of the DTTV
demodulator synchronization have changed.
The initial condition for the SYNC_CHANGE bit is 0 (no
interrupt). If this bit is set to 1, an interrupt is generated.
Interrupt Registers
4-7
The Sync change event is visible through the signal
SYNC CHANGE (see Section 4.6, “Performance Monitoring Registers Address Line 0x16”) and occurs when at
least one of the following synchronizations has changed
during the demodulation:
• The Frame_Sync_OK bit is set to 1 when the frame
synchronization is reached and reset to 0 when the
frame synchronization is lost. The Frame_Sync_OK
bit is visible through the Performance Monitoring
register.
• The Freq_Sync_OK bit is set to 1 when the demodulator is frequency locked and reset to 0 when the frequency synchronization is not yet reached or lost. The
Freq_Sync_OK bit is visible through Performance
Monitoring Register 1.
• The Start_Sync_OK bit is set to 1 when the timing
block has properly determined the start of the FFT; it
is reset to 0 when this is lost. Start_Sync_OK bit is
visible through Performance Monitoring Register 1.
• The Clock_Sync_OK bit is set to 1 when the sampling
frequency is properly locked; it is reset to 0 when sync
is not reached. Clock_Sync_OK is visible through Performance Monitoring register 1.
• The TPS_Sync_OK bit is set to 1 when the TPS
frame is error free; it is reset to 0 when the frame is
corrupted. The TPS_Sync_OK bit is visible through
Performance Monitoring Register 1.
TPS_INFO_CHANGE
TPS Change Interrupt
R0
A valid TPS structure has been received that differs from
the current mode of the DTTV demodulator. This interrupt
does not occur if the only change is in the frame number.
The TPS_INFO_CHANGE bit is initially reset to 0 (no
interrupt). If this bit is set to 1, an interrupt is generated.
The TPS_INFO_CHANGE bit is set to 1 only when the
received error-free (BCH-correct) TPS is different from
the last TPS information stored in the TPS registers. This
bit is only reset by a microprocessor read access. The
TPS_INFO_CHANGE bit is evaluated every COFDM
frame, and it is visible through the TPS_INFO_CHANGE
signal (see Section 4.3, “TPS Registers”).
4-8
Register Descriptions
4.2.2 Interrupt Mask Register, Address Line 0x01
The microprocessor can select between a polling or interrupt driven
approach by programming the Interrupt Mask register. Only when the bit
in the Interrupt Mask register associated with the event bit in the Interrupt
register is set to 1 is the interrupt for this event is enabled; otherwise,
polling is selected.
Any interrupt-related events reported in the Interrupt register lead to the
assertion of the INTn signal (active LOW). On receiving an interrupt
signal, the microcontroller is expected to read the Interrupt register to
identify the cause(s) of this interrupt. The microcontroller thereby resets
all interrupt events in the Interrupt register; this remains in effect until a
new interrupt (TPS info change or Sync change) occurs. To disable
permanently the interrupt mechanism, reset the Interrupt Mask register.
Figure 4.4 shows an implementation of the interrupt generation.
Figure 4.4
Interrupt Generation
AND
OR
Eventi
Maski
Interrupt Registers
INT
From other interrupts
4-9
Note that a read access to Address 0 resets the Interrupt Register. But
it does not mask new interrupts that arise at the time the host reads the
interrupt register; thus, when the Host reads the interrupt register, each
interrupt is either reset, or set again if a new interrupt occurs.
7
0x01
RES
2
RES
1
0
SYNC_CHANGE_MASK
TPS_INFO_CHANGE_
MASK
Reserved
These bits are reserved.
[7:2]
SYNC_CHANGE _MASK
Synchronization Change Interrupt Mask
R/W 1
This bit enables or disables the generation of an interrupt
if one or more aspects of the DTTV demodulator
synchronization have changed. If this bit is 0, the interrupt
is masked; if the bit is 1, the interrupt is enabled. The
initial condition for this bit is 0.
TPS_INFO_CHANGE_MASK
TPS Change Interrupt Mask
R/W 0
This bit enables or disables the generation of the interrupt
for the TPS_INFO_CHANGE bit. If this bit is 0, the
interrupt is masked; if the bit is 1, the interrupt is enabled.
The initial condition for this bit is 0.
4-10
Register Descriptions
4.3 TPS Registers
These registers have two functions, depending on whether they are read
from, or written to. If they are read from, they indicate that the contents
of the last TPS structure were correctly received. If they are written to,
they set the next mode of operation of the DTTV demodulator. The mode
change does not take effect until the CHANGE_MODE command is
issued (by setting the CHANGE_MODE bit in the Mode register). The
meaning of the bits contained in the TPS are described in the ETSI
specification.
4.3.1 Address Line 0x02
7
0x02
4
RES
3
2
FFT MODE
1
0
GUARD
RES
Reserved
These bits are reserved.
[7:4]
FFTMODE
COFDM Transmission Mode
R/W [3:2]
When this register is read, these bits provide the last
value received by the channel, using the TPS signalling
information.
When the register is written, these bits store the next
COFDM transmission mode value that the system uses.
The values are:
FFTMODE[1:0]
Definition
00
2 k Mode
01
8 k Mode
10
Unused
11
Unused
The initial condition for the FFTMODE is 0b00 (2k).
TPS Registers
4-11
GUARD
Guard Interval
R/W [1:0]
When this register is read, the Guard Interval provides
the last value received by the channel, using the TPS signalling information.
When this register is written, Guard [1:0] stores the next
Guard value that the system uses. The values are:
GUARD[1:0]
Definition
00
1/32 Guard Interval
01
1/16 Guard Interval
10
1/8 Guard Interval
11
1/4 Guard Interval
The initial condition for the Guard Interval is 0b00 (1/32).
4.3.2 Address Line 0x03
7
0x03
RES
6
RES
5
3
LP_CODE_RATE
Reserved
These bits are reserved.
2
0
HP_CODE_RATE
[7:6]
LP_CODE_RATE
Viterbi Low-Priority Code Rate
R/W [5:3]
When this register is read, these bits provide the last
value received by the channel, using the TPS signalling
information.
4-12
Register Descriptions
When this register is written, these bits store the next
Viterbi Code Rate for the Low-Priority stream value that
the system uses. The values are:
LP_CODE_RATE[2:0]
Definition
0
0
0
1/2 Code Rate
0
0
1
2/3 Code Rate
0
1
0
3/4 Code Rate
0
1
1
5/6 Code Rate
1
0
0
7/8 Code Rate
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
The initial condition for the LP_CODE_RATE is 0b000
(1/2).
HP_CODE_RATE
Viterbi High-Priority Code Rate
R/W [2:0]
When this register is read, these bits provide the last
value received by the channel, using the TPS signalling
information.
When this register is written, these bits store the next
Viterbi Code Rate for the High-Priority stream value that
the system uses. The values are:
HP_CODE_RATE[2:0]
Definition
000
1/2 Code Rate
001
2/3 Code Rate
010
3/4 Code Rate
011
5/6 Code Rate
100
7/8 Code Rate
101
Reserved
110
Reserved
111
Reserved
The initial condition for these bits is 0b001 (2/3).
TPS Registers
4-13
4.3.3 Address Line 0x04
7
0x04
6
RES
5
4
FRAME_NB
2
HIERARCHY
1
0
QAMTYPE
RES
Reserved
This bit is reserved.
FRAME_NB
COFDM Frame Number
R [6:5]
When this register is read, these bits provide the last
value received by the channel, using the TPS signalling
information. The values are:
FRAME_NB[1:0]
7
Definition
0
0
Frame 0
0
1
Frame 1
1
0
Frame 2
1
1
Frame 3
The initial condition for the FRAME_NB is 0b00 (Frame 0).
Internally, there are three TPS registers:
• The first (0x02, the active TPS register) contains the
current mode of the DTTV demodulator.
• The second (the next TPS register, 0x03) is written by
writing to the TPS register in the register map. When
the “change mode” command is issued, the next TPS
register is copied into the active TPS register, and this
becomes the current mode of the demodulator.
• The third register (the received TPS register, 0x04)
contains a copy of the last valid TPS that was
received in the input signal. This register can be read
by reading from the TPS register in the register map.
If the AUTO_MODE_ENABLE bit is set, then every time
a valid TPS is received and a super-frame boundary is
detected, the demodulator copies the contents of the
received TPS register into the active TPS register (and
changes the current mode of the DTTV receiver if the
received TPS changes).
If the received TPS (stored in the received TPS register)
and the current mode of the DTTV demodulator (held in
4-14
Register Descriptions
the active TPS register) differ, the TPS_INFO_CHANGE
bit is set to 1 for one CLK18 clock cycle. When the
TPS_INFO_CHANGE interrupt is enabled and this event
occurs, the DTTV demodulator generates an interrupt to
the external microcontroller. The rule for the
TPS_INFO_CHANGE applies to all TPS data bits except
for the frame number.
HIERARCHY COFDM Nonuniform Constellation Ratio
R/W [4:2]
When this register is read, these bits provide the last
value received by the channel, using the TPS signalling
information.
When this register is written, these bits store the next
Constellation expansion ratio that the system uses. The
values are:
HIERARCHY[2:0]
Definition
000
Nonhierarchical
001
α = 1
010
α = 2
011
α = 4
100
Reserved
101
Reserved
110
Reserved
111
Reserved
The initial condition for the HIERARCHY is 0b000
(Nonhierarchical).
TPS Registers
4-15
QAMTYPE
Constellation Type
R/W [1:0]
When this register is read, these bits provide the last
value received by the channel, using the TPS signalling
information.
When this register is written to, these bits store the next
Constellation Type value that the system uses. The
values are:
QAMTYPE[1:0]
00
Definition
QPSK
01
16 QAM
10
64 QAM
11
reserved
The initial condition for the QAMTYPE is 0b10 ( 64 QAM).
4.4 Parameter Registers
The Parameter registers contain configuration information. If the registers
are read, they indicate the current parameter value. These Parameter
registers are only configurable through the microprocessor.
4.4.1 Address Line 0x05
7
0x05
6
5
4
3
2
0
AFC_
AFC_FINE
AFC_MODE
AFC_STALL AFC_POL AFC_SENSITIVITY
CLIPPING
_MODE
AFC_CLIPPING
AFC Loop Bandwidth Limiter
R/W 7
This bit selects the combination method between the
Fine Algorithm part and the Coarse Algorithm part.
When using Method I (AFC_CLIPPING = 0), the
combination is done by adding the two values. When the
Coarse part is an integer number of carrier spacing, and
the Fine part is a fraction of the carrier spacing, the result
is the exact frequency offset.
When using Method II (AFC_CLIPPING = 1), the Fine
part is only considered when the AFC Coarse value is 0.
4-16
Register Descriptions
If not, the value applied to the Tuner Oscillator (via the
Sigma-Delta) is either +1 or −1. This limits the bandwidth
of the system.
The initial condition for the AFC_CLIPPING bit is 1, which
is Method II.
AFC_MODE
AFC Muxin Mode
R/W 6
When the MUXIN bus is connected to the AFC, this bit
determines if the Symbol Number is coming from the
OBC (Partial MUXIN Mode), as in Normal functional
mode, or coming from the MUXIN bus itself (Full MUXIN
Mode). If this bit is 0, the Symbol Number is coming from
the Full MUXIN Mode; if this bit is 1, the Symbol Number
is coming from the Partial MUXIN Mode.
The initial condition for the AFC_MODE is 0, the Full
MUXIN mode. However, this has no effect if the default
mode of AFC_MUXIN is 0 (which means that the AFC is
taking its Symbol Number from the OBC no matter what
the value of AFC_MODE is). See the definition of the
MUXIN register for more information.
AFC_FINE_MODE
AFC Fine Algorithm Mode
R/W 5
This bit determines if the AFC Fine Algorithm performs a
weighted mean.
If the Weighted mean mode is chosen (this bit is 0), the
AFC algorithm performs a weighted mean on the signal
measurements to perform its Fine AFC calculation.
If the Unweighted mean mode is chosen (this bit is 1), the
AFC algorithm does not perform a weighted mean on the
signal measurements to perform its Fine AFC calculation.
The initial condition for this bit is 0, the Weighted Mean
mode.
AFC_STALL
AFC Loop Updating Freeze
R/W 4
This bit determines if the AFC Loop is working or frozen.
If the Loop is working (0), the integrator inside the
L64780 updates its value from time to time.
Parameter Registers
4-17
If the Loop is stalled (1), the integrator inside the L64780
keeps its internal value constant, enabling you to set the
Frequency Offset by means of software (using
AFC_INIT_FREQ).
The initial condition for the AFC_STALL is 0, the normal
working mode.
AFC_POL
AFC VCO Polarity
R/W 3
These bits determine the polarity of the external VCO.
If the polarity is positive (this bit is 0), the output
frequency of the external down-converter must increase
with increasing voltage from the AFCOUT pin.
If the polarity is negative (this bit is 1), the output
frequency of the external down-converter must decrease
with increasing voltage from the AFCOUT pin.
The initial condition for the AFC_POL is 0 (positive).
AFC_SENSITIVITY
AFC Loop Gain
R/W [2:0]
These bits adjust the AFC Gain of the Loop Filter. The
value is set according to the sensitivity of the AFC input
of the external down-converter. The values in digital AFC
loop mode are:
AFC_SENSITIVITY[2:0]
Definition
–5
0
0
0
K SENS ≈ 1.52 ×10
0
0
1
K SENS ≈ 3 ×10
–5
0
1
0
K SENS ≈ 6 ×10
–5
0
1
1
K SENS ≈ 1.22 ×10
1
0
0
K SENS ≈ 2.44 ×10
1
0
1
K SENS ≈ 4.88 ×10
1
1
0
K SENS ≈ 9.8 ×10
1
1
1
K SENS ≈ 1.95 ×10
–4
–4
–4
–4
–3
The initial condition for these bits is 0b110, or
–4
K SENS ≈ 9.8 ×10 .
4-18
Register Descriptions
The values in Analog AFC loop mode are:
AFC_SENSITIVITY[2:0]
Definition
–4
0
0
0
K SENS ≈ 2.44 ×10
0
0
1
K SENS ≈ 4.88 ×10
–4
–4
0
1
0
K SENS ≈ 9.8 ×10
0
1
1
K SENS ≈ 1.95 ×10
1
0
0
K SENS ≈ 3.9 ×10
1
0
1
K SENS ≈ 7.8 ×10
1
1
0
K SENS ≈ 1.56 ×10
1
1
1
K SENS ≈ 3.1 ×10
–3
–3
–3
–2
–2
The initial condition for these bits is 0b110, or
–2
K SENS ≈ 1.56 ×10 .
4.4.2 Address Lines 0x06, 0x07, 0x08
7
0
0x06
AFC_INIT_FRQ_LSB
0x07
AFC_INIT_FRQ_CSB
0x08
AFC_INIT_FRQ_MSB
AFC_INIT_FRQ
AFC Initial Frequency Offset
R/W [7:0]
These three 8-bit registers select the Initial Frequency
Offset that is directed towards the Tuner or the DDFS
block.
• When these registers are read, the resultant value
represents the actual Frequency Offset (for example,
the content of the integrator) recovered by the system.
• When this register is written, the resultant value reinitializes the Integrator value.
• Three OBC accesses are necessary to update these
registers; thus, you should first stall the Integrator by
setting AFC_STALL to 1, then update the values. You
can reactivate the integrator by resetting AFC_STALL
to 0.
The initial condition for these registers is 0.
Parameter Registers
4-19
4.4.3 Address Line 0x09
7
0x09
6
SOFTBIT
SOFTBIT
5
BDI_
SDI_
DISABLE DISABLE
4
3
DOF_OUTPUT_
FORMAT
2
1
DDFS_ DDFS_
DISABLE MODE
0
ADCON
Soft Decision Number of Bits
R/W 7
This bit determines if a 3-bit (0) or a 4-bit (1) soft decision
is used. The initial condition for this bit is 1.
BDI_DISABLE
BDI Disable
R/W 6
If this bit is 1, the Bit Deinterleaver is disabled; if this bit
is 1, the Bit Deinterleaver is enabled. The initial condition
for this bit is 0, the Normal Operational Mode.
SDI_DISABLE
SDI Disable
R/W 5
If this bit is 1, the Symbol Deinterleaver is disabled; if this
bit is 0, the Symbol Deinterleaver is enabled. The initial
condition for this bit is 0, the Normal Operational Mode.
DOF_OUTPUT_FORMAT
Chip Output Format
R/W [4:3]
These bits select the output format of the L64780 towards
the FEC decoder chip. The different formats are
described in Section 3.4, “Microprocessor Interface.”
There are three modes:
• When in Nonhierarchical mode, two submodes are
provided: Serial and Parallel. In Serial Mode, data is
presented only on SD0. In Parallel Mode, data is presented on SD0 and SD1.
• When in Hierarchical mode with only one FEC chip,
either the HP stream or the LP Stream is presented.
4-20
Register Descriptions
• When in Hierarchical mode with two FEC chips, HP
and LP streams are presented on SD0 and SD1,
respectively.
DOF_OUTPUT_
Hierarchical FORMAT[1:0]
Definition
NO
X
0
Serial Mode
NO
X
1
Parallel Mode
YES
0
0
HP stream over SD0, 1 FEC
Mode
YES
1
0
LP stream over SD0, 1 FEC
Mode
YES
X
1
HP over SD0, LP over SD1,
Two FEC Mode
The initial condition for these bits is 0b00.
DDFS_DISABLE
DDFS Disable
R/W 2
This bit determines if the DDFS performs the Baseband
correction (0) or not (1). The initial condition for the
DDFS_DISABLE is the Normal Operational Mode (0).
DDFS_MODE
DDFS Start Pulse Selector
R/W 1
If this bit is 0, the DDFS block gets its START Pulse
(pulse delimiting every COFDM symbol) from the Timing
Recovery Unit Block; if this bit is 1, the DDFS block gets
its START Pulse from the MUXIN Block.
The initial condition value for the DDFS_MODE bit is 0.
The DDFS block can operate in four modes, as listed in
Table 4.2.
Table 4.2
DDFS
Mode
Parameter Registers
DDFS Block Modes
DDFS
Muxin
DDFS
Disable
Functional Mode
X
0
0
Normal
0
1
0
Test
1
1
0
Down-Converter Off-Chip
X
X
1
Disable Mode
4-21
When in Normal mode, the L64780 receives a real signal
in the intermediate frequency (about 4.5 MHz), and the
R2C block performs the baseband conversion. In this
mode, the DDFS block receives a complex baseband
signal directly from the R2C block and takes the
DDFS_XIN, DDFS_YIN, and DDFS_DVIN signals and
the symbol synchronization DDFS_STARTIN signal from
the Timing synchronization (TIM) block.
In Down-Converter Off-Chip mode, the baseband
conversion is done by the tuner, but the COFDM symbol
synchronization signal is still provided by the TIM block.
In this mode, the DDFS block takes the DDFS_XOFF,
DDFS_YOFF, and DDFS_DVOFF signals from the offchip interface, whereas the symbol synchronization
DDFS_STARTIN signal comes from the TIM block (see
Section 3.2.1, “Access to Timing and DDFS Blocks,”
page 3-10, for the DDFS_XOFF, DDFS_YOFF, and
DDFS_DVOFF signals mapping into the MUXIN bus).
When in Test mode, the DDFS block receives the
baseband complex data and the symbol synchronization
from the off-chip interface. In this mode, the
DDFS_XOFF, DDFS_YOFF, DDFS_DVOFF, and
DDFS_STARTOFF signals come from the off-chip
interface. (See Section 3.2.1, “Access to Timing and
DDFS Blocks,” page 3-10, for the DDFS_XOFF,
DDFS_YOFF, and DDFS_DVOFF and DDFS_STARTOFF
signals mapping into the MUXIN bus.)
In Disable mode, only the DDFS_XIN, DDFS_YIN,
DDFS_DVIN, and DDFS_STARTIN signals are used; no
frequency shift is applied to the incoming complex data,
but the data processing time latency must be preserved.
ADCON
4-22
ADC Selector
R/W 0
This bit determines if the L64780 uses the 8-bit on-chip
(1), or the external 10-bit (0) ADC. The initial condition for
the ADCON is 0, the external 10-bit ADC.
Register Descriptions
4.4.4 Address Line 0x0A
7
0x0A
5
AGC_TARGET_LSB
4
3
AGC_DISABLE AGC_POL
2
0
AGC_GAIN
AGC_TARGET_LSB
AGC Target RMS Value (LSB)
R/W [7:5]
These bits select the LSBs of the Target RMS value of
the AGC Loop (see Section 2.3.1, “AGC Target RMS
Value”). The initial condition for these bits is 0b100.
AGC_DISABLE
AGC Disable
R/W 4
This bit determines if the AGC is disabled (1) or not (0).
The initial condition for the AGC_DISABLE bit is 0,
Normal Operational Mode.
AGC_POL
AGC Loop Polarity
R/W 3
This bit selects the polarity of the external AGC Loop.
If the polarity is positive (this bit is 0), the gain of the
external down-converter must increase with increasing
voltage from the AGCOUT pin.
If the polarity is negative (this bit is 1), the gain of the
external down-converter must decrease with increasing
voltage from the AGCOUT pin.
The initial condition for the AGC_POL is 1, negative.
Parameter Registers
4-23
AGC_GAIN
AGC Loop Gain
R/W [2:0]
These bits adjust the AGC Gain of the Loop Filter. The
value is set according to the sensitivity of the AGC loop.
The values are:
AGC_GAIN[2:0]
Definition
–3
0
0
0
K s ≈ 3.9 ×10
0
0
1
K s ≈ 9.8 ×10
0
1
0
K s ≈ 2.4 ×10
0
1
1
K s ≈ 6.1 ×10
1
0
0
K s ≈ 1.5 ×10
1
0
1
K s ≈ 3.8 ×10
1
1
0
K s ≈ 9.5 ×10
1
1
1
K s ≈ 2.4 ×10
–4
–4
–5
–5
–6
–7
–7
–5
The initial condition for these bits is 0b011, K s ≈ 6.1 ×10 .
4.4.5 Address Line 0x0B
0x0B
7
6
ADC_FORMAT
R2C_SI
5
0
AGC_TARGET_MSB
ADC_FORMAT
Format of ADC Output
R/W 7
This bit determines if the ADC outputs its values in two’s
complement (1) or in binary offset format (0). The initial
condition for the ADC_FORMAT bit is 0, binary offset.
R2C_SI
COFDM Spectrum Inversion
R/W 6
During the up-conversion and the following downconversion, the COFDM spectrum can be inverted,
depending on the equipment used. This bit determines if
the COFDM signal should be spectrally inverted (1) or not
(0).
The initial condition for the R2C_SI bit is 0, normal
operation.
This spectrum inversion changes the sign of the sine
function (negative for 0, positive for 1).
4-24
Register Descriptions
AGC_TARGET_MSB
AGC Target RMS Value (MSB)
R/W [5:0]
These bits select the MSBs of the Target RMS value of
the AGC Loop (see Section 2.3.1, “AGC Target RMS
Value”).
The initial condition for these bits is 0x0E.
4.4.6 Address Line 0x0C
7
0x0C
5
4
TIM_LOOP_I
2
1
TIM_LOOP_P
0
TIM_IIRGAIN
TIM_LOOP_I Timing Gain Loop 2
R/W [7:5]
These bits adjust the Timing Gain of the Loop Filter. The
value is set according to the sensitivity of the VXCO loop.
TIM_LOOP_I[2:0]
Definition
0
0
0
K I ≈ 0.125
0
0
1
K I ≈ 3.125 ×10
0
1
0
K I ≈ 7.8 ×10
0
1
1
K I ≈ 1.95 ×10
–2
–3
–3
–4
1
0
0
K I ≈ 4.8 ×10
1
0
1
K I ≈ 1.22 ×10
1
1
0
K I ≈ 3 ×10
1
1
1
K I ≈ 7.63 ×10
–4
–5
–6
The initial condition for the TIM_LOOP_I is ob011
–3
(Gain 3) K I ≈ 1.95 ×10 .
Parameter Registers
4-25
TIM_LOOP_P
Timing Gain Loop 1
R/W [4:2]
These bits adjust the Timing Gain of the Loop Filter. The
value is set according to the sensitivity of the VXCO loop.
TIM_LOOP_P[2:0]
Definition
0
0
0
K P ≈ 8.0
0
0
1
K P ≈ 4.0
0
1
0
K P ≈ 2.0
0
1
1
K P ≈ 1.0
1
0
0
K P ≈ 0.5
1
0
1
K P ≈ 0.25
1
1
0
K P ≈ 0.125
1
1
1
K P ≈ 6.25 ×10
–2
The initial condition for the TIM_LOOP_P is 0b011
K P ≈ 1.0.
(Gain 3)
TIM_IIRGAIN Timing IIR Filter Time Constant
R/W [1:0]
These bits govern the amount of IIR Filtering done in the
Timing Loop Filter.
TIM_IIRGAIN[1:0]
Definition
–2
0
0
α ≈ 6.25 ×10
0
1
α ≈ 3.125 ×10
1
0
α ≈ 1.56 ×10
1
1
–2
–2
–3
α ≈ 7.8 ×10
The initial condition for the TIM_IIRGAIN is 0b01 (Gain 1)
–2
α ≈ 3.125 ×10 .
4-26
Register Descriptions
4.4.7 Address Line 0x0D
7
0
0x0D
TIM_OFFSET_LSB
TIM_OFFSET_LSB
Start Pulse Phase Offset (LSB)
R/W [7:0]
The start pulse is a signal with a periodicity of every
FFT-MODE+GUARD 9 MHz cycles (in steady state). The
TIM_OFFSET bits adjust the phase of this signal in the
periodic window. The initial condition for the
TIM_OFFSET_LSB bits is 0x00.
4.4.8 Address Line 0x0E
0x0E
7
6
TIM_STALL
TIM_POL
TIM_STALL
5
0
TIM_OFFSET_MSB
TIM Loop Updating Freeze
R/W 7
This bit determines if the Loop is working (this bit is 0) or
stalled (this bit is 1).
If the Loop is working, the integrator inside the L64780
updates its value.
If the Loop is stalled, the integrator inside the L64780
keeps its internal value constant, letting you set the
VCXO Frequency Offset by means of the TIM_CLK_INIT
bits.
The initial condition for the TIM_STALL bit is 0, normal
working mode.
TIM_POL
TIM VCXO Polarity
R/W 6
This bit determines the polarity of the external VCXO:
• If the polarity is positive (this bit is 0), the output
frequency of the external VCXO increases with
increasing voltage from VCXOUT.
• If the polarity is negative (this bit is 1), the output
frequency of the external VCXO decreases with
increasing voltage from VCXOUT.
The initial condition for the TIM_POL is 1, negative
polarity.
Parameter Registers
4-27
TIM_OFFSET_MSB
Start Pulse Phase Offset (MSB)
R/W [5:0]
The start pulse is a signal with a periodicity of every
FFT-MODE + GUARD 9 MHz cycles (in steady state).
The TIM_OFFSET bits adjust the phase of this signal in
the periodic window. The initial condition for these bits is
0x00.
4.4.9 Address Lines 0x0F, 0x10
7
0
0x0F
TIM_CLK_INIT_LSB
0x10
TIM_CLK_INIT_MSB
TIM_CLK_INIT
Timing Initial VCXO Offset
R/W [7:0]
These two registers, TIM_CLK_INIT_LSB and
TIM_CLK_INIT_MSB, select the initial VCXO frequency
offset that is directed to the external VCXO.
When this register is read, its value represents the actual
VCXO offset (for example, the content of the integrator)
recovered by the system.
When this register is written, this value reinitializes the
Integrator value.
Two OBC accesses are required to update these registers;
thus, you should first stall the Integrator by setting
TIM_STALL to 1, then update the values. The process can
be unfrozen by clearing TIM_STALL back to 0.
The initial condition for these bits is 0x00 (both registers
set to 0x00).
4-28
Register Descriptions
4.4.10 Address Line 0x11
i
7
0x11
6
5
4
3
2
CE_
CPE_
CE_
CE_TEMPO- CE_SEL
DISABLE_
FFT_DIR
DISABLE DISABLE
TYPE
ECT
ETS
1
0
FFT_GAIN
CPE_DISABLE
Common Phase Error Disable
R/W 7
This bit determines if the CPE is disabled (1) or not (0).
The initial condition for this bit is 0, normal operation.
CE_DISABLE CE Disable
R/W 6
This bit determines if the CE is disabled (1) or not (0).
The initial condition for this bit is 0, normal operation.
CE_DISABLE_ETS
CE Timing Shift Disable
R/W 5
The Channel Equalizer emulates a negative echo to ease
implementation. If this bit has a value of 1, the negative
echo generation is disabled. If this bit is set to 0, the
negative echo generation is enabled. The initial condition
for this bit is 0, Working Mode.
CE_TEMPOTYPE
CE Timing Interpolation Type
R/W 4
This bit selects the mode of operation of the Channel
Equalizer Timing Interpolation. If this bit is 0, the mode is
Zero Order Hold; if this bit is 1, the mode is Linear. The
initial condition for this bit is 1, Linear.
CE_SELECT
CE MUXOUT Selector
R/W 3
When MUXOUT is selected to output the Channel
Equalizer value, either the Channel Response (1) or the
Equalized Data (0) can be output. Note that both cases
do not affect receiver functionality. The initial condition for
this bit is 0, Equalized Data.
FFT_DIR
FFT Direction
R/W 2
This bit determines if the FFT is in Forward mode (Timing
to Frequency Domain, 0) or Backward mode (Frequency
to Timing Domain, 1). For L64780 normal operational
mode, the FFT direction is Forward. The initial condition
for the FFT_DIR is 0, Forward.
Parameter Registers
4-29
FFT_GAIN
FFT Clipping and Rounding
R/W [1:0]
This register selects how the FFT clips and rounds in
case of overflow. The values are:
FFT_GAIN[1:0]
Definition
0
0
Gain 0
0
1
Gain 1
1
0
Gain 2
1
1
Gain 3
The initial condition for these bits is 0b10, Gain 2.
4.4.11 Address Line 0x12
7
3
0x12
RES
2
CSI_OUT_
FORMAT
RES
Reserved
These bits are reserved.
1
0
CSI_IIRATE
[7:3]
CSI_OUT_FORMAT
CSI Softbits Format
R/W 2
This bit allows the generation of softbit values either in
two’s complement (1) or in binary offset (0). The initial
condition for this bit is 0, binary offset.
CSI_IIRATE
CSI IIR Filter Gain
R/W [1:0]
These bits set the IIR Gain of the Channel State
Information Unit. The values are:
CSI_IIRATE[1:0]
Definition
0
0
Gain 0
0
1
Gain 1
1
0
Gain 2
1
1
Gain 3
The initial condition for the CSI_IIRATE is 0b01, Gain 1.
4-30
Register Descriptions
4.4.12 Address Line 0x13
7
0x13
6
5
RES
0
HP_OFFSET
RES
Reserved
These bits are reserved.
[7:6]
HP_OFFSET
CSI HP Stream Quantizer Gains
R/W [5:0]
These bits set the Quantizer Gain of the Channel State
Information Unit for the High-Priority stream. The initial
value for the HP_OFFSET bits is 0x36.
4.4.13 Address Line 0x14
7
0x14
6
5
RES
0
LP_OFFSET
RES
Reserved
These bits are reserved.
LP_OFFSET
CSI LP Stream Quantizer Gains
R/W [5:0]
These bits set the Quantizer Gain of the Channel State
Information Unit for the Low-Priority stream. The initial
value for the LP_OFFSET is 0x36.
Parameter Registers
[7:6]
4-31
4.5 Mux Register Address Line 0x15
This register brings data to and from specific blocks. The MUXIN register
is directly output from the OBC and goes to the Clock generator block.
7
0x15
6
5
RES
3
2
MUXIN
0
MUXOUT
RES
Reserved
These bits are reserved.
MUXIN
MUXIN Selector
R/W [5:3]
These bits select the point in the system to be driven
through the MUXIN input pins and the CLKMUXIN clock
to sample the data coming into the L64780. There are six
possibilities:
MUXIN
[7:6]
Definition
Muxin Clock
000
Normal Mode
Set LOW
001
MUXIN inputs to Timing and
DDFS Block
18 MHz
010
MUXIN inputs to AFC Block
36 MHz
011
MUXIN inputs to FFT Block
36 MHz
100
MUXIN inputs to CSI Block
18 MHz
101
MUXIN inputs to SDI Block
18 MHz
110
unused
Set LOW
111
unused
Set LOW
The initial value for MUXIN is 0b000 (no MUXIN).
Table 4.3 defines how to set the different MUXIN signals
and the Muxin clock.
4-32
Register Descriptions
Table 4.3
MUXIN Signal Settings and MUXIN Clock
TIM
Muxin
DDFS
Muxin
AFC
Muxin
FFT
Muxin
CSI
Muxin
SDI
Muxin
000
0
0
0
0
0
0
Set LOW
001
1
1
0
0
0
0
CLK18
010
0
0
1
0
0
0
CLK36
011
0
0
0
1
0
0
CLK36
100
0
0
0
0
1
0
CLK18
101
0
0
0
0
0
1
CLK18
110
0
0
0
0
0
0
Set LOW
111
0
0
0
0
0
0
Set LOW
MUXIN
MUXOUT
Muxin
Clock
MUXOUT Selector
R/W [2:0]
These bits select the point in the system to be monitored
through the output block. There are six possibilities:
MUXOUT[2:0]
Definition
0
0
0
DDFS Output Presented
0
0
1
FFT Output Presented
0
1
0
AFC Output Presented
0
1
1
CE Output Presented
1
0
0
CSI Output Presented
1
0
1
AFC Output Presented
1
1
0
unused
1
1
1
unused
The initial value for these bits is 0b011, CE Output.
Mux Register Address Line 0x15
4-33
4.6 Performance Monitoring Registers Address Line 0x16
These registers contain the aggregate statistical and monitoring
information available to the OBC block.
7
0x16
RES
6
RES
5
4
FRAME_ TPS_
SYNC_ SYNC_
OK
OK
3
2
1
0
AFC_
TIM_
TIM_CLK_
SYNC_
START_ SYNC_OK
SYNC_OK
OK
SYNC_OK
Reserved
These bits are reserved.
[7:6]
FRAME_SYNC_OK
COFDM Frame Synchronization
R/W 5
If the frame synchronization in the DTTV demodulator is
correct, this bit is 1 (ODFM frame is locked). If this bit is
0, the COFDM frame is unlocked. The initial condition for
this bit is 1, locked.
TPS_SYNC_OK
TPS Synchronization
R/W 4
If the BCH code in the TPS indicates that the TPS is
valid, this bit is 1 (TPS is locked). If this bit is 0, TPS is
unlocked. The initial condition for this bit is 1, locked.
AFC_SYNC_OK
AFC Synchronization
R/W 3
If the frequency synchronization in the DTTV
demodulator is correct, this bit is 1 (AFC locked);
otherwise, it is 0 (unlocked). The initial condition for this
bit is 1, locked.
TIM_CLK_SYNC_OK
Timing Synchronization
R/W 2
If the sampling frequency synchronization in the DTTV
demodulator is correct, this bit is 1 (VCXO is locked);
otherwise, it is unlocked. The initial condition for this bit
is 1, locked.
4-34
Register Descriptions
TIM_START_SYNC_OK
Start Pulse Synchronization
R/W 1
If the start FFT window synchronization (start pulse is
locked) in the DTTV demodulator is correct, this location
is 1; otherwise, the start pulse is unlocked. The initial
condition for this bit is 1, locked.
SYNC_OK
Overall Chip Synchronization
R/W 0
If all aspects of the DTTV demodulator are synchronized,
this bit is 1. If this bit is 0, at least one unit is not locked.
The initial condition for this bit is 1, locked.
4.6.1 Address Line 0x17
7
0x17
0
CSI_AVERAGE
CSI_AVERAGE
CSI Reliability Average
R [7:0]
This register indicates the overall reliability of the carriers
by making an average (integer number) of the reliability
of each carrier.
4.6.2 Address Line 0x18
7
0x18
CSI_PEAK
0
CSI_PEAK
CSI Reliability Peak
R [7:0]
This register gives the integer number of carriers when
the value of the filtered Channel State Information
exceeds a given threshold. If more than 255 carriers
exceed this value, then 255 is returned.
Performance Monitoring Registers Address Line 0x16
4-35
4.7 Mode Register Address Line 0x19
This register influences how the DTTV demodulator operates.
7
0x19
RES
RES
6
5
ODRAIN WIRES3
_CTRL _CTRL
4
3
2
SD_
CTRL
MUX_
CTRL
SOFT_
RESET
1
0
AUTO_
CHANGE
MODE_
_MODE
ENABLE
Reserved
This bit is reserved.
7
ODRAIN_CTRL
Output Drain Controller
R/W 6
This bit allows the 3-Wire Bus pins to be set in Open
Drain Mode. When this bit is 1, the 3-wire output bus is
working in open drain (1 => Z, 0 => 0). When this bit is
0, the bus is in normal mode. The initial condition for this
bit is 1, Output Drain Mode.
The WIRES3_CTRL and ODRAIN_CTRL bits generate
the OBC_WIRE3_CTRL[2:0] 3-state control signals, as
specified in the following table.
OBC_WIRE3_OUT
ODRAIN_CTRL WIRE3_CTRL OUT
0
0
0
0
0
1
0
0
0
0
1
Z
0
1
1
Z
1
0
0
1
1
1
0
Z
1
0
1
Z
1
1
1
Z
WIRES3_CTRL
3-Wire Bus 3-State Controller
R/W 5
When this bit is 1, the 3-Wires Bus pins are 3-stated.
When this bit is 0, the bus pins are in normal mode. The
initial condition for this bit is 0, normal mode.
4-36
Register Descriptions
SD_CTRL
Normal Output 3-State Controller
R/W 4
When this bit is 1, all Normal pins are 3-stated. The initial
condition for this bit is 0, normal mode.
MUX_CTRL
MUXOUT 3-State Controller
R/W 3
When this bit is 1, all MUXOUT pins are 3-stated. The
initial condition for this bit is 0, normal mode.
SOFT_RESET Chip Soft Reset
R/W 2
Setting this bit enables a hard reset of the L64780 logic
(except the OBC registers, which keep their values). This
allows a proper reset of the chip in any default
configuration (memories are also reset to 0). Note that
the Soft Reset must be asserted from the external
microcontroller; it is not a pulse. When this bit is 1, soft
reset is enabled. When this bit is 0, no soft reset is
possible.
AUTO_MODE_ENABLE
TPS Auto Updating
R/W 1
This bit determines if the TPS updating is controlled by
the external microcontroller, or if the Active registers are
automatically updated each time new value TPS arrive
from the Broadcaster.
If this bit is 1, the current mode (as defined by the TPS
register) of the demodulator is updated whenever a valid
TPS is received.
If this bit is 0, manual configuration of the TPS register is
required.
The initial condition for this bit is 0, Manual Update.
CHANGE_MODE
TPS Updating Register
W0
When a new mode of operation has been written into the
TPS register, writing the value 1 into this location causes
the demodulator to change mode. See Section 4.3, “TPS
Registers,” page 4-11 for more information.
Mode Register Address Line 0x19
4-37
4.8 3-Wires Register Address Line 0x1A
The 3-wires register emulates the 3-Wires Bus protocol and controls the
tuner. It can also be used to emulate a software I2C interface towards
the tuner.
7
0x1A
6
RES
5
3
WIRES3_IN
2
0
WIRES3_OUT
RES
Reserved
These bits are reserved.
[7:6]
WIRES3_IN
3-Wires Input
R/W [5:3]
These bits collect the information coming from the
3-Wires off-chip inputs. The initial condition for
WIRES3_IN is 0x0.
WIRES3_OUT 3-Wires Output
R/W [2:0]
These bits are directly presented off-chip to the control
Tuner. The initial condition for WIRES3_OUT is 0x0.
4-38
Register Descriptions
Chapter 5
Signal Descriptions
This chapter describes the L64780 signals. These signals are grouped
by function. Within each group, the signals are described in alphabetical
order. This chapter consists of the following sections:
•
Section 5.1, “Overview,” page 5-1
•
Section 5.2, “Microprocessor Interface,” page 5-3
•
Section 5.3, “Main Signals,” page 5-4
•
Section 5.4, “Sigma-Delta Outputs,” page 5-6
•
Section 5.5, “MUX Signals,” page 5-6
•
Section 5.6, “3-Wires Signals,” page 5-7
•
Section 5.7, “JTAG Signals,” page 5-7
•
Section 5.8, “Test Pins,” page 5-8
•
Section 5.9, “ASIC Pins,” page 5-8
•
Section 5.10, “PLL Pins,” page 5-8
•
Section 5.11, “Tester Pins,” page 5-9
5.1 Overview
Figure 5.1 provides the logic symbol for the L64780.
L64780 DVB-T OFDM Demodulator
5-1
Figure 5.1
L64780 Logic Symbol
Microprocessor Interface
D
A
5
READ
DTACKn
INTn
DIGIN
ASn
P_S
8
Main inputs
RESET
CSn
Main outputs
4
10
4
CLK18
AVIN
SD1
SD0
DVOUT
ADCPD
DVOUT_LP
ADCGVSS
STARTOUT
ADCVSS
CLKOUT54
ADCGVDD
ADCVDD
ADDVREFP
Sigma-Delta outputs
AFCOUT
AGCOUT
ADCVREFN
IBIAS
VCXOUT
L64780
JTAG pins
TCK
TMS
TDI
TRESETN
TDO
DVB-T Receiver
Mux I/O
27
MUXOUT
17
MUXIN
CLKMUXIN
Tester pins
3 Wires I/O
3
XCTR_OUT
TEST0
TEST1
3
ASIC pins
TTN
TIDDTN
PROCQ
PLLAGND
PLLVSS
PLLVDD
PLLLP2
PLL pins
5-2
Signal Descriptions
PLLTSTCLK
PLLTSTSEL
XCTR_IN
5.2 Microprocessor Interface
This section lists and describes the microprocessor interface signals.
Note that the parallel interface mode is used for LSI Logic internal testing
and is not intended for use in customer production receivers. The serial
mode interface is used for production systems.
A[4:0]
Address Bus
I
The DTTV receiver has a five-bit address bus, A[4:0], that
is used with an eight-bit data bus, D[7:0], a read/write
strobe, Read, an address strobe, ASn, and a chip select
strobe, CSn, to read and write internal registers. The
address lines select internal registers. In Serial Mode, A0
is used as the serial clock, and A[4:1] must be connected
to ground.
ASn
Address Strobe
I
Active LOW address strobe input. Latches the address
on the A[4:0] bus on the falling edge. In Serial interface
mode, ASn must be connected to VDD.
CSn
Chip Select
I
Active LOW chip select strobe input. During a read cycle,
CSn must be LOW to access the on-chip data registers.
During a read access, the external controller can latch
the data from the DTTV receiver with the rising edge of
CSn. During a write access, CSn must go LOW prior to
data being valid from the external controller to the DTTV
receiver. In Serial Interface mode, CSn must be connected to VDD.
D[7:0]
Microprocessor Data Bus
I/O
This bidirectional bus is used as an input when data is
written to the chip, and as an output when the chip is
read. When the L64780 is not being read or written to,
the data lines are 3-stated. In Serial Interface Mode, D0
is used as the serial data, and D[7:1] are used for the
programmable Serial Bus interface.
DTACKn
Data Transaction Acknowledge
O
Active LOW output indicating that the transaction has
been completed. When not driven, the line is open-drain
3-stated.
Microprocessor Interface
5-3
INTn
Interrupt
O
The DTTV receiver asserts INTn when an internal,
unmasked interrupt flag is set. INTn remains asserted as
long as the interrupt condition persists and the interrupt
flag is not masked. When not driven, the line is opendrain 3-stated.
P_S
Microprocessor Operation Mode
When this signal is LOW, operation is Parallel Mode;
when HIGH, operation is Serial Mode.
READ
Read Strobe
I
When HIGH, a read operation is selected; when LOW, a
write operation is selected. In Serial interface mode,
READ must be connected to VDD.
I
5.3 Main Signals
This section lists and describes the main signals input to the L64780 or
output to the L64705/L64724.
5-4
ADCGVDD
Guard VDD for Internal ADC
Must be connected to VDD.
I
ADCGVSS
Internal ADC Guard VSS
Must be connected to ground.
I
ADCPD
Power-Down Mode for Internal ADC
I
This pin is active HIGH and in normal mode must be connected to ground.
ADCVDD
Analog VDD for Internal ADC
Must be connected to VDD.
ADCVREFN
Internal ADC Negative Reference Voltage
I
When not used, this pin must be connected to ground.
ADCVREFP
Internal ADC Positive Reference Voltage
I
When not used, this pin must be connected to ground.
ADCVSS
Analog VSS for Internal ADC
Must be connected to ground.
I
AVIN
Analog Input for Internal ADC
For an external ADC, this pin must be connected to
ground.
I
Signal Descriptions
I
CLK18
18 MHz Clock
I
This is the 18 MHz input clock coming from the external
VCXO.
CLKOUT54
54 MHz Clock
O
This is the 54 MHz clock output and is used to clock the
L64705 or the L64724.
DIGIN[9:0]
Digital Inputs
I
Digital inputs in normal mode when a 10-bit off-chip ADC
is used. DIGIN0 represents the LSB, while DIGIN9
represents the MSB. This bus is latched with the CLK18
clock. In MUXIN mode, DIGIN[9:0] represents the 10
LSBs of the 27 MUXIN bits, with DIGIN[0] mapped to
MUXIN0, and DIGIN9 to MUXIN9. For an on-chip ADC,
this bus must be connected to ground.
DVOUT
SD0 Data Valid Out
O 3-State
When asserted HIGH, this signal validates the SD0[3:0]
bus.
DVOUT_LP
SD1 Data Valid Out
O 3-State
When asserted HIGH, this signal validates the SD1[3:0]
bus.
IBIAS
Input Bias Current for Internal ADC
I
When not used, this pin must be connected to ground.
RESET
Reset
I
Hard reset. This pin is active-HIGH. See Section Table 6.6,
“Reset AC Timing Parameters,” page 6-5, for the minimum and maximum assertion time for a valid reset.
SD0[3:0]
SD0 Bus
O 3-State
The first 4-bit output bus used to output the high- and
low-priority streams.
SD1[3:0]
SD1 Bus
O 3-State
The second 4-bit output bus used to output the high- and
low-priority streams.
STARTOUT
First Soft Decision Mark
O 3-State
When asserted HIGH, this signal marks the first soft
decision of an COFDM symbol to be presented off-chip.
Main Signals
5-5
5.4 Sigma-Delta Outputs
This section lists and describes the output signals to the L64705/L64724.
AGCOUT
AGC Output
Sigma-Delta output of the AGC.
VCXOUT
O Open Drain
O Open Drain
Sigma Delta output of the VCXOUT.
AFCOUT
AFC Output
Sigma Delta output of the AFCOUT.
O Open Drain
5.5 MUX Signals
This section lists and describes the MUX input and output signals.
This interface is used for LSI Logic internal testing and is not intended
for use in customer production receivers.
MUXIN[16:0]
Muxin Bus
I Pull-Down
This bus is combined with the 10-bit ADCIN[9:0] to form
a 27-input MUXIN bus. When not used, this bus must be
connected to ground.
CLKMUXIN
Clock for MUXIN
I Clock
This pin provides the clock to latch the MUXIN bus.
MUXOUT[26:0]
MUX Test Bus
This 27-input bus is used for testing.
5-6
Signal Descriptions
O 3-State
5.6 3-Wires Signals
This section lists and describes the 3-wire signals.
XCTR_OUT[2:0]
Tuner Control Output
O 3-State
These three output pins are mainly used to control the
tuner and are directly controlled through the
microprocessor.
XCTR_IN[2:0] Tuner Control Input
I
These three input pins collect information from the tuner.
When not used, these pins must be connected to ground.
5.7 JTAG Signals
This section lists and describes the JTAG signals.
TCK
JTAG TAP Clock
I Pull-Up
When in normal operating mode, this pin must be
connected to VDD.
TDI
JTAG TAP Test Data Input
I Pull-UP
When in normal operating mode, this pin must be
connected to VDD.
TDO
JTAG TAP Test Data Output
JTAG TAP Test Data output.
TMS
JTAG TAP Test Mode Select
I Pull-Up
When in normal operating mode, this pin must be
connected to VDD.
TRESETN
JTAG TAP Reset
I Pull-Up
When in normal operating mode, this pin must be
connected to VDD.
3-Wires Signals
O 3-State
5-7
5.8 Test Pins
This section lists and describes the test signals.
TEST0
Test Selection 0
I
This pin is used for test selection. When in normal
operating mode, this pin must be connected to ground.
TEST1
Test Selection 1
I
This pin is used for test selection. When in normal
operating mode, this pin must be connected to ground.
5.9 ASIC Pins
This section lists and describes the ASIC signals.
TTn
I
This pin is active LOW and controls all the output pins. In
normal operating mode, it must be connected to VDD.
TIDDTN
I
This pin is active HIGH. In normal operating mode, it
must be connected to ground.
PROCQ
O
Dedicated output for ASIC characterization.
5.10 PLL Pins
This section lists and describes the PLL signals.
5-8
PLLVSS
Ground for Internal PLL
This signal must be connected to ground.
I
PLLVDD
VDD for Internal PLL
This signal must be connected to VDD.
I
PLLAGND
Analog Ground for Internal PLL
This signal must be connected to ground.
I
PLLLP2
VCO Voltage Control
This signal must be connected to the external filter.
I
Signal Descriptions
5.11 Tester Pins
This section lists and describes the internal tester signals.
PLLTSTCLK
I
Pin dedicated to internal test purposes. In normal
operating mode, this pin must be connected to ground.
PLLTSTSEL
I
Pin dedicated to internal test purposes. In normal
operating mode, this pin must be connected to ground.
Tester Pins
5-9
5-10
Signal Descriptions
Chapter 6
Specifications
This chapter describes the electrical specifications, power requirements,
DC characteristics, and AC timing parameters for the L6780. It consists
of the following sections:
•
Section 6.1, “Electrical Specifications,” page 6-1
•
Section 6.2, “AC Timing,” page 6-4
•
Section 6.3, “Signal Specifications,” page 6-6
•
Section 6.4, “Pinouts,” page 6-11
•
Section 6.5, “Mechanical Drawing,” page 6-15
6.1 Electrical Specifications
This section specifies the electrical requirements for L64780.
Table 6.1 lists the absolute maximum ratings for the L64780.
Table 6.1
Absolute Maximum Ratings
Parameter
Symbol
Limits1
Unit
DC Supply Voltage
VDD
−0.3 to +3.9
V
LVTTL Input Voltage
VIN
−1.0 to VDD + 0.3
V
5 V Compatible Input Voltage
VIN
−1.0 to 6.5
V
DC Input Current
IIN
± 10
mA
Storage Temperature Range (Plastic)
TSTG
−40 to +125
°C
1. The ratings in this table are those beyond which permanent device damage is likely to
occur. These values should not be used as the limits for normal device operation.
L64780 DVB-T OFDM Demodulator
6-1
Table 6.2 lists the recommended operating conditions for the L64780.
Table 6.2
Recommended Operating Conditions
Parameter
Symbol
Limits1
Unit
DC Supply Voltage
VDD
+3.0 to +3.6
V
Operating Ambient Temperature Range
TA
0 to +70
°C
1. For normal device operation, adhere to the limits in this table. Sustained operation of the
device at conditions exceeding these values, even if they are within the absolute maximum
rating limits, can result in permanent device damage or impaired device reliability. Device
functionality to stated DC and AC limits is not guaranteed if conditions exceed recommended
operating conditions.
Table 6.3 lists the DC characteristics of L64780, which is produced with
the LCBG10p process. This is a 0.35-micron drawn gate length cellbased process. Characteristics in the table are the same for any device
that has a buffer with the listed parameters.
Table 6.3
DC Characteristics
Symbol
Parameter
VDD
Supply Voltage
VIL
Input Low Voltage
VIH
Input High Voltage
Condition
Min
Typ
Max
Unit
3.0
3.3
3.6
V
0.8
V
VSS − 0.5
LVTTL Temp Range
2.0
5-V Compatible
2.0
VDD +0.3 V
5.5
V
VT
Switching Threshold
1.4
2.0
V
VT+
Schmitt Trigger, Positivegoing Threshold
1.7
2.0
V
VT−
Schmitt Trigger, Negativegoing Threshold
0.8
1.0
V
Schmitt Trigger, Hysteresis
0.6
0.7
V
Input Current
VIN = VDD or VSS
Inputs with Pulldown
VIN = VDD
Resistors
Inputs with Pullup Resistors VIN = VSS
−10
35
±1
115
10
222
mA
mA
-35
−115
−214
mA
IIN
6-2
Specifications
Table 6.3
DC Characteristics (Cont.)
Symbol
Parameter
VOH
Output High Voltage
Type
Type
Type
Type
Type
Type
VOL
B1
B2
B4
B6
B8
B121
Condition
IOH
IOH
IOH
IOH
IOH
IOH
= -1 mA2
= -2 mA3
= -4 mA3
= -6 mA3
= -8 mA3
=-12 mA3
IOL
IOL
IOL
IOL
IOL
IOL
= 1 mA
= 2 mA
= 4 mA
= 6 mA
= 8 mA
=12 mA
Min
Typ
Max
Unit
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
0.2
0.2
0.2
0.2
0.2
0.2
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
V
V
V
±1
10
mA
2.4
2.4
2.4
2.4
2.4
2.4
Output Low Voltage
Type
Type
Type
Type
Type
Type
B1
B2
B4
B6
B8
B122
−10
IOZ
3-state Output Leakage
Current
VOH = VSS or VDD
IOS
Output Short Circuit
Current3, BT4
VO = VDD
VO = VSS
140
−40
mA
mA
Output Short Circuit, BT4F
VO = VDD
VO = VSS
67
−86
mA
mA
IDD
Quiescent Supply Current
VIN = VDD or VSS
ICC
Dynamic Supply Current
CIN
Input Capacitance4
COUT
Output Capacitance5
tbd
mA
Input and
Bidirectional Buffers
2.5
pF
5-volt Compatible
3.0
pF
Output Buffer5
2.0
pF
5-volt Compatible
3.0
pF
1. Requires two output pads.
2. See the “Interfacing to 5 V Signals Using G10®-p Technologies” application note for “F” series output buffer IOH values.
3. Type B4 output. Output short circuit current for other outputs will scale.
4. Excluding package capacitance.
5. Output using single buffer structure (excluding package).
Electrical Specifications
6-3
6.2 AC Timing
The following subsections provide the AC timing for the input data
interface and output data interface.
6.2.1 Input Data Interface
Figure 6.1 shows the waveform timing for the input data interface.
Figure 6.1
Input Data AC Timing
3
4
1
2
CLK18
DIGADCIN
Table 6.4 lists the AC timings for the input data interface of the L64780.
Table 6.4
Input Data AC Timing Parameters
No.
Parameter
Description
Min
Max
Unit
1
ts
Input Setup time to CLK18
6
–
ns
2
th
Input Hold time to CLK18
–
13
ns
3
tpwh
Clock pulse width high
24.9
–
ns
4
tcycle
Clock cycle time
55.5
–
ns
6-4
Specifications
6.2.2 Output Data Interface
Figure 6.2 shows the waveform timing for the output data interface.
Figure 6.2
Output Data AC Timing
T
1
CLKOUT54
S0[3:0]
S1[3:0]
STARTOUT
DVOUT
DVOUT_LP
T = 3/2 * CLK18
Table 6.5 lists the AC timing parameters for the output data interface of
the L64780.
Table 6.5
1
Output Data AC Timing Parameters
Parameter
Description
tod
Output delay from CLKOUT54 falling
edge
Min
Max
Unit
–
5.0
ns
6.2.3 Reset Timing
Figure 6.3 illustrates the reset timing for L64780. Table 6.6 lists and
describes the output data AC timing parameters.
Figure 6.3
Reset Timing
.
1
2
RESET
Table 6.6
Reset AC Timing Parameters
Parameter
Description
1
tRWH
Reset Pulse Width High
2
tWK
Wake-Up time (PLL acquisition time)
AC Timing
Min
Max
Unit
3
–
CLK18
cycles
300
–
ms
6-5
6.3 Signal Specifications
Table 6.7 provides a summary of the pin numbers and their associated
signals, grouped by function.
Table 6.7
Signal Summary List
Pin Name
Description
Buffer Type
5-Volt
Compatible
99
CLK18
Input clock
LVTTL Input
Yes
–
20
RESET
Main Reset
LVTTL Input
Yes
High
34
CLKOUT54
Clock output to
the L64705 or
L64724
LVTTL
Output
Yes
–
Address Bus1
LVTTL Input
Yes
LVTTL Bidir
Yes
Pin
Drive
(mA)
Type
Active
Major I/Os
Microprocessor Interface
125–9
A[4:0]
Bus2
Pull-Down
–
109–18
D[7:0]
Data
108
READ
Read/Write
selection
LVTTL Input
Yes
Pull-Up
–
107
CSn
Chip Select
LVTTL Input
Yes
Pull-Up
Low
106
ASn
Address Strobe
LVTTL Input
Yes
Pull-Up
Low
35
DTACKn
Data
Acknowledge
LVTTL
Output
Yes
4
3-State
Low
36
INTn
Interrupt
LVTTL
Output
Yes
4
Open
Drain
Low
105
P_S
Serial/Parallel
Mode
LVTTL Input
Yes
6-6
Specifications
4
–
–
Table 6.7
Signal Summary List (Cont.)
Pin Name
Description
Buffer Type
5-Volt
Compatible
144–142,
139, 138,
135–133,
131, 130
DIGIN[9:0]
Digital Input in
normal mode.
Testin input
otherwise
LVTTL Input
Yes
152
ADCPD
ADC Power
Down
Analog Input
Yes
HIGH
153
ADCGVSS
Guard VSS
Supply
Analog Input
Yes
–
154
ADCVSS
Analog VSS
supply
Analog Input
Yes
–
155
ADCVREFP
Positive
Reference
Voltage
Analog Input
Yes
–
156
ADCVREFN
Negative
Reference
Voltage
Analog Input
Yes
–
157
AVIN
Analog Input
when using the
internal ADC
Analog Input
YES
–
158
IBIAS
Input bias
current
Analog Input
Yes
–
159
ADCVDD
Analog VDD
supply
Analog Input
Yes
–
160
ADCGVDD
Guard VDD
Supply
Analog Input
Yes
–
Pin
Drive
(mA)
Type
Active
Pull-Down
–
Main Input
Signal Specifications
6-7
Table 6.7
Pin
Signal Summary List (Cont.)
Pin Name
Description
Buffer Type
5-Volt
Compatible
Drive
(mA)
Type
Active
Main Output
63
DVOUT
SD0 Data Valid
Out
LVTTL
Output
Yes
4
3-state
–
62
DVOUT_LP
SD1 Data Valid
Out
LVTTL
Output
Yes
4
3-state
–
61
STARTOUT
First Soft
Decision Mark
LVTTL
Output
Yes
4
3-state
–
56–8, 60
SD0[3:0]
SD0 Bus
LVTTL
Output
Yes
4
3-state
–
51–3, 55
SD1[3:0]
SD1 Bus
LVTTL
Output
Yes
4
3-state
–
PWM Output
42
VCXOUT
VCXOUT
Timing Loop
LVTTL
Output
Yes
4
Open
Drain
–
122
AFCOUT
Output to the
Tuner
LVTTL
Output
Yes
4
Open
Drain
–
150
AGCOUT
Output to the
AGC
LVTTL
Output
Yes
6
Open
Drain
–
Pull-Down
–
Mux In Pins
5, 6, 8–
12, 14–
18, 21–
24, 26
MUXIN[16:0]
Input Mux.
Combined with
DIGADCIN to
form 27 input
bits
LVTTL Input
Yes
50
CLKMUXIN
Clock output
use to
Generate
MUXIN bus
LVTTL
Output
Yes
6-8
Specifications
4
–
Table 6.7
Pin
Signal Summary List (Cont.)
5-Volt
Compatible
Drive
(mA)
Type
Active
Pin Name
Description
Buffer Type
MUXOUT[26:0]
Output Mux:
Mainly for test
issues
LVTTL
Output
Yes
4
3-state
–
4
3-state
–
Mux Out
64,
66–69,
71–74,
76–79,
82–85,
87–90,
92–97,
3 Wires Buffer
37–39
XCTR_OUT[2:0] Pins used to
control the
Tuner
LVTTL
Output
Yes
2–4
XCTR_IN[2:0]
LVTTL Input
Yes
Pins used to
retrieve
informations
from Tuner
–
JTAG: Test Access Port (TAP)
28
TCK
JTAG Tap Clock LVTTL Input
Yes
Pull-Up
–
29
TMS
JTAG Tap Test
Mode Select
LVTTL Input
Yes
Pull-Up
–
30
TDI
JTAG Tap Test
Data Input
LVTTL Input
Yes
Pull-Up
–
33
TDO
JTAG Tap Test
Data Output
LVTTL
Output
Yes
3-state
–
27
TRESETN
JTAG Tap
Reset
LVTTL Input
Yes
Pull-Up
Low
4
Test PLL; Scan Mode; Bist Mode
46
TEST0
Test Mode
Selection
LVTTL Input
Yes
–
47
TEST1
Test Mode
Selection
LVTTL Input
Yes
–
Signal Specifications
6-9
Table 6.7
Pin
Signal Summary List (Cont.)
Pin Name
Description
Buffer Type
5-Volt
Compatible
Drive
(mA)
Type
Active
ASIC Specific Pins
45
TTN
Control tn pins
of all
bidirectional
and 3-state
outputs
LVTTL Input
Yes
Low
140
TIDDTN
Control power
down PLL,
oscillator and
disable pull
up/pull down
LVTTL Input
Yes
High
147
PROCQ
Dedicated
output of
Procmon
LVTTL
Output
Yes
–
Internal PLL Pins
103
PLLVSS
PLL ground
Analog Input
Yes
–
100
PLLVDD
PLL power
Analog Input
Yes
–
102
PLLLP2
VCO control
voltage pin,
connection to
external loop
filter
Analog Bidir
Yes
–
101
PLLAGND
PLL analog
ground
Analog
Output
Yes
–
145
PLLTSTCLK
open pll loop
LVTTL Input
Yes
–
146
PLLTSTSEL
replace pll clk
output and
feedback loop
LVTTL Input
Yes
High
Tester Pins
1. A0 is also used as the
2. D0 is also used as the
6-10
I2C Serial Clock. Therefore Pin A0 is a Schmitt Buffer.
I2C Serial Data. Therefore, Pin D0 is a Bidirectional Schmitt Buffer.
Specifications
6.4 Pinouts
The following subsections provide a numerical and alphabetic listing of
the L64780 pins, as well as a pinout package drawing showing the
location of the pins.
6.4.1 Pin List
Table 6.8 numerically lists the L64780 pins and their associated signals.
Pinouts
6-11
Table 6.8
Signal
VDD
XCTR_IN0
XCTR_IN1
XCTR_IN2
MUXIN0
MUXIN1
VSS2
MUXIN2
MUXIN3
MUXIN4
MUXIN5
MUXIN6
VDD
MUXIN7
MUXIN8
MUXIN9
MUXIN10
MUXIN11
VSS2
RESET
MUXIN12
MUXIN13
MUXIN14
MUXIN15
VDD
MUXIN16
TRESETN
TCK
TMS
TDI
VSS2
VSS
TDO
CLKOUT54
DTACKn
INTn
XCTR_OUT0
XCTR_OUT1
XCTR_OUT2
VDD
VDD
VCXOUT
Pin List by Number
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Signal
VSS
VSS2
TTN
TEST0
TEST1
VDD
VDD
CLKMUXIN
SD1_3
SD1_2
SD1_1
VSS
SD1_0
SD0_3
SD0_2
SD0_1
VDD
SD0_0
STARTOUT
DVOUT_LP
DVOUT
MUXOUT26
VSS
MUXOUT25
MUXOUT24
MUXOUT23
MUXOUT22
VDD
MUXOUT21
MUXOUT20
MUXOUT19
MUXOUT18
VSS
MUXOUT17
MUXOUT16
MUXOUT15
MUXOUT14
VDD
VDD
MUXOUT13
MUXOUT12
MUXOUT11
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Signal
Pin
Signal
Pin
MUXOUT10
VSS
MUXOUT9
MUXOUT8
MUXOUT7
MUXOUT6
VDD
MUXOUT5
MUXOUT4
MUXOUT3
MUXOUT2
MUXOUT1
MUXOUT0
VSS
CLK18
PLLVDD
PLLAGND
PLLLP2
PLLVSS
VSS2
P_S
ASn
CSn
READ
D_7
VDD
VDD
D_6
D_5
D_4
D_3
D_2
D_1
D_0
VSS
VSS2
VSS
AFCOUT
VDD
VSS2
A_4
A_3
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
A2
A1
A0
DIGIN_0
DIGIN_1
VDD
DIGIN_2
DIGIN_3
DIGIN_4
VSS
VDD
DIGIN_5
DIGIN_6
TIDDTN
VSS2
DIGIN_7
DIGIN_8
DIGIN_9
PLLTSTCLK
PLLTSTSEL
PROCQ
VDD
VDD
AGCOUT
VSS
ADCPD
ADCGVSS
ADCVSS
ADCVREFP
ADCVREFN
AVIN
IBIAS
ADCVDD
ADCGVDD
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Table 6.9 alphabetically lists the L64780 signals and their associated
pins.
6-12
Specifications
Table 6.9
Pin List by Name
Signal
Pin
Signal
A0
A1
A2
A3
A4
ADCGVDD
ADCGVSS
ADCPD
ADCVDD
ADCVREFN
ADCVREFP
ADCVSS
AFCOUT
AGCOUT
ASn
AVIN
CLK18
CLKMUXIN
CLKOUT54
CSn
D0
D1
D2
D3
D4
D5
D6
D7
DIGIN0
DIGIN1
DIGIN2
DIGIN3
DIGIN4
DIGIN5
DIGIN6
DIGIN7
DIGIN8
DIGIN9
DTACKn
DVOUT
DVOUT_LP
IBIAS
129
128
127
126
125
160
153
152
159
156
155
154
122
150
106
157
99
50
34
107
118
117
116
115
114
113
112
109
130
131
133
134
135
138
139
142
143
144
35
63
62
158
INTn
MUXIN0
MUXIN1
MUXIN2
MUXIN3
MUXIN4
MUXIN5
MUXIN6
MUXIN7
MUXIN8
MUXIN9
MUXIN10
MUXIN11
MUXIN12
MUXIN13
MUXIN14
MUXIN15
MUXIN16
MUXOUT0
MUXOUT1
MUXOUT2
MUXOUT3
MUXOUT4
MUXOUT5
MUXOUT6
MUXOUT7
MUXOUT8
MUXOUT9
MUXOUT10
MUXOUT11
MUXOUT12
MUXOUT13
MUXOUT14
MUXOUT15
MUXOUT16
MUXOUT17
MUXOUT18
MUXOUT19
MUXOUT20
MUXOUT21
MUXOUT22
MUXOUT23
Pinouts
Pin
36
5
6
8
9
10
11
12
14
15
16
17
18
21
22
23
24
26
97
96
95
94
93
92
90
89
88
87
85
84
83
82
79
78
77
76
74
73
72
71
69
68
Signal
Pin
Signal
Pin
MUXOUT24
MUXOUT25
MUXOUT26
PLLAGND
PLLLP2
PLLTSTCLK
PLLTSTSEL
PLLVDD
PLLVSS
PROCQ
READ
RESET
P_S
SD0_0
SD0_1
SD0_2
SD0_3
SD1_2
SD1_0
SD1_1
SD1_3
STARTOUT
TCK
TDI
TDO
TEST0
TEST1
TIDDTN
TMS
TRESETN
TTN
VCXOUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
67
66
64
101
102
145
146
100
103
147
108
20
105
60
58
57
56
52
55
53
51
61
28
30
33
46
47
140
29
27
45
42
40
41
49
59
70
80
81
91
111
123
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
XCTR_IN0
XCTR_IN1
XCTR_IN2
XCTR_OUT0
XCTR_OUT1
XCTR_OUT2
137
149
1
13
25
48
110
132
148
32
43
54
65
75
86
98
119
121
136
151
7
19
31
44
104
120
124
141
2
3
4
37
38
39
6-13
6.4.2 Pin Layout
Figure 6.4 illustrates the L64780 package pin layout.
Package Pin Layout
VDD
XCTR_IN_0
XCTR_IN_1
XCTR_IN_2
MUXIN_0
MUXIN_1
VSS2
MUXIN_2
MUXIN_3
MUXIN_4
MUXIN_5
MUXIN_6
VDD
MUXIN_7
MUXIN_8
MUXIN_9
MUXIN_10
MUXIN_11
VSS2
RESET
MUXIN_12
MUXIN_13
MUXIN_14
MUXIN_15
VDD
MUXIN_16
TRESETN
TCK
TMS
TDI
VSS2
VSS
TDO
CLKOUT54
DTACKn
INTn
XCTR_OUT_0
XCTR_OUT_1
XCTR_OUT_2
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
ADCGVDD
ADCVDD
IBIAS
AVIN
ADCVREFN
ADCVREFP
ADCVSS
ADCGVSS
ADCPD
VSS
AGCOUT
VDD
VDD
PROCQ
PLLTSTSEL
PLLTSTCLK
DIGIN_9
DIGIN_8
DIGIN_7
VSS2
TIDDTN
DIGIN_6
DIGIN_5
VDD
VSS
DIGIN_4
DIGIN_3
DIGIN_2
VDD
DIGIN_1
DIGIN_0
A_0
A_1
A_2
A_3
A_4
VSS2
VDD
AFCOUT
VSS
Figure 6.4
L64780
VDD
VCXOUT
VSS
VSS2
TTN
TEST0
TEST1
VDD
VDD
CLKMUXIN
SD1_3
SD1_2
SD1_1
VSS
SD1_0
SD0_3
SD0_2
SD0_1
VDD
SD0_0
STARTOUT
DVOUT_LP
DVOUT
MUXOUT_26
VSS
MUXOUT_25
MUXOUT_24
MUXOUT_23
MUXOUT_22
VDD
MUXOUT_21
MUXOUT_20
MUXOUT_19
MUXOUT_18
VSS
MUXOUT_17
MUXOUT_16
MUXOUT_15
MUXOUT_14
VDD
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
(PQFPt 160 Package, Top View)
(Body Size 28 x 28 x 3.4 mm)
(Tip to Tip dimension: 31.2 mm)
(External Lead Pitch: 0.65 mm)
( Package Code: UM55)
6-14
Specifications
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VSS2
VSS
D_0
D_1
D_2
D_3
D_4
D_5
D_6
VDD
VDD
D_7
READ
CSn
ASn
P_S
VSS2
PLLVSS
PLLLP2
PLLAGND
PLLVDD
CLK18
VSS
MUXOUT_0
MUXOUT_1
MUXOUT_2
MUXOUT_3
MUXOUT_4
MUXOUT_5
VDD
MUXOUT_6
MUXOUT_7
MUXOUT_8
MUXOUT_9
VSS
MUXOUT_10
MUXOUT_11
MUXOUT_12
MUXOUT_13
VDD
6.5 Mechanical Drawing
Figure 6.5 shows the mechanical drawing for the L64780 160-pin PQFP.
Figure 6.5
Important:
160 PQFP Mechanical Drawing: Top and Side Views
This drawing may not be the latest version. For board layout and manufacturing, obtain the
most recent engineering drawings from your LSI Logic marketing representative by
requesting the outline drawing for package code UM55.
Mechanical Drawing
6-15
Figure 6.6
Important:
6-16
160 PQFP Mechanical Drawing: Detail
This drawing may not be the latest version. For board layout and manufacturing, obtain the
most recent engineering drawings from your LSI Logic marketing representative by
requesting the outline drawing for package code UM55.
Specifications
Appendix A
Programming the
L64780 Using The
Serial Bus Interface
This appendix discusses how to program the L64780 internal registers
and data tables using the serial bus protocol. This appendix is intended
primarily for system programmers who are developing software drivers
using the serial bus.
It consists of the following sections:
•
Section A.1, “Serial Bus Protocol Overview,” page A-2
•
Section A.2, “Programming the Slave Address Using the Serial Bus,”
page A-3
A-1
A.1 Serial Bus Protocol Overview
The multimaster Serial bus interface has two one-bit lines: A0 (Serial
Clock), and D0 (Serial Data). These are connected to the bus (see
Figure A.1). External pullup resistors hold the bus at a logic 1 when it is
not in operation. See the Serial Bus protocol documentation for a
detailed explanation and electrical characteristics. D[7:1] are used to set
the serial bus slave address. When using the serial bus, D[7:1] must be
hardwired to set the appropriate device slave address.
Select the serial bus mode on the L64780 by asserting P_S.
Features of the serial bus protocol include:
•
Two one-bit lines: A0 and D0.
•
D0: Serial Data.
•
A0: serial clock (maximum frequency = 400 kHz).
•
A0 and D0 have external pull-up resistors (the bus is normally
HIGH).
•
The Master always generates the clock, A0, and cycle start/stop
conditions.
Figure A.1 provides an overview illustration of the serial bus.
Figure A.1
Serial Bus Overview
5.0V
5.0V
D0
A0
Serial Bus Compliant Device
A-2
Serial Bus Compliant Device
Programming the L64780 Using The Serial Bus Interface
A.2 Programming the Slave Address Using the Serial Bus
A general call (Master issues a start condition followed by eight zeroes)
is used to address every device on the serial bus. Any device that
requires information to be supplied through this general call must
acknowledge the cycle.
Figure A.2
General Call Address
S 0 0 0 0 0 0 0 0 A X X X X X X X 0 A
General Call Addr.
S: Start Condition
A: Acknowledge Cycle
X: Don’t Care
A.2.1 Write Cycle Using the Serial Bus
The following steps describe a write cycle using the serial bus.
1. The cycle is started by the Master issuing a start condition.
2. The 7-bit slave address is transmitted.
3. The R/W bit is reset to 0 and transmitted, indicating a write cycle.
4. The addressed Slave acknowledges the reception of the slave
address by driving SDA LOW in the ACK cycle.
5. The Master sends the 8-bit address.
6. The addressed Slave acknowledges the reception of the address by
driving SDA LOW in the ACK cycle.
7. The Master sends the 8-bit data.
8. The addressed Slave acknowledges the reception of the data by
driving SDA LOW in the ACK cycle.
9. The Master terminates the cycle by issuing a stop condition.
Programming the Slave Address Using the Serial Bus
A-3
A.2.2 Read Cycle Using the Serial Bus
1. The cycle is started with the start condition.
2. The 7-bit slave address is transmitted.
3. The R/W bit is reset to 0 and transmitted, indicating a write cycle.
4. The addressed Slave acknowledges the reception of the slave
address by driving SDA LOW in the ACK cycle.
5. The Master sends the 8-bit address.
6. The addressed Slave acknowledges the reception of the address by
driving SDA LOW in the ACK cycle.
7. The Master issues another start condition.
8. The 7-bit slave address is transmitted.
9. The R/W bit is set to 1 bit and transmitted, indicating a read cycle.
10. The addressed Slave acknowledges the reception of the slave
address by driving SDA LOW in the ACK cycle.
11. The slave starts transmitting the data.
12. The Master must acknowledge receipt of the data by driving SDA
LOW during the ACK cycle.
13. The Master terminates the cycle by issuing a stop condition.
A-4
Programming the L64780 Using The Serial Bus Interface
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