ETC AHA4524

comtech aha corporation
Product Specification
AHA4524
4K Block Turbo Product Code
Encoder/Decoder
This product is covered under multiple patents held or licensed by Comtech AHA Corporation.
This product is covered by a Turbo Code Patent License from France Telecom - TDF - Groupe des ecoles des telecommunications.
PS4524_0204
A subsidiary of Comtech Telecommunications Corporation
2345 NE Hopkins Court
Pullman WA 99163
tel: 509.334.1000
fax: 509.334.9000
www.aha.com
comtech aha corporation
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.0 Data and Configuration Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Configuration Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Configuration Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Configuration Cycle Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Decoder Status Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Decoder Status Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Encoder and Decoder - Synchronous I/O - Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Encoder and Decoder Synchronous - Half Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 Bus Mode - Half Duplex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Decoder Bus Interface, Encoder Synchronous Interface - Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 CRC Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 TPC Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 Encoder Code Shortening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 Helical Interleaver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3 Internal Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.4 Encoder Rapid Code Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.5 Encoder Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.0 Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.1 Channel Input Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 TPC Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1 Helical Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.2 Code Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.3 Decoder Code Shortening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.4 Corrections Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.5 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.6 CRC Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.7 Decoder Rapid Code Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.8 Decoder Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2.9 Code Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.0 Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.0 General Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Register List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 User Data Formatting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3.1 CRC and Scrambler Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.4 Code Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4.1 TPC Constituent Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4.2 Block Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4.3 Buffer Configuration (Encoder Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4.4 Shortening Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4.5 Feedback (Decoder Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4.6 Iterations (Decoder Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PS4524_0204
A subsidiary of Comtech Telecommunications Corporation
i
comtech aha corporation
7.5
8.0
9.0
10.0
11.0
12.0
13.0
14.0
Channel Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5.1 Quantization (Decoder Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6 Data Input/Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.6.1 Transfer Word Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.7 Control and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.7.1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.7.2 Status and Correction Count (Decoder Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.7.3 Actual Iterations (Decoder Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.8.1 Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 System Control and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 Unencoded Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.3 Encoded Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.4 Channel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.5 Decoded Data Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.1 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11.1 SYSCLK Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11.2 U_CLK, E_CLK, C_CLK, D_CLK Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.3 U_WR_N, E_RD_N, C_WR_N, D_RD_N Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.4 Synchronous Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.5 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.6 Reset_n Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.1 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Appendix A:
ii
Vad Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
A subsidiary of Comtech Telecommunications Corporation
PS4524_0204
comtech aha corporation
List of Figures
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Figure 43:
Figure A1:
PS4524_0204
AHA4524 Functional Block Diagram ................................................................................................... 2
Configuration Cycle Followed by Block 1 ............................................................................................ 3
Configuration Header for Consecutive Blocks .................................................................................... 4
Fixed Configuration Mode ................................................................................................................... 4
Configuration Example for Gaps Between Configuration Writes ........................................................ 4
Full Duplex Connection Diagram ........................................................................................................ 6
Synchronous Data/Configuration Communication Timing - Start of Block .......................................... 8
Synchronous Data/Configuration Communication Timing - End of Block ........................................... 9
Half Duplex Connection Diagram ........................................................................................................ 9
Half Duplex Connection Diagram ........................................................................................................ 10
Bus Interface Data/Configuration Communication Timing - Start of Block .......................................... 12
Full Duplex Connection Diagram ........................................................................................................ 13
Encoder Block Diagram ...................................................................................................................... 14
CRC Encoder ...................................................................................................................................... 14
2D TPC Encoded Block with CRC ...................................................................................................... 15
Scrambler ............................................................................................................................................ 15
Structure of Shortened Code .............................................................................................................. 16
Structure of Shortened 3D Block ......................................................................................................... 17
Input Block .......................................................................................................................................... 17
2D Interleaving .................................................................................................................................... 17
Encoded/Interleaved Data Output ....................................................................................................... 18
Encoder Rapid Code Reconfiguration with Helical Interleaving Disabled ........................................... 19
Encoder Rapid Code Reconfiguration with Helical Interleaving Enabled ............................................ 19
C_DATA Interface ............................................................................................................................... 20
Decoder Rapid Code Reconfiguration ................................................................................................ 21
Pinout .................................................................................................................................................. 40
Signal Timing vs. Output Load ............................................................................................................ 42
SYSCLK Clock Timing ........................................................................................................................ 43
Clock Timing ....................................................................................................................................... 44
Strobe Timing ...................................................................................................................................... 44
Encoder Interface Data Input Timing .................................................................................................. 45
Decoder Interface Data Input Timing .................................................................................................. 46
Encoder Interface Data Output Timing Using Chip Select .................................................................. 47
Encoder Interface Data Output Timing ................................................................................................ 48
Decoder Interface Data Output Timing Using Chip Select .................................................................. 49
Decoder Interface Data Output Timing ............................................................................................... 50
Encoder Bus Interface Data Input Timing ........................................................................................... 51
Decoder Bus Interface Data Input Timing ........................................................................................... 52
Encoder Bus Interface Data Output Timing ........................................................................................ 53
Decoder Bus Interface Data Output Timing ........................................................................................ 53
RESET_N Timing ................................................................................................................................ 54
Package Dimensions - Top View ........................................................................................................ 55
Package Dimensions - Cross Section View ........................................................................................ 55
Example External Circuit Component Configuration ........................................................................... 58
A subsidiary of Comtech Telecommunications Corporation
iii
comtech aha corporation
List of Tables
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iv
Recommended CRC Polynomials ........................................................................................................... 15
Partial Code List and Decoder Datapath Latency .................................................................................... 23
Partial Code List and Performance - Synchronous Interface ................................................................... 23
Partial Code List and Performance - Bus Interface ................................................................................. 24
Register Bits - Alphabetical ..................................................................................................................... 25
Summary of Code Shortening Rules ....................................................................................................... 31
Pinout - Pin Number Order ...................................................................................................................... 39
SYSCLK Clock Timing with PLLBYPASS = 0 ......................................................................................... 43
SYSCLK Clock Timing with PLLBYPASS = 1 ......................................................................................... 43
Clock Timing ............................................................................................................................................ 44
Strobe Timing with PLLBYPASS = 0 ....................................................................................................... 44
Encoder Interface Data Input Timing ....................................................................................................... 45
Decoder Interface Data Input Timing ...................................................................................................... 46
Encoder Interface Data Output Timing Using Chip Select ...................................................................... 47
Encoder Interface Data Output Timing ................................................................................................... 48
Decoder Interface Data Output Timing Using Chip Select ...................................................................... 49
Decoder Interface Data Output Timing .................................................................................................... 50
Encoder Bus Interface Data Input Timing ............................................................................................... 51
Decoder Bus Interface Data Input Timing ............................................................................................... 52
Encoder Bus Interface Data Output Timing ............................................................................................. 53
Decoder Bus Interface Data Output Timing ............................................................................................ 53
RESET_N Timing .................................................................................................................................... 54
TQFP (Thin Quad Flat Pack) 7 x 7 mm Package Dimensions ................................................................ 56
A subsidiary of Comtech Telecommunications Corporation
PS4524_0204
comtech aha corporation
1.0
INTRODUCTION
The AHA4524 device is a single-chip Turbo
Product Code (TPC) Forward Error Correction
(FEC) Encoder/Decoder. This device integrates
both a TPC encoder and decoder, and operates in
full or half duplex modes. In addition to TPC
coding, the device includes helical interleaving,
CRC computation, and data scrambling. Each of the
functional blocks can be independently bypassed,
refer to the functional block diagram in Figure 1.
The encoder and decoder accept data through an
interface designed to connect directly to a DSP
either through a synchronous serial port or the data
bus. Separate chip select signals are provided on the
encoder and decoder to allow half duplex operation.
Encoder and decoder configuration registers are
written and read through the same interface as the
data. Configuration registers may only be accessed
at the start of every block transfer.
The encode datapath with all functional blocks
enabled computes and inserts CRC bits, scrambles
the data, inserts error correction code (ECC) bits,
and helically interleaves the data. The decoder
datapath is the reverse of the encoder datapath. With
all functional blocks enabled, the received data is
helically deinterleaved before decoding. The
decoder output is descrambled and the CRC is
computed to verify data integrity. Decoded data is
then output in a serial bit stream.
The decoder input interface includes an option
to accept 4 bit parallel soft metric data symbols. The
parallel decoder input is used to support symbol per
transfer for fast channel input rates.
PS4524_0204
1.1
FEATURES
PERFORMANCE:
• 60 Mbit/sec channel rate and 50 Mbit/sec payload
data rate for (64,57)x(64,57) code with 3
iterations
• Integrated 16 bit scrambler and descrambler
• Integrated 32 bit CRC computation and
verification
• Supports two dimensional (2D) and three
dimensional (3D) Turbo Product Codes
• Supports 2D Enhanced Turbo Product Codes
• Correction count for channel SNR estimation
FLEXIBILITY:
• Code Rates from 0.25 to 0.97
• Encoded Block Sizes from 64 bits to 4K bits
• Programmable code shortening supports exact
block sizes
• Programmable decoder input quantization for up
to 4 bit wide soft metrics
• Programmable Iterations up to 255 per block
• 4 programmable block configurations which are
selectable for fast code changing
• On chip PLL allows low frequency system clock
(SYSCLK)
CHANNEL INTERFACE:
• Synchronous serial input and output ports
designed to be compatible with DSP serial ports
• Bus mode input and output ports designed to be
compatible with a DSP bus
• Chip selects on encoder and decoder ports for full
or half-duplex operation
• Pin selectable ready and accept control signal
polarity
• Decoder supports 4 bit parallel soft metric input
data for fast decode operation
• Block status is optionally output at the end of
every decoded block to provide correction and
CRC error information
SYSTEM INTERFACE:
• Datapath is used for accessing the AHA4524
configuration registers through the data ports
ELECTRICAL:
• 3.3V I/O, 1.8V core operation
• 5V tolerant inputs
• TTL signal compatible
• 7 mm x 7 mm, 64 pin, TQFP Package
• Commercial or Industrial temperature rating
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Page 1 of 58
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1.2
GLOSSARY OF TERMS
1.3
Block (TPC) –
A TPC error correction block, including
user data bits, CRC bits, and TPC error
correction bits.
Channel Rate The bit rate output from the encoder, or
input to the decoder, including all user data
bits, CRC bits, and TPC error correction
bits.
Data Rate The bit rate input to the encoder, or output
from the decoder, including only user data
bits. This is sometimes referred to as the
payload data rate.
Figure 1:
DOCUMENT CONVENTIONS
The following are formatting examples for
specific document elements.
– SIGNAL OR PINS - Electrical connections
available to the system.
– Register Bit - Bit(s) within a register. When the
same register exists in both the encoder and
decoder, an ‘x’ is used to designate both register
bits, as in ECRCEnable and DCRCEnable.
– Hex values are represented with a prefix of “0x,”
such as Register “0x00.” Binary values are
represented with a prefix of “0b”.
– Active low signals have “_N” appended to the
signal name, as in E_RD_N.
– Signals labelled “= 1” are tied to Vddio. Signals
labelled “= 0” are tied to ground.
– “configuration header or footer bit” Configuration header control bits are listed in
quotes, as in “last” or “rwn”.
AHA4524 Functional Block Diagram
ENCODER
U_DATA
E_DATA
I/O
Formatter
Configuration
Registers
CRC
Computation
Scrambler
eTPC
Helical
Interleaver
Encoder
DECODER
C_DATA
D_DATA
I/O
Formatter
Configuration
Registers
Helical
Deinterleaver
CRC
Verification
eTPC
Decoder
Descrambler
AHA4524
Page 2 of 58
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2.0
DATA AND CONFIGURATION
INPUT/OUTPUT
The input/output ports of the AHA4524 chip
may be configured to operate in synchronous mode
or bus mode. Synchronous mode signals consist of a
continuous port clock, a frame sync signal, and data.
Bus mode signals consist of a read or write strobe,
and data.
Bus mode is selected for the encoder when pin
E_MODE = 1 on the rising edge of RESET_N, and
is selected for the decoder when pin D_MODE = 1
on the rising edge of RESET_N. Synchronous
mode is selected for the encoder when pin
E_MODE = 0 and for the decoder when pin
D_MODE = 0.
The interface modes are independent. The
encoder is not required to use the same interface
mode as the decoder. The input port can not be
configured to use a different mode than the output
port within the encoder or decoder.
The interfaces into and out of the encoder and
out of the decoder are always serial in either mode.
The soft decision channel data into the decoder may
be input symbol per transfer, up to 4 bits parallel, in
either mode. The parallel channel input is selected
when pin DPARINPUT = 1 on the rising edge of
RESET_N. When pin DPARINPUT = 0, the
channel data is input serially.
A summary of the differences between
synchronous and bus interface modes is:
1)Synchronous mode requires a continuous not gated - port clock. Bus mode uses a data
strobe.
2)Synchronous mode requires a frame sync
signal to assert 1 clock before data on each
block. Bus mode does not require a frame
sync.
3)Data input and output can be faster in the
synchronous mode than in bus mode. The
bus mode data strobe is limited to the
SYSCLK frequency and the synchronous
port clock allows an input clock rate of
1.9*SYSCLK (refer to Section 11.2
U_CLK, E_CLK, C_CLK, D_CLK Clock
Timing and Section 11.3 U_WR_N,
E_RD_N, C_WR_N, D_RD_N Strobe
Timing).
Figure 2:
With the exception of the 4 bit parallel channel
input to the decoder, the encoder interface is
identical to the decoder interface. The following
sections describe the interface in terms of the
decoder, but all control descriptions and signal
timing, except where explicitly stated, apply to the
encoder signals. The encoder and decoder are
shown on all connection diagrams.
2.1
CONFIGURATION WRITES
The AHA4524 configuration registers are split
into 2 sets of register banks, one for the encoder
datapath functions and one for the decoder datapath
functions. Each register bank contains 4 sets of
block configuration data to allow fast configuration
changes between blocks. The 4 sets of configuration
data are referred to as config 0, config 1, config 2,
and config 3 in this document.
All encoder configuration registers are written
through the encoder unencoded data input port. All
decoder configuration registers are written through
the decoder channel data input port. The
configuration registers can be written before the
start of a block transfer - not during a block transfer.
Configuration data is written in a 16 bit
configuration cycle format (refer to Section 2.3
Configuration Cycle Format). When writing
configuration data to the decoder and the decoder is
configured for a parallel input by setting pin
DPARINPUT = 1, the configuration data must be
input 4 bits per transfer. When writing the
configuration in parallel, the first of 4 data transfers
expects bit 15 to be input on CDATA[3] down to bit
12 input on CDATA[0]. All 4 CDATA inputs are
always used when writing configuration data in
parallel.
The configuration cycle starts with a “rwn” bit
to indicate whether the current configuration cycle
is a read or write cycle, and is followed by the “last”
bit to indicate that the current configuration cycle is
the last configuration write cycle. Configuration
cycles are expected to continue until a cycle is
received with the “last” bit set.
If the “last” bit is set, the AHA4524 expects
data to immediately follow the current
configuration cycle unless the last configuration
cycle writes a one to the NoBlock bit, see
configuration Section 7.7.1 Control. An example of
the configuration cycle is shown in Figure 2.
Configuration Cycle Followed by Block 1
C_FS, U_FS
C_DATA, U_DATA
PS4524_0204
cycle 1
cycle 2
cycle 3
last cycle
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block 1
Page 3 of 58
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Figure 3:
Configuration Header for Consecutive Blocks
C_FS, U_FS
C_DATA, U_DATA
Figure 4:
header 1
block 1
header 2
block 2
Fixed Configuration Mode
C_FS, U_FS
C_DATA, U_DATA
cycle 1 cycle 2 cycle 3 cycle 4
block 1
last
block 2
block 3
C_ACPT, V_ACPT
Figure 5:
Configuration Example for Gaps Between Configuration Writes
Last Bit Set
No Block Set
DATA
cycle 1
Reg 26
cycle 2
Reg 26
cycle 3
Reg 26
FS
ACPT
The “last” bit is followed by a 6 bit address and
then 8 bits of data to be written to the specified
address. Refer to Section 7.0 Register Descriptions
for configuration register functions and addresses.
In general, at least one configuration write cycle
must be attached as a header to each input block. A
minimal input header contains a write to
configuration address 0x26 to select which set of
block configuration to use for the attached block.
Refer to configuration register Section 7.7.1
Control. An example of the configuration header is
shown in Figure 3.
Some AHA4524 applications may only require
a single TPC code for every block. For these
applications, the AHA4524 may be configured for a
fixed configuration mode with only 1 block code,
and no configuration cycle headers are required
with the data blocks. An example of the fixed
configuration mode is shown in Figure 4.
If system constraints make it necessary to allow
for dead time in between configuration writes you
may use the configuration timing shown in Figure 5.
Cycle 1, 2, 3 are normal configuration writes
followed by a register 0x26 write. Register 0x26
must have the “last” bit set and the xNoBlock bit
set.
The fixed configuration mode is selected during
the initial configuration following RESET_N.
When a 1 is written to the xNoConfig bit in the
control register (Refer to Section 7.7.1 Control), all
data blocks are received as config 0, and no
Page 4 of 58
configuration headers are expected. After the chip is
configured in fixed configuration mode, there is no
access to the configuration registers until
RESET_N is asserted.
2.2
CONFIGURATION READS
All encoder configuration read requests are
written through the encoder unencoded data input
port. All decoder configuration read requests are
written through the decoder channel data input port.
The encoder configuration registers can only be
read when the encoder datapath is empty. The
decoder configuration registers can only be read
when the decoder datapath is empty. The AHA4524
has a general output pin that may be used to monitor
the datapath empty status. Refer to Section 7.7.1
Control.
All encoder configuration registers are read
from the encoder encoded data output port. All
decoder configuration registers are read from the
decoder decoded data output port.
A configuration data read request is written in a
16 bit configuration cycle format (refer to Section
2.3 Configuration Cycle Format). The
configuration cycle starts with a “rwn” bit to
indicate whether the current configuration cycle is a
read or write cycle. When the “rwn” bit is set, the
configuration cycle is a read request and it is by
default the last configuration cycle. The “last” bit is
irrelevant in a configuration read because each read
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must wait for the read data to be output before a new
read can be requested. Data can not directly follow
a read configuration request.
The “last” bit is followed by a 6 bit address to
specify which register to read. The 8 bits of data that
2.3
follow the address field of the configuration read
cycle are don’t cares, but they must be input to finish
the configuration cycle. Refer to Section 7.0
Register Descriptions for configuration register
functions and addresses.
CONFIGURATION CYCLE FORMAT
Bit 15 is input first, bit 0 is input last.
bit15 bit14 bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
rwn last a[5]
a[4]
a[3]
a[2]
a[1]
a[0]
d[7]
d[6]
d[5]
d[4] d[3] d[2] d[1]
d[0]
“rwn” -
Read/Write_not. When “rwn” = 1, the configuration cycle is a read cycle. When “rwn” = 0, the
configuration cycle is a write cycle.
“last” -
Last configuration cycle. When set, the current configuration cycle is the last configuration
cycle before data begins. When cleared, the current configuration cycle will be followed by
another configuration cycle.
“a[5:0]” -
Configuration address. Address of configuration read or write.
“d[7:0]” -
Configuration data. When “rwn” = 0, this is the data to be written to the addressed configuration
register. When “rwn” = 1, this data is a don’t care.
2.4
DECODER STATUS OUTPUT
The AHA4524 has the option to output status
information with each decoded block. There is no
option to output any status information with
encoded blocks.
The status of a decoded block is output as 16
bits at the end of every decoded block when the
DStatus configuration bit is set to 1, see Section
2.5
7.7.1 Control. The structure of the status output is
shown in Section 2.5 Decoder Status Output
Format. The status is output in serial, msb first.
The status includes a parity error flag “perr”
which is asserted when the CRC is enabled and the
output block failed the CRC verification.
The last status information is the number of
corrections “c[11:0]”. This is a count of the number
of bit errors corrected in the current block, including
user data, inserted CRC bits, and ECC bits.
DECODER STATUS OUTPUT FORMAT
Bit 15 is output first, bit 0 is output last.
bit15 bit14 bit13
bit12
bit11
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
res
perr
c[11] c[10] c[9]
c[8]
c[7]
c[6]
c[5]
c[4]
c[3]
c[2]
c[1]
c[0]
“perr” -
bit10
Parity error. Asserted when CRC is enabled and the output block failed the CRC verification.
“c[11:0]” - Correction count. The number of bit errors corrected in the current block including user data,
inserted CRC bits, and ECC bits.
PS4524_0204
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2.6
ENCODER AND DECODER - SYNCHRONOUS I/O - FULL DUPLEX
An AHA4524 synchronous interface full
duplex connection diagram is shown in Figure 6.
Data blocks and configuration information are input
through the U_DATA port when encoding or the
C_DATA port when decoding.
The soft decision channel data into the decoder
is serially input when DPARINPUT = 0 on the
rising edge of RESET_N, which reduces the input
rate by up to a factor of 4 when a 4 bit soft metric is
used. The channel input port may be configured to
allow 4 bit parallel input on C_DATA when
DPARINPUT = 1 on the rising edge of RESET_N.
When DPARINPUT = 1, the C_DATA port is
configured in parallel mode and the configuration
data is expected to be received in 4 bit parallel.
When DPARINPUT = 0, the C_DATA port resets
into serial mode and expects to receive
configuration data serially.
Figure 6:
The synchronous interface timing for the
decoder signals is shown in Figures 7 and 8. The
signal timing for the encoder is similar.
A data or configuration write is started when
C_FS is asserted for one C_CLK cycle. The C_FS
signal is a sync signal that is asserted once for every
block when the DWordEqBlk configuration bit is
set to 1 or asserted once for every word when the
DWordEqBlk configuration bit is set to 0, see
Section 7.6.1 Transfer Word Size. The word size is
configured using the DWordSize[4:0] register also
shown in Section 7.6.1 Transfer Word Size. The
DWordSize[4:0] register resets to 16 bits per word.
Figure 32 shows the input timing requirements for
C_FS.
Full Duplex Connection Diagram
E_CS_N
GND
CLKX
U_CLK (U_WR_N)
DX
U_DATA
FSX
U_FS
U_ACPT
synchronous Port 0
CLKR
Encoder
E_CLK (E_RD_N)
DR
E_DATA
FSR
E_FS
E_RDY
Serial I/F
AHA4524
D_CS_N
GND
C_CLK (C_WR_N)
CLKX
DX
C_DATA
FSX
C_FS
C_ACPT
synchronous Port 1
CLKR
Decoder
D_CLK (D_RD_N)
DR
D_DATA
FSR
D_FS
D_RDY
DPARINPUT
D_MODE
E_MODE
GND
Page 6 of 58
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All AHA4524 configuration is done
immediately following the first C_FS of a block and
the interface remains in the configuration mode until
a configuration cycle is input with the “last” bit set.
The structure of a configuration cycle is shown in
Section 2.3 Configuration Cycle Format and in the
timing diagram Figure 7 in the C_DATA input data
stream.
In Figure 7, A[3:0] and B[3:0] following the
configuration cycle indicate the start of the data
block where A is a 4 bit soft metric and B is a 4 bit
soft metric.
If the configuration cycle is a read request, the
read data is available on D_DATA on the D_CLK
cycle following when the D_FS output signal is
asserted for one D_CLK cycle. Data can not follow
a configuration read and decoder configuration reads
are only allowed when the decoder datapath is empty.
The read data must be read from the D_DATA port
before another configuration cycle is started.
The D_FS signal timing is shown in Figures 7
and 8, the electrical characteristics are shown in
Figure 35. D_FS asserts to indicate that the block is
finished processing and the output data will start on
the next D_CLK cycle. The D_FS signal is a sync
signal that is asserted once for every block when the
DWordEqBlk configuration bit is set to 1 or
asserted once for every word when the
DWordEqBlk configuration bit is set to 0, see
Section 7.6.1 Transfer Word Size. The word size is
configured using the DWordSize[4:0] register also
shown in Section 7.6.1 Transfer Word Size. The
DWordSize[4:0] register resets to 16 bits per word.
The output data is read serially through the
D_DATA port.
PS4524_0204
D_RDY asserts with the D_FS at the start of a
block and stays asserted until the last data, including
block status, is clocked out of the decoder (see
Figures 7 and 8). Note that the encoder does not
output a block status footer. D_RDY is not required
for systems where the receive port is set up to expect
a certain output block size, but it may be used in
systems that do not count the bits in the received
block.
C_ACPT asserts when the input buffer is ready
to accept a block and is deasserted after the data
portion of the block transfer is started or a
configuration read is started (see Figures 7 and 8).
This signal may be used to allow the decoder to
process more than one block at a time. C_ACPT is
not required for systems that process one block at a
time, i.e. the first block is input, processed, and
output before a second block is input.
The synchronous interface requires continuous
port clocks C_CLK and D_CLK. Gated port clocks
are not allowed. The continuous D_CLK
automatically fills any padding required by a serial
receive port.
The following timing diagrams Figure 7 and
Figure 8 show a block input and output through the
decoder in serial mode (DPARINPUT = 0). The
C_FS and D_FS signals shown in the following
diagrams are shown assuming DWordEqBlk is set.
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Figure 7:
Synchronous Data/Configuration Communication Timing - Start of Block
Start of Block - Configuration Write
C_CLK
(input)
C_FS
(input)
C_DATA
(input)
rwn last a[5] a[4] a[3] a[2] a[1] a[0] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] A[3] A[2] A[1] A[0] B[3] B[2] B[1] B[0] C[3]
channel data
configuration cycle
C_ACPT
(output)
Decoded Start of Block - Output Data (after decoder latency)
D_CLK
(input)
D_FS
(output)
D_DATA
(output)
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
xx
xx
xx
q
r
s
t
u
v
w
x
y
decoded data
D_RDY
(output)
Start of Block - Configuration Read
C_CLK
(input)
C_FS
(input)
C_DATA
(input)
C_ACPT
rwn last a[5] a[4] a[3] a[2] a[1] a[0] xx
configuration read
xx
xx
xx
xx
rwn last a[5] a[4] a[3]
configuration write
c_data is a don’t care on read
(output)
Output Configuration Read Data
D_CLK
(input)
D_FS
(output)
D_DATA
(output)
D_RDY
r[7] r[6] r[5] r[4] r[3] r[2] r[1] r[0]
read data
a
b
c
d
e
f
g
h
i
next block data
(output)
Page 8 of 58
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Figure 8:
Synchronous Data/Configuration Communication Timing - End of Block
End of Block Write
C_CLK
(input)
C_FS
(input)
C_DATA
(input)
Z[3] Z[2] Z[1] Z[0]
rwn last a[5] a[4] a[3] a[2] a[1] a[0] d[7]
data end
next block configuration
C_ACPT
(output)
Decoded End of Block Output Data
D_CLK
(input)
D_FS
data start
(output)
D_DATA
(output)
x
y
z
s[15] s[14] s[13] s[12] s[11] s[10] s[9] s[8] s[7] s[6] s[5] s[4] s[3] s[2] s[1] s[0]
data end
a
block status
D_RDY
b
c
next
block
(output)
2.7
ENCODER AND DECODER SYNCHRONOUS - HALF DUPLEX
This interface is the same as the full duplex synchronous mode, except the E_CS_N and D_CS_N inputs
are used to switch between the encoder and decoder.
Figure 9:
Half Duplex Connection Diagram
GOUT[1:0]
E_CS_N
CLKX
U_CLK (U_WR_N)
DX
U_DATA
U_FS
FSX
U_ACPT
synchronous Port 0
Encoder
E_CLK (E_RD_N)
CLKR
DR
E_DATA
FSR
E_FS
E_RDY
AHA4524
D_CS_N
C_CLK (C_WR_N)
C_DATA
C_FS
C_ACPT
Decoder
D_CLK (D_RD_N)
D_DATA
D_FS
D_RDY
DPARINPUT
D_MODE
E_MODE
GND
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The differences in the communication timing
between the full duplex and half duplex
synchronous configurations are the tristated D_FS
and D_DATA outputs when the decoder D_CS_N is
not asserted, and the tristated E_FS and E_DATA
outputs when the encoder E_CS_N is not asserted.
Refer to the full duplex synchronous configuration
Section 2.6 Encoder and Decoder - Synchronous I/
O - Full Duplex for communication timing
diagrams.
2.8
BUS MODE - HALF DUPLEX
The AHA4524 bus interface half duplex
connection diagram is shown in Figure 10. The bus
interface is selected for the encoder when
E_MODE = 1 and is selected for the decoder when
D_MODE = 1. Data blocks and configuration
information are input through the U_DATA port
when encoding or the C_DATA port when
decoding.
The bus mode interface allows a 4 bit parallel
channel input through the C_DATA port to allow
soft metrics to be written to the decoder at a rate of
one symbol per transfer. The interfaces to
D_DATA, U_DATA, and E_DATA are serial.
When bus mode is selected at reset, the status of the
DPARINPUT pin determines if the C_DATA port
is configured in serial or 4 bit parallel mode. When
DPARINPUT = 1 at reset, the C_DATA port is
configured in 4 bit parallel mode and the first
configuration cycle is expected to be received in 4
bit parallel.
Figure 10: Half Duplex Connection Diagram
CS, ADDR
E_CS_N
U_CLK (U_WR_N)
WR_N
DATA[3:0]
U_DATA
U_FS
U_ACPT
Bus I/F
Encoder
E_CLK (E_RD_N)
RD_N
E_DATA
E_FS
INT0
INT1
INT2
E_RDY
AHA4524
INT3
D_CS_N
C_CLK (C_WR_N)
C_DATA[3:0]
C_FS
C_ACPT
Decoder
D_CLK (D_RD_N)
D_DATA
D_FS
Vddio
D_RDY
DPARINPUT
D_MODE
E_MODE
Page 10 of 58
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The bus interface timing for the decoder signals
is shown in Figure 11. The signal timing for the
encoder is typical.
A data or configuration write cycle is started
when C_WR_N is asserted low. There is no block
start signal in bus mode. The C_WR_N signal is a
write strobe signal, with data being registered on the
rising edge (see Figure 38).
All configuration is done immediately
following reset or immediately following the end of
an input block. The AHA4524 counts the number of
input data bits and compares the input count to the
DBlockSize configuration setting (see Section 7.4.2
Block Size) to find the end of an input block.
The interface remains in the configuration
mode until a configuration cycle is input with the
“last” bit set. The structure of a configuration cycle
is shown in Section 2.3 Configuration Cycle
Format. The configuration cycle is shown as c[3:0]
in Figure 11 in the C_DATA input stream. Note that
the encoder does not have the parallel input option
and all configuration bits must be input serially. The
first 16 bits (4 writes) in the C_DATA stream are
configuration write bits with bits (15:11) written
first and bits (3:0) written last. The configuration
starts with a “rwn” (read/write_not) bit and is
followed by a “last” bit which indicates that the
current configuration cycle is the last configuration
cycle. The “last” bit is followed by a 6 bit address
a[5:0] and then the data d[7:0] to be written to the
address.
The AHA4524 expects data to immediately
follow the last configuration write cycle unless the
last configuration cycle writes a one to the NoBlock
bit (see configuration Section 7.7.1 Control). A and
B following the configuration cycle indicate the start
of the data block where A is a 4 bit soft metric and
B is a 4 bit soft metric.
If the configuration cycle is a read request, the
read data is available on D_DATA when D_RDY is
asserted. The configuration data is read when
D_RD_N is asserted low and the data is valid until
the D_RD_N rising edge (see Figure 40). Data can
not follow a configuration read and decoder
configuration reads are only allowed when the
decoder datapath is empty. Each configuration read
is considered a last configuration cycle similar to a
last configuration write cycle with the NoBlock bit
set. The read data must be read from the D_DATA
port before another configuration cycle is started.
D_RDY asserts when valid data is available to
be read at the output and stays asserted until the last
data, including block status, is strobed out of the
decoder (see Figure 11). D_RDY can be monitored
to know when to start an output read, or the output
can be read after decoder block latency number of
PS4524_0204
SYSCLKs. The decoder latency calculations are
shown in Section 4.2.8 Decoder Latency. Any
D_RD_N strobes beyond the end of a block are
ignored until the D_RDY signal is asserted.
C_ACPT asserts when the input buffer is ready
to accept a block and deasserts after the data portion
of the block transfer is started or a configuration
read is started (see Figure 11). This signal may be
used to allow the decoder to process more than one
block at a time. C_ACPT is not required for
systems that process one block at a time, i.e. the first
block is input, processed, and output before a
second block is input.
The status of the decoded block is output in 16
bits at the end of every decoded block when the
DStatus configuration bit is set to 1, see control
Section 7.7.1 Control. The structure of the status
output is shown in Section 2.5 Decoder Status Output
Format and partially in the timing diagram Figure 11
in the D_DATA output data stream as s[8:0] (s[15:9]
are not shown). There is not an option to output status
information at the end of encoded blocks.
In bus mode, the AHA4524 is a slave to the
system. The C_WR_N and D_RD_N signals are
both inputs to AHA4524. Blocks do not need to be
read or written in a continuous stream in bus mode.
See Section 4.2.7 Decoder Rapid Code
Reconfiguration for fast code change details.
The signal differences between synchronous
mode and bus mode are:
a) the C_CLK and U_CLK inputs become
C_WR_N and U_WR_N in bus mode,
b) the D_CLK and E_CLK inputs become
D_RD_N and E_RD_N inputs in bus
mode,
c) the D_DATA bus is tristated when
D_RD_N is not asserted, and
d) the E_DATA bus is tristated when
E_RD_N is not asserted.
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Figure 11: Bus Interface Data/Configuration Communication Timing - Start of Block
Start of Block - Configuration Write
C_WR_N
(input)
C_DATA
c[3]
(input)
c[2]
c[1]
c[0]
A
B
C
D
configuration
C_ACPT
E
F
G
H
i
j
k
l
c[3]
c[2]
c[1]
c[0]
data
(output)
Decoded Start of Block Output Data (after decoder latency)
D_RD_N
(input)
D_DATA
a
b
c
d
e
f
g
h
(output)
decoded data
D_RDY
(output)
Start of Block - Configuration Read
C_WR_N
(input)
C_DATA
c[3]
(input)
c[2]
c[1]
c[0]
configuration
configuration
C_ACPT
(output)
Output Configuration Read Data
D_RD_N
(input)
D_DATA
r[7]
(output)
r[6]
r[5]
D_RDY
r[4]
r[3]
r[2]
r[1]
r[0]
a
configuration read data
(output)
b
c
next data block
End of Block Write
C_WR_N
(input)
C_DATA
(input)
X
Y
Z
c[3]
data end
c[2]
c[1]
c[0]
configuration
A
B
C
data
C_ACPT
(output)
Decoded End of Block Output Data
D_RD_N
(input)
D_DATA
(output)
s[8]
s[7]
s[6]
s[5]
s[4]
s[3]
s[2]
s[1]
s[0]
status footer
D_RDY
a
b
next
block
(output)
Page 12 of 58
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2.9
DECODER BUS INTERFACE, ENCODER SYNCHRONOUS INTERFACE - FULL
DUPLEX
The full duplex connection diagram shown in
Figure 12 is used to show the flexibility of the
AHA4524 interface. The decoder uses the bus
connection with a 4 bit parallel channel input, while
the encoder uses the synchronous port.
In this configuration, the C_ACPT output is used
to signal that the C_DATA input is ready to accept
data. The AHA4524 decoder resets into 4 bit parallel
mode when DPARINPUT = 1, so the first decoder
configuration write must be done in 4 bit parallel.
Fast code changing allows the decoder to input
one block type while processing a second block type
while outputting a third block type, refer to Section
4.2.7 Decoder Rapid Code Reconfiguration. The
D_RDY signal in this configuration can be used as
a data valid to signal when a block is finished
unloading.
Figure 12: Full Duplex Connection Diagram
E_CS_N
GND
U_CLK (U_WR_N)
CLKX
U_DATA
DX
U_FS
FSX
synchronous Port 0
U_ACPT
Encoder
E_CLK (E_RD_N)
CLKR
DR
E_DATA
FSR
E_FS
E_RDY
AHA4524
CS, ADDR
D_CS_N
WR_N
C_CLK (C_WR_N)
DATA[3:0]
C_DATA
C_FS
Bus I/F
INT1
C_ACPT
Decoder
D_CLK (D_RD_N)
RD_N
D_DATA
D_FS
D_RDY
INT0
Vddio
DPARINPUT
D_MODE
E_MODE
GND
PS4524_0204
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3.0
ENCODER
Figure 13: Encoder Block Diagram
User
Data
Encoded
Data
HELICAL
INTERLEAVER
U_DATA
CRC
ENCODER
SCRAMBLER
PRBS
E_DATA
TPC
ENCODER
Figure 13 shows a block diagram of the encode
path. Note that all of the blocks in the encode path
except the helical interleaver operate by only
inserting or modifying data in the stream. Therefore,
the entire encode path has low latency.
Data is input serially through U_DATA. The
CRC engine computes a CRC over each block of
data which is inserted at the end of the uncoded data
block. This data is scrambled by exclusive-ORing
with the output of a Pseudo Random Binary
Sequence (PRBS) generator. The scrambler ensures
adequate bit transitions in the data stream, which are
often required to allow improved DC balance and to
accelerate clock recovery in the demodulator. The
scrambled data is input to a TPC encoder, which
computes ECC bits and inserts them at the
appropriate locations in the data stream.
The helical interleaver improves burst error
performance of the decoder. However, it adds a one
block latency to the datapath. The encoded block is
serially output through E_DATA.
3.1
CRC ENCODER
The cyclic redundancy check (CRC) encoder is
a 32 bit linear feedback shift register, with a
programmable polynomial. Figure 14 shows a
diagram of the shift register. Each TPC block has a
separate CRC encoded, with the resultant CRC bits
appended to the block.
The polynomial for the CRC encoder is written
into the ECRCPoly register. The highest order of
the polynomial (defined by ECRCSize) is assumed
to be a 1, and bit 0 of the polynomial register
corresponds to the 0th order of the polynomial, as
shown in Figure 14. The desired size of the CRC, in
bits, is written into the ECRCSize register.
Table 1 gives a suggested list of polynomials for
various length CRCs. The POLY column of table 1
gives the value to program into the ECRCPoly
register. The detection capability column gives the
probability that an incorrect block will be detected
and flagged as incorrect by the CRC decoder.
Figure 14: CRC Encoder
ECRCPoly[0:ECRCSize-1]
Shift Direction
Page 14 of 58
User Data
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CRC Output
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Table 1:
Recommended CRC Polynomials
CRC
SIZE
4
8
12
ANSI
CCITT
SDLC
24
32A
32B
4
8
12
16
16
16
24
32
32
Notes:
*
POLY
Program Value
(hex)*
(bits)
1f
1d5
180f
18005
11021
1a097
1805101
1404098e2
104c11db7
Figure 15: 2D TPC Encoded Block with CRC
DETECTION
CAPABILITY**
0.9375
0.99609
0.999756
0.999985
0.999985
0.999985
0.9999999404
0.99999999953
0.99999999977
D
D
E
E
D
D
D
E
E
D
D
E
E
CRC
E
E
3.2
The leading ‘1’ in these values is assumed
by the device, and should not be written to
the register.
This detection capability is the probability
that an incorrect block is marked in error.
The probability of an undetected block is
computed by multiplying the block error
rate by (1 - Detection Capability).
**
D
SCRAMBLER
The scrambler is built with a 16 bit pseudo-random
binary sequence generator with programmable
polynomial, length, and initialization seed. Figure 16
shows the configuration of the scrambler. The shift
register is clocked once for each bit. As shown in
Figure 16, the output of the shift register is exclusiveORed with the data to be scrambled.
Figure 16 shows an example configuration for
the generator polynomial sequence:
The shift register is reset to all 0s at the
beginning of each TPC block. Data from the block
is shifted into the circuit, until the number of bits
programmed into EBlkSize is reached. Note that the
value written into EBlkSize does not include the
CRC bits. After the entire TPC block is shifted into
the CRC encoder, the data input and feedback of the
CRC shifter are disabled, and the contents of the
CRC registers are shifted out and inserted into the
data stream.
Figure 15 shows the location of the CRC word
inserted in a 2D TPC encoded block. D denotes data
bits and E denotes computed error correction bits.
1+X
14
+X
15
This sequence is programmed into the
EScramPoly register as 0b0110000000000000. The
seed for the shift register that is shown in the
diagram is programmed into EScramSeed as
0b0000000010101001. Every time the scrambler is
reset, it is initialized with this seed value.
Figure 16: Scrambler
EScramPoly[0:15]
1
2
3
4
5
6
7
8
9
1
0
0
1
0
1
0
1
0
10 11 12 13 14 15 16
0
0
0
0
0
0
0
EScramSeed[0:15]
Shift Direction
Data Output
Data Input
PS4524_0204
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Note that the length of the generator is directly
determined by the polynomial configuration. The
sequence shown here is generated by a 15 stage shift
register. Since the highest order of the polynomial is
15, the 16th bit XOR feedback will be disabled, and
only 15 bits of the shift register are used. Also note
that the 0th order of the polynomial is assumed to be 1.
The scrambler is reset at the beginning of every
TPC block.
3.3
ENCODER CODE SHORTENING
There are two methods of shortening product
codes. The first method is to remove an entire row
or column from a 2D code, or an entire X, Y, or Z
plane from a 3D code. This is equivalent to
shortening the constituent codes that make up the
product code, and is accomplished by writing the
amount to shorten into the xShortX, xShortY, and
xShortZ registers (see Section 7.4.4 Shortening
Configuration). This method enables a coarse
granularity on shortening, and at the same time
maintaining the highest code rate possible by
removing both data and parity symbols. Further
shortening is obtained by removing individual bits
from the first row of a 2D code (using xShortB), or
from the top plane of a 3D code (using xShortR).
The following examples discuss shortening in a
2D code and a 3D code. Assume a 456 bit block size
is required, with code rate of approximately 0.6. The
base code chosen before shortening is the
(32,26)x(32,26) code which has a data size of 676
bits. Shortening all rows by 5 and all columns by 4
results in a (27,21)x(28,22) code, with a data size of
462 bits. To get the exact block size, the first row of
the product is shortened by an addition 6 bits. The
final code is a (750,456) code, with a code rate of
0.608. Figure 17 shows the structure of the resultant
block. This shortening is programed into the device
by writing xShortX to 5, xShortY to 4, and xShortB
to 6.
Page 16 of 58
Shorten 6
Additional Bits
26 bits
6 bits
26 bits
Unshortened
Block
TPC ENCODER
The TPC encoder supports 2D or 3D codes,
with constituent code lengths of up to 64 bits, and
overall block size up to 4096 bits. The encoder
supports both extended Hamming and parity only
constituent codes, and supports 2D enhanced TPCs.
See Section 7.4.1 TPC Constituent Code for a
description of supported codes and shortening
configurations.
3.3.1
Figure 17: Structure of Shortened Code
6 bits
Data Bits
28 bits
ECC Bits
27 bits
For the 3D example, suppose a 0.4-0.45 rate
code is required with a data block size of 1100 bits.
Starting with a (32,26)x(32,26)x(4,3) base code, the
optimum shortening for this code is to remove rows
and columns, while leaving the already very short z
axis alone. Therefore, since we desire a 1100 bit 3D
code, we can find the desired vector data size by
taking the square root of 1100/3, and rounding up.
This yields a row/column size of about 20. In fact,
having a row size of 20, a column size of 19, and a
z column size of 3 gives us the closest block size to
1100 bits. This is accomplished by writing xShortX
to 6, xShortY to 7, and xShortZ to 0.
The code size is now a (26,19)x(25,20)x(4,3) =
(2600,1140). To get the exact data size, we further
shorten the first plane of the code by 40 bits. This is
accomplished by shortening 2 full rows from the
first plane (xShortR), with each row removing 19
bits from the data block, and shortening another 2
bits from the next row (xShortB). This results in a
(2546,1100) code, with rate = 0.43. Figure 18 shows
the original code, along with the physical location
of the shortened bits. This is accomplished by
writing xShortB to 2 and xShortR to 2.
There are limitations to code shortening when
helical interleaving or enhanced codes are used.
Refer to Section 7.4.4 Shortening Configuration.
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Figure 18: Structure of Shortened 3D Block
1
Shorten
by 7
3
Original
Unshortened
Block
6
26
Data Bits
25
26
Shorten Front
Plane by 2 Rows
and 2 Bits
6
Shorten
by 6
3.3.2
HELICAL INTERLEAVER
Helical interleaving transmits data in a helical
fashion. When the channel introduces a burst of
errors, the helical deinterleaver in the decoder will
spread these errors across all axes of the code. The
use of helical interleaving increases the burst error
correcting capability of the code, and increases the
block latency. Refer to Section 3.3.5 Encoder
Latency.
The helical interleaver is enabled by setting
EHelical to one (see Section 7.4.1 TPC Constituent
Code). When helical interleaving is enabled, the
EShortX, EShortB, and EShortR values must be
set to 0. For 3D codes, EShortY must also be set to
0 (see Section 7.4.4 Shortening Configuration).
This constrains the shortening resolution to one row
for 2D codes, and one plane for 3D codes. All of the
blocks in the encode datapath must be either
interleaved or not interleaved. A mixture of
interleaving blocks and non-interleaving blocks in
the encoder datapath at the same time is not
allowed.
Helical interleaving is applied along a diagonal
path through the encoded block. Data is output
along diagonal lines from the upper left to lower
right corner (for a 2D code). The first diagonal
output starts with the bit row 1, column 1 followed
by the diagonal starting at row 1, column 2. For 3D
codes, instead of reading diagonally through the 2D
array, interleaving reads diagonally through a cube
of data.
The example below shows how interleaving is
applied for a 2D (64,57)x(64,57) code.
PS4524_0204
Final
Shortened Block
ECC Bits
26
Figure 19: Input Block
Note:
0
1
2
3
...
64
65
66
67
. . . 127
128 129 130 . . .
. . . 191
192 193 . . .
...
...
...
...
...
...
...
...
4032 4033 . . .
...
. . . 4095
...
63
The number reflects the bit order, including
generated ECC bits.
The encoded, interleaved data output is taken
along diagonal lines starting with bit zero as shown
below. The order of the interleaving is noted for
each diagonal line.
Figure 20: 2D Interleaving
1
2
4
127
0
1
2
3
...
64
65
66
67
. . . 127
128 129 130 . . .
. . . 191
192 193 . . .
...
...
...
...
...
...
...
...
4032 4033 . . .
...
. . . 4095
3
...
126
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63
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For the (64,57)x(64,57) block, the data output
is: 0, 65, 130,..., 4095, 1, 66,..., 4031, 4032, 2,
67,...,..., 63, 64,..., 4094 for a total of 4096 bits
output. The AHA4524 operating as a decoder
deinterleaves the block to restore it to its original
order.
Figure 21: Encoded/Interleaved Data Output
0
65
130 . . . 4030 4095
1
66
131 . . . 4031 4032
2
67
132 . . . 3968 4033
3
68
...
...
...
...
...
...
...
...
...
...
63
64
129 . . . 4029 4094
Data bits are output from the encoder in row
order from left to right. 3D interleaving or
deinterleaving is done by reading or writing cells
diagonally through the x, y, and z dimensions.
3.3.3
INTERNAL BUFFERING
An internal encoder buffer is used to allow data
to stream into and out of AHA4524. The encoder
buffer is always enabled because the data flow into
the encoder is not throttled by AHA4524 in either
bus mode or synchronous mode. The logical size of
the encoder input buffer is set via EBufferSize.
Refer to Section 7.4.3 Buffer Configuration
(Encoder Only) for an equation to calculate
EBufferSize.
Page 18 of 58
3.3.4
ENCODER RAPID CODE
RECONFIGURATION
The AHA4524 supports rapid code changing
for up to 4 different block types. This is useful in
systems that require consecutive blocks of different
code types to be encoded. For example, a multichannel system that uses the same encoder to
encode multiple channels, each with a different
code type. In this case, the encoder is rapidly
switching between code types.
The AHA4524 encoder configuration registers
are split into 4 sets of block configuration data to
allow fast configuration changes between blocks.
The 4 sets of configuration data are referred to as
config 0, config 1, config 2, and config 3.
The block configuration set is selected in the
configuration cycle. The control register
ConfigSelect bits (see Section 7.7.1 Control) are
written to select the block configuration of the
immediately following block.
The following registers may be changed for
each block: ECodeX, ECodeY, ECodeZ,
EEnhanced, EHelical, EShortX, EShortY,
EShortZ, EShortB, EShortR, EBufferSize, and
EBlkSize. Each of these registers is mirrored for
each configuration, so that one block can be
processing while another is unloading. A new block
type can be started when U_ACPT is asserted.
U_ACPT deasserts after the block transfer is
started.
The CRC and scrambler configurations do not
change with configuration changes. If CRC and
scrambler changes are necessary for different
blocks, they must be written in the configuration
cycle preceding the block.
Figures 20 and 21 show how data blocks are
processed through the encoder. In Figure 20, helical
interleaving is not enabled so the encoder datapath
processes 1 block at a time. In Figure 21, helical
interleaving is enabled and a data block can be
loaded while another block is unloaded.
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Figure 22: Encoder Rapid Code Reconfiguration with Helical Interleaving Disabled
LOAD
UNLOAD
BLOCK 0
BLOCK 1
BLOCK 0
BLOCK 2
BLOCK 1
BLOCK 2
Figure 23: Encoder Rapid Code Reconfiguration with Helical Interleaving Enabled
LOAD
BLOCK 0
BLOCK 0
UNLOAD
3.3.5
BLOCK 1
BLOCK 2
BLOCK 1
BLOCK 2
ENCODER LATENCY
The encoder latency is defined as the time from when the first un-encoded bit is input, until the E_RDY
signal is asserted to indicate that a block is ready to be output. When helical interleaving is disabled and
E_MODE = 0, the approximate encoder latency in SYSCLKs when PLLBYPASS = 0 is:
( EBufferSize × 16 ) + 31 ⎛
SYSCLK (MHz)
SYSCLK (MHz)
------------------------------------------------------------ + 2 × ------------------------------------------⎞ + ⎛ 2 × ------------------------------------------⎞
⎝
2
U _CLK (MHz) ⎠ ⎝
E_CLK (MHz) ⎠
When helical interleaving is disabled and E_MODE = 1, the approximate encoder latency in SYSCLKs is:
( EBufferSize × 16 ) + 36
-----------------------------------------------------------2
The EBufferSize input buffer is used to guarantee a streaming input and output.
Helical interleaving adds one block of latency. When helical interleaving is enabled, the encoder input
buffer is not used. The worst case encoder latency in SYSCLKs when helical interleaving is enabled and
E_MODE = 0 is:
(MHz)
SYSCLK (MHz)
SYSCLK (MHz)
⎛ 1 encoded block size × SYSCLK
------------------------------------------⎞ + ⎛ 2 × ------------------------------------------⎞ + 24 + ⎛ 2 × ------------------------------------------⎞
⎝
⎝
U_CLK (MHz) ⎠ ⎝
U_CLK (MHz) ⎠
E_CLK (MHz) ⎠
When helical interleaving is enabled and E_MODE = 1, the worst case encoder latency in SYSCLKs is:
(MHz)
⎛ 1 encoded block size × SYSCLK
------------------------------------------⎞ + 26
⎝
U_CLK (MHz) ⎠
If the PLL is bypassed (PLLBYPASS = 1), then the latency result in SYSCLKs must be multiplied by 4.
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4.0
DECODER
4.2.1
The decode path of AHA4524 includes a
counterpart for each encoder module. The encoder
and decoder are isolated paths. This allows full
duplex operation, where the encoder and decoder may
be operating with different code types and data rates.
4.1
CHANNEL INTERFACE
The channel interface formats the channel data
for decoding by the Turbo Product Code decoder.
For best decoder performance, soft metric
information from the channel is necessary.
4.1.1
CHANNEL INPUT FORMATTING
When decoding, data may be input either
serially or one quantization value per handshake on
C_DATA[q-1:0] where q is the number of input
quantization bits. The number of quantization bits is
configurable based on the setting of QBIT[1:0]
within the Quantization register in Section 7.5.1.
The QMODE[1:0] bits within the Quantization
register determine the type of input data. The input
data may be 2’s complement, sign/magnitude, or
unsigned. All unused C_DATA inputs are ignored
except in configuration cycles. Note that all
C_DATA[3:0] inputs are used for configuration
cycles in parallel mode. In parallel configuration
cycles, configuration bits (15:11) are written first
with configuration bit 15 input on C_DATA[3]. In
parallel data cycles, the lsb of the soft metric value
is input on C_DATA[0] and the msb is determined
by QBits[1:0]. Figure 24 shows example
connections when QBits[1:0] = “11” (3 input bits).
Figure 24: C_DATA Interface
AHA4524
C_DATA[2]
C_DATA[1]
C_DATA[0]
C_DATA[3]
C_DATA[2] - msb
C_DATA[1]
C_DATA[0] - lsb
For QBits = “11” connect C_DATA as shown
4.2
TPC DECODER
The Turbo Product Code decoder supports
block sizes up to 4096 encoded bits. The decoder
supports iterative decoding of 2D or 3D codes built
from extended Hamming or parity only constituent
codes of length up to 64 bits. The decoder supports
decoding of 2D enhanced TPCs to improve low bit
error rate (BER) performance.
Page 20 of 58
HELICAL DEINTERLEAVER
The helical deinterleaver is enabled by setting
DHelical to 1 in the configuration register shown in
Section 7.4.1 TPC Constituent Code. See Section
3.3.2 for a description of helical interleaving.
4.2.2
CODE CONFIGURATION
Turbo Product Codes are specified by the
constituent codes of each axis in the code. The code
configuration registers in Section 7.4.1 TPC
Constituent Code specify the code type (extended
Hamming or Parity) and length of each axis, as well
as enabling the 2D enhanced TPC axis.
To generate a specific block size, the product
code is shortened. Shortening is discussed in detail
in Section 4.2.3.
The decoder can be configured to run specific
number of iterations by programming the number of
Iterations in the configuration register shown in
Section 7.4.6 Iterations (Decoder Only). The
decoder can be set to detect when a block converges
and stop iterating. This allows the decoder to spend
more time, up to the number of iterations specified
in Iterations, on difficult blocks and less time on
less difficult blocks. This feature is enabled by
setting StopIter in the configuration register shown in
Section 7.4.5 Feedback (Decoder Only).
4.2.3
DECODER CODE SHORTENING
Refer to Section 3.3.1 Encoder Code
Shortening.
4.2.4
CORRECTIONS COUNT
In order to assist the system with estimation of
channel bit error rates, the AHA4524 device reports
the number of bits corrected in each block decoded.
The Corrections register, see Section 7.7.2
Status and Correction Count (Decoder Only),
contains the number of corrections between
incoming (channel) data and outgoing (decoded)
data. This corrections value is the corrections done
on all bits in the TPC block, including user data,
CRC, and TPC ECC bits. The correction count is
updated in the Corrections register after each block
is decoded and is also optionally output at the end of
every block as a status footer (see Section 2.5
Decoder Status Output Format). Note that any reads
from the Corrections register can only occur when
the decoder datapath is empty. The Corrections
value will apply to the last decoded block.
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4.2.5
DESCRAMBLER
4.2.7
The descrambler is built with a 16 bit pseudorandom binary sequence generator with
programmable polynomial, length, and
initialization seed. The descrambler logic matches
that of the scrambler, shown in Figure 16, refer to
Section 3.2.
The generator polynomial sequence is
programmed into the DScramPoly register. The
seed for the shift register shown in Figure 16 is
programmed into DScramSeed. Every time the
descrambler is reset, it initializes to the
DScramSeed value. The descrambler is reset at the
start of every block.
4.2.6
CRC CHECKING
The CRC parity bits are checked after decoding.
Each packet has a separate CRC, with variable
length up to 32 bits. The CRC comparator circuit
matches that of the encoder, shown in Figure 14.
The shift register is reset at the beginning of
each TPC block. Data from the TPC block is shifted
into the circuit, until the number of bits
programmed into DBlkSize is reached. At this point,
the contents of the CRC shift register are examined.
If all bits are 0, then the CRC is correct. Otherwise,
a CRC error is detected, and the CRCErr status flag
is set in the decoder status footer (see Section 2.5
Decoder Status Output Format). The CRCErr flag
can also be read from the status register shown in
Section 7.7.2 Status and Correction Count
(Decoder Only).
DECODER RAPID CODE
RECONFIGURATION
Similar to the encoder (see Section 3.3.4
Encoder Rapid Code Reconfiguration), the
AHA4524 decoder supports rapid code changing.
This is useful in systems that require consecutive
blocks of different code types to be decoded.
The AHA4524 decoder configuration registers
are split into 4 sets of block configuration data to
allow fast configuration changes between blocks. The
4 sets of configuration data are referred to as config 0,
config 1, config 2, and config 3.
The block configuration set is selected in the
input configuration cycle. The control register
ConfigSelect bits (see Section 7.7.1 Control) are
written to select the configuration for the following
block. The CRC and scrambler configuration do not
change with configuration changes. If CRC and
scrambler changes are necessary for different
blocks, they must be written in the configuration
cycle preceding the block.
The following registers may be changed for
each block configuration: DCodeX, DCodeY,
DCodeZ, DEnhanced, DHelical, DShortX,
DShortY, DShortZ, DShortB, DShortR, DBlkSize,
FeedbackX, FeedbackY, FeedbackZ, FeedbackH,
FeedbackHP, StopIter, and Iterations. Each of
these registers is mirrored for each configuration, so
that one block type can be loading while another
block type is processing while another block type is
unloading. A new block type may be started when
C_ACPT is asserted. C_ACPT deasserts after the
block transfer is started.
Figure 25 shows the block timing when using
decoder rapid code reconfiguration. The figure
shows a code type for block 1 that is larger than for
blocks 0 and 2.
Figure 25: Decoder Rapid Code Reconfiguration
LOAD
DECODE
UNLOAD
PS4524_0204
BLOCK 0
BLOCK 1
BLOCK 0
BLOCK 2
BLOCK 1
BLOCK 0
BLOCK 2
BLOCK 1
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BLOCK 2
Page 21 of 58
comtech aha corporation
4.2.8
DECODER LATENCY
The decoder latency is defined as the time from when the last channel bit is input, until the D_RDY
signal is asserted to indicate that a block is ready to be output. In the following equations, DCodeX is
DCodeX[2:0], DCodeY is DCodeY[2:0], and DCodeZ is DCodeZ[2:0]. The approximate decoder latency in
SYSCLKs when PLLBYPASS = 0 is:
If DCodeX is not 0,
DCodeX
DCodeY
DCodeZ
DCodeX
DCodeZ
DCodeX
DCodeY
2
× (2
– DShortY ) × ( 2
– DShortZ )
DCodeX
x_latency = ----------------------------------------------------------------------------------------------------------------------------------------- + 2
+ 16
4
If DCodeX = 0, x_latency = 0.
If DCodeY is not 0,
DCodeY
2
× (2
– DShortX ) × ( 2
– DShortZ )
DCodeY
y_latency = ----------------------------------------------------------------------------------------------------------------------------------------- + 2
+ 16
4
If DCodeY = 0, y_latency = 0.
If DCodeZ is not 0,
DCodeZ
2
× (2
– DShortX ) × ( 2
– DShortY )
DCodeZ
z_latency = ----------------------------------------------------------------------------------------------------------------------------------------- + 2
+ 16
4
If DCodeZ = 0, z_latency = 0.
If enhanced = 1,
DCodeY
DCodeX
2
×2
DCodeY
e_latency = -------------------------------------------- + 2
+ 16
4
If enhanced = 0, e_latency = 0.
iter_clocks = ( x_latency + y_latency + z_latency + e_latency ) × Iterations
When D_MODE = 1,
DCodeX
) + DShortB
iter_clocks ( DShortR × 2
latency = 29 + -------------------------- + ---------------------------------------------------------------------------------4
2
When D_MODE = 0,
DCodeX
) + DShortB
2 × SYSCLK (MHz)
2 × SYSCLK (MHz) iter_clocks ( DShortR × 2
latency = --------------------------------------------------- + 27 + --------------------------------------------------- + -------------------------- + -----------------------------------------------------------------------------------C_CLK (MHz)
D_CLK (MHz)
2
4
If the PLL is bypassed (PLLBYPASS = 1), then the latency result in SYSCLKs must be multiplied by 4.
Table 2 gives an abridged list of possible codes supported by AHA4524, along with the latency in
SYSCLKs for 4, 6, and 12 iterations with the CRC disabled. This table applies to a synchronous (D_MODE
= 0) port configuration with the internal PLL enabled (PLLBYPASS = 0) and assumes that the frequency of
C_CLK = SYSCLK. This is a very small subset of supported codes. AHA can provide software to assist the
code selection process.
Page 22 of 58
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Table 2:
Partial Code List and Decoder Datapath Latency
CODE
(X)x(Y)x(Z)
BLOCK
SIZE
DATA
SIZE
(bits)
(bits)
(64,63)x(64,62)+
(64,57)x(64,57)
(32,26)x(32,26)x(4,3)
(16,11)x(16,11)x(16,11)
(64,63)x(32,30)+
(64,57)x(32,26)
(16,11)x(16,11)x(8,4)
(32,26)x(32,30)+
(32,26)x(32,26)
(16,11)x(16,11)x(4,3)
*
4096
4096
4096
4096
2048
2048
2048
1024
1024
1024
4 ITERATIONS 6 ITERATIONS 12 ITERATIONS
(SYSCLKs)*
3906
3249
2028
1331
1890
1482
484
780
676
363
6621
4445
6405
6365
3421
2333
3277
1837
1245
1733
(SYSCLKs)*
9917
6653
9593
9533
5117
3485
4901
2741
1853
2585
(SYSCLKs)*
19805
13277
19157
19037
10205
6941
9773
5453
3677
5141
The number of SYSCLKs is assuming the PLL is enabled (PLLBYPASS=0) and is accurate to within 2%. If the PLL
is not enabled (PLLBYPASS=1), then the latency in SYSCLKs must be multiplied by 4.
Table 3:
Partial Code List and Performance - Synchronous Interface
CODE
(X)x(Y)x(Z)
(64,63)x(64,62)+
(64,57)x(64,57)
(32,26)x(32,26)x(4,3)
(16,11)x(16,11)x(16,11)
(64,63)x(32,30)+
(64,57)x(32,26)
(16,11)x(16,11)x(8,4)
(32,26)x(32,30)+
(32,26)x(32,26)
(16,11)x(16,11)x(4,3)
*
+
BLOCK
SIZE
DATA
SIZE
(bits)
(bits)
4096
4096
4096
4096
2048
2048
2048
1024
1024
1024
3906
3249
2028
1331
1890
1482
484
780
676
363
CODE
RATE
6 ITER
CODING
GAIN
(dB)
0.954
0.793
0.495
0.325
0.923
0.724
0.236
0.762
0.660
0.354
4.5
7.3
8.1
8.5
4.9
7.2
8.2
5.3
7.2
7.4
4 ITER
Channel/
Data*
6 ITER
Channel/
Data*
12 ITER
Channel/
Data*
(Avg Mbit/sec) (Avg Mbit/sec) (Avg Mbit/sec)
32.7/31.1
48.1/38.5
34.0/17.3
33.9/11.3
31.6/27.6
46.0/33.9
33.2/8.1
29.7/22.9
43.9/29.4
31.8/11.8
22.1/20.8
32.7/26.1
22.9/11.5
23.1/7.6
21.3/19.8
31.3/22.9
22.6/5.3
20.0/15.5
29.7/19.8
21.5/7.7
11.1/10.6
16.6/13.2
11.6/5.6
11.6/3.7
10.8/10.0
16.0/11.6
11.3/2.6
10.0/7.7
16.0/10.0
10.8/3.9
The input and output rates assume a 50 MHz SYSCLK frequency when the PLL is enabled, or a 200 MHz SYSCLK
frequency when the PLL is bypassed. The port clocks C_CLK and D_CLK are assumed to be running at 95 MHz.
Enhanced TPC. In enhanced codes, the Y axis is shortened by 1. The shortening and addition of enhanced axis is
included in the code description.
PS4524_0204
A subsidiary of Comtech Telecommunications Corporation
Page 23 of 58
comtech aha corporation
Table 4:
Partial Code List and Performance - Bus Interface
CODE
(X)x(Y)x(Z)
(64,63)x(64,62)+
(64,57)x(64,57)
(32,26)x(32,26)x(4,3)
(16,11)x(16,11)x(16,11)
(64,63)x(32,30)+
(64,57)x(32,26)
(16,11)x(16,11)x(8,4)
(32,26)x(32,30)+
(32,26)x(32,26)
(16,11)x(16,11)x(4,3)
*
+
BLOCK
SIZE
DATA
SIZE
(bits)
(bits)
4096
4096
4096
4096
2048
2048
2048
1024
1024
1024
3906
3249
2028
1331
1890
1482
484
780
676
363
CODE
RATE
6 ITER
CODING
GAIN
(dB)
0.954
0.793
0.495
0.325
0.923
0.724
0.236
0.762
0.660
0.354
4 ITER
Channel/
Data*
6 ITER
Channel/
Data*
12 ITER
Channel/
Data*
(Avg Mbit/sec) (Avg Mbit/sec) (Avg Mbit/sec)
4.5
7.3
8.1
8.5
4.9
7.2
8.2
5.3
7.2
7.4
31.3/30.0
36.0/30.2
32.4/16.6
32.7/11.1
30.3/28.2
37.1/27.6
31.8/7.9
28.5/22.1
37.1/25.2
31.0/11.5
21.5/20.5
31.3/25.3
22.1/11.3
22.4/7.4
20.8/19.2
30.0/22.1
21.8/5.3
19.5/15.0
12.4/19.4
20.8/7.6
11.0/10.5
16.3/13.1
11.5/5.5
8.9/3.7
10.6/9.8
15.6/11.5
11.1/2.6
10.0/7.6
14.8/10.0
10.6/3.9
The input and output rates assume a 50 MHz SYSCLK frequency when the PLL is enabled, or a 200 MHz SYSCLK
frequency when the PLL is bypassed. The read and write strobes C_WR_N and D_RD_N are assumed to be
running at 50 MHz.
Enhanced TPC. In enhanced codes, the Y axis is shortened by 1. The shortening and addition of enhanced axis is
included in the code description.
4.2.9
CODE PERFORMANCE
Table 3 and Table 4 give code rate, coding gain,
and maximum channel and user (decoded) data
rates for the same abridged list of possible codes
that was shown in Table 2. The data rate calculations
assume that the frequency of SYSCLK is 50 MHz.
The coding gain is measured on a Binary Input
Additive White Gaussian Noise (AWGN) channel
at 10-6 Bit Error Rate (BER) and 6 iterations. AHA
can provide software to assist in code BER
performance analysis.
5.0
PHASE LOCK LOOP
The AHA4524 contains an internal PLL which
is used to multiply the input SYSCLK frequency by
4 for internal clocking. The internal PLL has a
minimum input SYSCLK frequency of 20 MHz
and a maximum input SYSCLK frequency of 50
MHz, see Section 11.1 SYSCLK Clock Timing. The
PLL can not lock to frequencies below 20 MHz.
The internal PLL is enabled when pin
PLLBYPASS = 0. If PLLBYPASS = 1, the internal
PLL is bypassed, and the input SYSCLK directly
drives the internal logic.
Page 24 of 58
When the PLL is bypassed, the latency and
throughput are reduced by a factor of 4 given the
same input SYSCLK frequency. The throughput and
latency are identical when the PLL is bypassed and
a 4x SYSCLK frequency is used when compared to
the throughput and latency when the PLL is enabled
and a 1x SYSCLK frequency is used.
Refer to Section 3.3.5 Encoder Latency and
Section 4.2.8 Decoder Latency.
6.0
GENERAL OUTPUT SIGNALS
The AHA4524 contains a general output signal
for the encoder and a general output signal for the
decoder that can be used to control external logic, or
for system debugging. The signals can be driven to
a 1 or 0, or can be driven according to events within
the device, including load complete, decode
complete, empty, etc. See Section 7.7.1 for a
complete list of available status outputs.
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7.0
REGISTER DESCRIPTIONS
7.1
CONFIGURATION SEQUENCE
7.2
The following sequence should be followed
when configuring the device. The encoder and
decoder configuration sequences are identical. The
following configuration sequence is described in
terms of the decoder, but all descriptions, except
where explicitly stated, apply to the encoder.
The decoder is reset when RESET_N = 0. After
the rising edge of RESET_N, the decoder is idle.
The first write to the decoder is expected to start a
configuration cycle. The order of configuration is
not important. The last configuration cycle is
specified by either the “rwb” bit = 1 or “last” bit = 1
(see Section 2.3 Configuration Cycle Format). Data
is not expected to follow the configuration cycles if
the last configuration cycle is a read, or if the
DNoBlock bit was set (see Section 7.7.1 Control).
Table 5:
There are 2 complete register sets in the
AHA4524 device, one for the encoder and one for
the decoder. Registers used in both the encoder and
decoder have the same address but are accessed
through either the encoder or decoder data interface.
In Table 5, the register bit name does not include the
E for encoder register or D for decoder register
when the register is common to both the encoder
and decoder. Registers that are specific to the
encoder or decoder are labelled with the E for
encoder or D for decoder. All register bits labelled
as “res” are reserved and must be written to 0. Reads
from reserved registers return unpredictable values.
Register Bits - Alphabetical
REGISTER BIT NAME
ActualIterations[7:0]
ConfigSelect[1:0]
Corrections[11:8]
Corrections[7:0]
CRCEnable
CONFIG ADDRESS
read only
0x3d
0
0x11
1
0x11
2
0x12
3
0x12
0
0x13
1
0x14
2
0x15
3
0x16
0
0x09
1
0x0b
2
0x0d
3
0x0f
0
0x09
1
0x0b
2
0x0d
3
0x0f
0
0x0a
1
0x0c
2
0x0e
3
0x10
all
0x26
read only
0x3b
read only
0x3c
all
0x00
CRCErr
read only
BlkSize[11:8]
BlkSize[7:0]
CodeX[3:0]
CodeY[3:0]
CodeZ[3:0]
PS4524_0204
REGISTER LIST
0x3b
BIT
REGISTER SECTION
7:0 Section 7.7.3 Actual Iterations (Decoder Only)
3:0
7:4
3:0
7:4
Section 7.4.2 Block Size
7:0
7:4
3:0 Section 7.4.1 TPC Constituent Code
3:0
1:0
3:0
7:0
5
Section 7.7.1 Control
Section 7.7.2 Status and Correction Count
(Decoder Only)
Section 7.3.1 CRC and Scrambler Configuration
Section 7.7.2 Status and Correction Count
4
(Decoder Only)
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Page 25 of 58
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REGISTER BIT NAME
CRCPoly[31:24]
CRCPoly[23:16]
CRCPoly[15:8]
CRCPoly[7:0]
CRCSize[4:0]
DOutputECC
DStatus
EBufferSize[8]
Enhanced
EPassThrough
FeedbackH[4:0]
FeedbackHP[4:2]
FeedbackHP[1:0]
FeedbackX[4:0]
FeedbackY[4:2]
FeedbackY[1:0]
FeedbackZ[4:0]
GOutConfig[2:0]
Helical
Page 26 of 58
CONFIG
all
all
all
all
0
1
2
3
0
1
2
3
all
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
all
0
1
2
3
ADDRESS
0x01
0x02
0x03
0x04
0x00
0x0a
0x26
0x28
0x29
0x2a
0x2b
0x0a
0x0c
0x0e
0x10
0x0a
0x30
0x31
0x32
0x34
0x30
0x33
0x33
0x34
0x31
0x33
0x33
0x35
0x28
0x2a
0x2c
0x2e
0x28
0x2a
0x2c
0x2e
0x29
0x2b
0x2d
0x2f
0x29
0x2b
0x2d
0x2f
0x26
0x0a
0x0c
0x0e
0x10
BIT
7:0
REGISTER SECTION
Section 7.3.1 CRC and Scrambler Configuration
4:0
5 Section 7.4.1 TPC Constituent Code
6 Section 7.7.1 Control
7:0
4
Section 7.4.3 Buffer Configuration (Encoder
Only)
Section 7.4.1 TPC Constituent Code
6
4:0
6:2
4:0
7:5
6:4
7:5
1:0
3:2
1:0
4:0 Section 7.4.5 Feedback (Decoder Only)
7:5
1:0
6:2
5:3 Section 7.7.1 Control
7 Section 7.4.1 TPC Constituent Code
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comtech aha corporation
REGISTER BIT NAME
Iterations[7:0]
NoBlock
NoConfig
QBits[1:0]
QMode[1:0]
ScramEnable
ScramPoly[15:8]
ScramPoly[7:0]
ScramSeed[15:8]
ScramSeed[7:0]
ShortB[5:2]
ShortB[1:0]
ShortR[5:0]
ShortX[5:0]
ShortY[5:4]
ShortY[3:0]
ShortZ[3:0]
StopIter
Version[7:0]
WordEqBlk
WordSize[4:0]
PS4524_0204
CONFIG ADDRESS
0
0x36
1
0x37
2
0x38
3
0x39
all
0x26
all
all
0x3a
all
all
0x00
all
0x05
all
0x06
all
0x07
all
0x08
0
0x18
1
0x1b
2
0x1e
3
0x21
0
0x19
1
0x1c
2
0x1f
3
0x22
0
0x19
1
0x1c
2
0x1f
3
0x22
0
0x17
1
0x1a
2
0x1d
3
0x20
0
0x17
1
0x1a
2
0x1d
3
0x20
0
0x18
1
0x1b
2
0x1e
3
0x21
0
0x23
1
0x23
2
0x24
3
0x24
0
0x29
1
0x2b
2
0x2d
3
0x2f
read only
0x3f
all
0x27
all
0x27
BIT
REGISTER SECTION
7:0 Section 7.4.6 Iterations (Decoder Only)
2
Section 7.7.1 Control
7
3:2
Section 7.5.1 Quantization (Decoder Only)
1:0
6
7:0
Section 7.3.1 CRC and Scrambler Configuration
7:4
1:0
7:2
5:0 Section 7.4.4 Shortening Configuration
7:6
3:0
3:0
7:4
3:0
7:4
7 Section 7.4.5 Feedback (Decoder Only)
7:0 Section 7.8.1 Version
5 Section 7.6.1 Transfer Word Size
4:0 Section 7.6.1 Transfer Word Size
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7.3
USER DATA FORMATTING REGISTERS
7.3.1
CRC AND SCRAMBLER CONFIGURATION
Read/Write
Reset Value (hex) = 00 00 00 00 00 00 00 00 00
address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
bit7
res
bit6
bit5
bit4
bit3
bit2
bit1
xScramEnable xCRCEnable
xCRCSize[4:0]
xCRCPoly[31:24]
xCRCPoly[23:16]
xCRCPoly[15:8]
xCRCPoly[7:0]
xScramPoly[15:8]
xScramPoly[7:0]
xScramSeed[15:8]
xScramSeed[7:0]
bit0
xCRCEnable - CRC Enable. When set, the encoder will compute and insert CRC bits, and the decoder will
compute, check and remove CRC.
xCRCSize[4:0] - CRC Size. A value of 0 represents 32 bits. This value must always be less than or equal to
xBlockSize[11:0].
xCRCPoly[31:0] - CRC Polynomial. Refer to Table 1 on page 15 for configuration of the polynomial.
xScramEnable - Scrambler/Descrambler Enable. When set, the scrambler or descrambler will scramble the
data according to the polynomial. When cleared, the scrambler or descrambler is disabled.
xScramPoly[15:0] - Scrambler/Descrambler polynomial. For each exponential term in the polynomial, XN,
a binary one should be loaded at bit location N-1. X0 is assumed to be a term in the polynomial.
For example, the polynomial 1+X3+X5+X8 is programmed as 0b0000000010010100. Note that
the length of the PRBS is determined by the most significant bit location containing a one in
xScramPoly[15:0]. Refer to Figure 16 on Page 15 for configuration of the polynomial.
xScramSeed[15:0] - Seed for scrambler and descrambler. The PRBS is reset to this seed at the beginning of
every TPC block. Refer to Figure 16 on Page 15 for configuration of the seed.
Page 28 of 58
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7.4
CODE CONFIGURATION REGISTERS
7.4.1
TPC CONSTITUENT CODE
Read/Write
Reset Value (hex) = 00 00 00 00 00 00 00 00
address
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
0x10
bit7
xHelical - config 0
xHelical - config 1
xHelical - config 2
xHelical - config 3
bit6
bit5
bit4
xCodeX[3:0] - config 0
EPass DOutput
xEnhanced - config 0
Thru
ECC
xCodeX[3:0] - config 1
res
xEnhanced - config 1
xCodeX[3:0] - config 2
res
xEnhanced - config 2
xCodeX[3:0] - config 3
res
xEnhanced - config 3
bit3
bit2
bit1
bit0
xCodeY[3:0] - config 0
xCodeZ[3:0] - config 0
xCodeY[3:0] - config 1
xCodeZ[3:0] - config 1
xCodeY[3:0] - config 2
xCodeZ[3:0] - config 2
xCodeY[3:0] - config 3
xCodeZ[3:0] - config 3
xCodeX[3:0] - X axis code. xCodeX[3] determines whether the code is an extended Hamming or parity only
code. When set, the code is a parity only code, when cleared, it is an extended Hamming code.
xCodeX[2:0] determines the size of the code, as follows:
Code[2:0]
EXTENDED HAMMING
PARITY ONLY
0x2
0x3
0x4
0x5
0x6
N/A
(8,4)
(16,11)
(32,26)
(64,57)
(4,3)
(8,7)
(16,15)
(32,31)
(64,63)
xCodeY[3:0] - Y axis code. Defined the same as xCodeX[3:0]. The maximum length for y-code is 64 bits.
xEnhanced - Enhanced TPC Enable. When set, a diagonal axis is added to the code. This adds 1 additional
row of parity bits to 2D codes. This bit is not valid for 3D codes. When xEnhanced is set with
a 2D code, xShortY must be greater than or equal to 1.
xCodeZ[3:0] - Z axis code. Defined the same as xCodeX[3:0]. Set xCodeZ[3:0] to 0 for 2D codes. The
maximum length for code Z is 16 bits.
EPassThru - Encoder Pass Through. When set, the encoder does not add ECC bits. The block size is still
configured by the code configuration, but the encoder simply passes bits through from the input
to the output. This is a reserved bit in the decoder configuration register stack.
DOutputECC - Decoder Output ECC. When set, the decoder will output both the user data and the TPC
ECC bits. Descrambling and CRC checking must be disabled when this bit is set. This is a
reserved bit in the encoder configuration register stack.
xHelical - Helical Interleaver/Deinterleaver Enable. See Section 3.3.2 for a description of helical
interleaving. The following rules must be followed when helical interleaving.
If a 2D code is used, the length of the x dimension vector (xCodeX - xShortX) must be a
multiple of 2.
If a 3D code is used, the length of the x dimension and the length of the y dimension (xCodeY
- xShortY) must be a multiple of 2.
xShortR and xShortB must be 0.
When fast code changing is used, all of the blocks in the encode path must be either interleaved
or not interleaved. A mixture of interleaving blocks and non-interleaving blocks in the encoder
datapath at the same time is not allowed.
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7.4.2
BLOCK SIZE
Read/Write
Reset Value (hex) = 00 00 00 00 00 00
address
0x11
0x12
0x13
0x14
0x15
0x16
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
xBlockSize[11:8] - config 1
xBlockSize[11:8] - config 0
xBlockSize[11:8] - config 3
xBlockSize[11:8] - config 2
xBlockSize[7:0] - config 0
xBlockSize[7:0] - config 1
xBlockSize[7:0] - config 2
xBlockSize[7:0] - config 3
xBlockSize - Block Size. This is the number of input bits per block when encoding or decoding.
When decoding, DBlockSize includes the CRC bits if they were inserted by the encoder. When
encoding, EBlockSize does not include CRC bits. EBlockSize + ECRCSize must always be less
than 4096 bits. When set to 0, xBlockSize is 4096 bits. The minimum number of data bits in a
block is 16, and the number of data bits must be greater than or equal to xCRCSize[4:0].
An example of (16,11) × (16,11) with 16 bit CRC gives
D BlockSize = 16 × 16 = 256 = 0 × 100
E BlockSize = (11 × 11) - 16 = 105 = 0 × 069
When decoding, DBlockSize is equal to the channel block for a maximum of 4096 bits.When
encoding EBlockSize is equal to the data block size minus CRC bits.
7.4.3
BUFFER CONFIGURATION (ENCODER ONLY)
Read/Write
Reset Value (hex) = 00 00 00 00
address
0x28
0x29
0x2a
0x2b
bit7
bit6
bit5
bit4
bit3
EBufferSize[7:0] - config 0
EBufferSize[7:0] - config 1
EBufferSize[7:0] - config 2
EBufferSize[7:0] - config 3
bit2
bit1
bit0
EBufferSize[7:0] - Encoder Logical Buffer Size * 16. The encoder input buffer is used to allow data blocks
to stream into and out of the TPC encoder. When set to 0, EBufferSize[7:0] is 256.
EBufferSize[7:0] should be set according to the following equations:
If the frequency of U_CLK is greater than or equal to the frequency of E_CLK, or if EHelical
= 1, then
EBufferSize = 1.
If the frequency of E_CLK is greater than the frequency of U_CLK, and EHelical = 0, then in
order to stream out a block continuously,
EBufferSize =
cr
[ n x × n y × ( n z – k z ) + n x × ( n y – k y ) + n x – k x ] ------ × ( ( eclk ) ⁄ ( uclk ) )
16
Where the codes (nx,kx), (ny,ky) and (nz,kz) refer to the shortened constituent codes and cr is the
code rate of the input block. The code rate is the number of input bits divided by the number of
output bits including bits inserted by the CRC encoder. For 2D and enhanced 2D codes, nz and
kz are zero. ky includes the enhanced axis parity bits.
If EBufferSize*16 is calculated to be greater than EBlockSize, then
EBufferSize = EBlockSize/16
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7.4.4
SHORTENING CONFIGURATION
Read/Write
Reset Value (hex) = 00 00 00 00 00 00 00 00 00 00 00 00 00 00
address
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20
0x21
0x22
0x23
0x24
bit7
bit6
bit5
bit4
xShortY[5:4] - config 0
xShortB[5:2] - config 0
xShortR[5:0] -config 0
xShortY[5:4] - config 1
xShortB[5:2] - config 1
xShortR[5:0] -config 1
xShortY[5:4] - config 2
xShortB[5:2] - config 2
xShortR[5:0] -config 2
xShortY[5:4] - config 3
xShortB[5:2] - config 3
xShortR[5:0] -config 3
xShortZ[3:0] - config 1
xShortZ[3:0] - config 3
bit3
bit2
bit1
bit0
xShortX[5:0] - config 0
xShortY[3:0] - config 0
xShortB[1:0] - config 0
xShortX[5:0] - config 1
xShortY[3:0] - config 1
xShortB[1:0] - config 1
xShortX[5:0] - config 2
xShortY[3:0] - config 2
xShortB[1:0] - config 2
xShortX[5:0] - config 3
xShortY[3:0] - config 3
xShortB[1:0] - config 3
xShortZ[3:0] - config 0
xShortZ[3:0] - config 2
xShortX[5:0] - Number of bits to shorten from the X axis code. This value must be set to an even value when
helical interleaving or enhanced TPC is enabled. The X axis must always contain at least 2 data
bits.
xShortY[5:0] - Number of bits to shorten from the Y axis code. For 2D codes, this value must be greater than
or equal to 1 if enhanced TPC is enabled. For 3D codes, this value must be set to an even value
when helical interleaving is enabled.
xShortZ[3:0] - Number of bits to shorten from the Z axis code. For 2D codes, this value must be set to 0.
xShortB[5:0] - Number of bits to shorten from the first row of a 2D code, or from the xShortR+1 row of the
top plane of a 3D code. This value must be set to 0 when helical interleaving is enabled.
xShortR[5:0] - Number of full rows to shorten from the top plane of a 3D code. For 2D codes, this value must
be set to 0. This value must be set to 0 when helical interleaving is enabled.
Table 6:
Summary of Code Shortening Rules
Code Type
2D
2D Enhanced
2D Helical
2D Enhanced and
Helical
3D
3D Helical
PS4524_0204
ShortX
ShortY
ShortZ
even
even
>= 1
even
even
even
ShortB
ShortR
not allowed
not allowed
not allowed
not allowed
not allowed
not allowed
not allowed
not allowed
not allowed
not allowed
not allowed
not allowed
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7.4.5
FEEDBACK (DECODER ONLY)
Read/Write
Reset Value (hex) = 00 00 00 00 00 00 00 00 00 00 00 00 00 00
address
0x28
0x29
0x2a
0x2b
0x2c
0x2d
0x2e
0x2f
0x30
0x31
0x32
0x33
0x34
0x35
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
FeedbackY[4:2] - config 0
FeedbackX[4:0] - config 0
StopIter - config 0
FeedbackZ[4:0] - config 0
FeedbackY[1:0] - config 0
FeedbackY[4:2] - config 1
FeedbackX[4:0] - config 1
StopIter - config 1
FeedbackZ[4:0] - config 1
FeedbackY[1:0] - config 1
FeedbackY[4:2] - config 2
FeedbackX[4:0] - config 2
StopIter - config 2
FeedbackZ[4:0] - config 2
FeedbackY[1:0] - config 2
FeedbackY[4:2] - config 3
FeedbackX[4:0] - config 3
StopIter - config 3
FeedbackZ[4:0] - config 3
FeedbackY[1:0] - config 3
FeedbackHP[4:2] - config 0
FeedbackH[4:0] - config 0
res
FeedbackH[4:0] - config 1
FeedbackHP[1:0] - config 0
FeedbackHP[4:2] - config 2
FeedbackH[4:0] - config 2
res
FeedbackHP[4:0] - config 1
FeedbackHP[1:0] - config 2
FeedbackHP[4:2] - config 3
FeedbackH[4:0] - config 3
res
FeedbackHP[1:0] - config 3
FeedbackX[4:0] - Feedback for the X axis. The output of the SISO is multiplied by FeedbackX[4:0], then
shifted by 5 (divided by 32) before being input to following iterations.
FeedbackY[4:0] - Feedback for the Y axis.
FeedbackZ[4:0] - Feedback for the Z axis.
FeedbackH[4:0] - Feedback for the enhanced axis.
FeedbackHP[4:0] - Feedback for the enhanced parity row.
StopIter - When set, decoder will stop iterating before reaching the maximum number of iterations
specified in the Iterations register if convergence is detected (see Section 7.4.6 Iterations
(Decoder Only)). When clear, the decoder will iterate the full number of Iterations.
7.4.6
ITERATIONS (DECODER ONLY)
Read/Write
Reset Value (hex) = 00 00 00 00
address
0x36
0x37
0x38
0x39
bit7
bit6
bit5
bit4
bit3
Iterations[7:0] - config 0
Iterations[7:0] - config 1
Iterations[7:0] - config 2
Iterations[7:0] - config 3
bit2
bit1
bit0
Iterations[7:0] - Maximum number of iterations to perform. When set to 0, the decoder outputs the hard
decision values for each bit with no corrections.
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7.5
CHANNEL INTERFACE REGISTERS
7.5.1
QUANTIZATION (DECODER ONLY)
Read/Write
Reset Value (hex) = 00
address
0x3a
bit7
bit6
bit5
bit4
bit3
bit2
QBits[1:0]
res
bit1
bit0
QMode[1:0]
QBits[1:0] - Quantization bits. A value of 0 represents 4 bits. QBits = 01 is not valid unless QMode = 00.
QMode[1:0] - Quantization Mode for soft input data. When set to “11,” input data is assumed to be in signed
2’s complement notation (mid-tread). When set to “01,” data is assumed to be mid-riser sign/
magnitude notation. When set to “00,” data is assumed to be mid-riser unsigned. When set to
“10,” data is assumed to be in “half 2’s complement” mid-riser notation. The confidence
mapping for each mode is shown below with four bit quantization.
QMode[1:0]
00
01
10
11
INPUT DATA
TYPE
Unsigned
Sign/Magnitude
Half 2’s Compl
2’s Complement
HARD DECISION
0 CONFIDENCE RANGE
Max
...
Min
0000
0111
1000
1000
...
...
...
...
0111
0000
1111
1111
7.6
DATA INPUT/OUTPUT CONFIGURATION
7.6.1
TRANSFER WORD SIZE
HARD DECISION
NO
1 CONFIDENCE RANGE
CONFIDENCE
N/A
N/A
N/A
0000
Min
...
Max
1000
1000
0000
0001
...
...
...
...
1111
1111
0111
0111
Read/Write
Encoder Reset Value (hex) =e0
Decoder Reset Value (hex) =e0
address
0x27
bit7
bit6
res
bit5
xWordEqBlk
bit4
bit3
bit2
bit1
xWordSize[4:0]
bit0
xWordEqBlk - Word size equals block size. Only valid when port is configured as a synchronous port
(x_MODE = 0). When set, the input port expects 1 x_FS per block and the output will generate
1 x_FS per block. When cleared, the input port expects 1 x_FS pulse for every xWordSize[4:0]
input bits and the output port generates 1 x_FS pulse for every xWordSize[4:0] output bits.
xWordSize[4:0] - Word size. Only valid when port is configured as a synchronous port (x_MODE = 0) and
xWordEqBlk is cleared. The input port expects 1 x_FS pulse for every xWordSize[4:0] input
bits and the output port generates 1 x_FS pulse for every xWordSize[4:0] output bits. Valid
values for xWordSize[4:0] range from 2 to 32 bits. When set to 0, xWordSize[4:0] is 32 bits.
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7.7
CONTROL AND STATUS
7.7.1
CONTROL
Read/Write
Reset Value (hex) = 00
address
bit7
0x26
xNoConfig
bit6
DStatus
bit5
bit4
bit3
xGOutConfig[2:0]
bit2
xNoBlock
bit1
bit0
xConfigSelect[1:0]
xGOutConfig[2:0] - General output control. These registers control the state of the general output signals
(E_GOUT and D_GOUT). The general outputs can be driven to a 1 or 0, or any one of six
signals can be muxed to either of the general output signals. This is used for system debugging
or control of an external device. The following table shows the options for each GOUT signal.
Note that xGOutConfig[2] is only used in the decoder.
DGOut
Config[2:0]
0
1
2
3
4
5*
EGOut
Config[1:0]
0
1
2
3*
SELECTED OUTPUT SIGNAL
Drive D_GOUT to 0 (low).
Drive D_GOUT to 1 (high).
Drive decoder load complete event. D_OUT will change state each time the
decoder completes loading one block of data.
Drive decode complete event. D_GOUT will change state each time the
decoder completes decoding one block of data.
Drive unload complete event. D_GOUT will change state each time the
decoder completes unloading one block of data.
Drive D_GOUT to 1 when the decoder datapath is empty, 0 when not empty.
SELECTED OUTPUT SIGNAL
Drive E_GOUT to 0 (low).
Drive E_GOUT to 1 (high).
Drive encoder load complete event. E_GOUT will change state each time the
encoder completes loading one block of data. This is only valid when helical
interleaving is enabled.
Drive E_OUT to 1 when the encoder datapath is empty and not processing a
block, 0 when not empty or processing a block.
* The datapath empty flags may assert between a configuration read request and the read data output.
xNoBlock - No block input following configuration. This bit is written to indicate that the configuration
write cycle will not be followed by data. The xNoBlock bit must be written to a 1 for each set
of configuration cycles that is not finished with a configuration read, or followed by a data
block. The xNoBlock bit is automatically cleared between blocks. Reads of xNoBlock will
always return a 0.
xNoConfig - No configuration cycles. This bit is written after configuration 0 is programmed and no further
configuration is needed. The configuration cycle with xNoConfig set must be the last
configuration cycle. The AHA4524 expects data to follow this configuration cycle unless
xNoBlock is set.
DStatus -
Decoder Status. When this bit is asserted, a status footer is attached at the end of every decoded
block. The status footer contains the Corrections count and the CRCErr flag.
xConfigSelect[1:0] - Configuration Select. Used to select one of the four programmed block configurations.
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7.7.2
STATUS AND CORRECTION COUNT (DECODER ONLY)
Read Only
Reset Value (hex) = 00 00
address
0x3b
0x3c
bit7
bit6
res
bit5
bit4
bit3
CRCErr
Corrections[7:0]
bit2
bit1
Corrections[11:8]
bit0
Corrections[11:0] - Corrections per block. The total number of bits corrected by the TPC decoder in the
previous block. This value may be output as a footer at the end of the TPC block when DStatus
is set. The Corrections count value can only be read when the decoder datapath is empty. The
Corrections value applies to the last decoded block. Writes to these bits have no effect.
CRCErr - CRC verification error. This decoder signal is asserted when the data block did not pass the CRC
verification. This value may be output as a footer at the end of the TPC block when DStatus is
set. The CRCErr status is updated with the last read of a block and is valid until the last read
of the next block. A write to this bit has no effect.
7.7.3
ACTUAL ITERATIONS (DECODER ONLY)
Read Only
Reset Value (hex) = 00
address
0x3d
bit7
bit6
bit5
bit4
bit3
ActualIterations[7:0]
bit2
bit1
bit0
ActualIterations[7:0] - Iterations per block. This is the actual number of iterations performed on the previous
block. This number will always equal Iterations when StopIter is not asserted. The
ActualIterations count value can only be read when the decoder datapath is empty. The
ActualIterations value applies to the last decoded block. ActualIterations may be used as a tool
to tune the Iterations setting for specific noise levels. Writes to these bits have no effect.
7.8
MISCELLANEOUS
7.8.1
VERSION
Read Only
Reset Value (hex) = 2b
address
0x3f
bit7
bit6
bit5
bit4
bit3
xVersion[7:0]
bit2
bit1
bit0
xVersion[7:0] - Version number of the device.
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8.0
SIGNAL DESCRIPTIONS
This section contains descriptions for all the pins. Each signal has a type code associated with it. The
type codes are described in the following table.
TYPE CODE
I
O
8.1
DESCRIPTION
Input only pin
Output only pin
SYSTEM CONTROL AND MISCELLANEOUS
SIGNAL
TYPE
DESCRIPTION
RESET_N
TRISTATE_N
TESTMODE
SCANMODE
I
I
I
I
DPARINPUT
I
PLL_BYPASS
I
E_MODE
I
D_MODE
I
E_CS_N
I
D_CS_N
I
SYSCLK
I
E_GOUT
O
D_GOUT
O
RDYPOLARITY
I
ACPTPOLARITY
I
Refer to Section 11.6 Reset_n Timing for RESET_N timing rules.
When low, all outputs are tristated. Tie high for normal operation.
Test mode input signal. Tie low for normal operation.
Scan mode input signal. Tie low for normal operation.
Decoder parallel input. When DPARINPUT = 1 on the RESET_N rising
edge, C_DATA[3:0] is configured as a 4 bit input bus. When DPARINPUT
= 0 on the RESET_N rising edge, C_DATA[0] is configured as a serial input.
PLL bypass input signal. Tie low for normal operation.
Encoder interface mode. When E_MODE = 0 on the RESET_N rising edge,
the encoder interface is configured as a synchronous port. When E_MODE =
1 on the RESET_N rising edge, the encoder interface is configured as a bus
interface.
Decoder interface mode. When D_MODE = 0 on the RESET_N rising edge,
the decoder interface is configured as a synchronous port. When D_MODE =
1 on the RESET_N rising edge, the decoder interface is configured as a bus
interface.
Encoder chip select, active low. When deasserted, E_DATA and E_FS are
tristated.
Decoder chip select, active low. When deasserted, D_DATA and D_FS are
tristated.
System Clock.
Encoder general output signal. The functionality of this signal is configured in
Section 7.7.1 Control.This signal is driven from an internal clock domain.
There is no timing relationship between the external clocks and the GOUT
signals.
Decoder general output signal. The functionality of this signal is configured
in Section 7.7.1 Control. This signal is driven from an internal clock domain.
There is no timing relationship between the external clocks and the GOUT
signals.
Ready polarity signal. When RDYPOLARITY = 1, E_RDY and D_RDY
are active high. When RDYPOLARITY = 0, E_RDY and D_RDY are active
low. This can only change when RESET_N is asserted.
Accept polarity signal. When ACPTPOLARITY = 1, U_ACPT and
C_ACPT are active high. When ACPTPOLARITY = 0, U_ACPT and
C_ACPT are active low. This input can only change when RESET_N is
asserted.
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8.2
UNENCODED DATA INTERFACE
SIGNAL
U_CLK
or
U_WR_N
U_DATA
TYPE
Unencoded Input Data.
When E_MODE = 0,
U_DATA is synchronous to U_CLK. Data is transferred into the device
on the rising edge of U_CLK.
I
I
U_ACPT
O
8.3
Unencoded Data Clock. Refer to Section 11.2 U_CLK, E_CLK, C_CLK,
D_CLK Clock Timing for timing rules.
I
U_FS
DESCRIPTION
When E_MODE = 1,
U_DATA is latched on the rising edge of U_WR_N.
Unencoded Frame Sync. Only used when E_MODE = 0, U_FS is
synchronous to U_CLK. Indicates to the device that data will be transferred
on the next rising edge of U_CLK.
Unencoded Data Accept. Indicates that the device can accept U_DATA. The
polarity of this signal is selected with the ACPTPOLARITY pin.
ENCODED DATA INTERFACE
SIGNAL
E_CLK
or
E_RD_N
E_DATA
TYPE
DESCRIPTION
I
Encoded Data Clock. Refer to Section 11.2 U_CLK, E_CLK, C_CLK, D_CLK
Clock Timing for timing rules.
O
E_FS
O
E_RDY
O
PS4524_0204
Encoded Output Data.
When E_MODE = 0,
E_DATA is synchronous to E_CLK. Data is transferred into the device
on the rising edge of E_CLK.
When E_MODE = 1,
E_DATA is transferred on the rising edge of E_RD_N.
Encoded Frame Sync. Only used when E_MODE = 0, E_FS is synchronous
to E_CLK. Indicates to the device that data will be transferred on the next
rising edge of E_CLK.
Encoded Data Ready. Indicates that the device has data ready to be transferred
across E_DATA. The polarity of this signal is selected with the
RDYPOLARITY pin.
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8.4
CHANNEL DATA INTERFACE
SIGNAL
C_CLK
or
C_WR_N
TYPE
DESCRIPTION
I
Channel Data Clock. Refer to Section 11.2 U_CLK, E_CLK, C_CLK, D_CLK
Clock Timing for timing rules.
Channel Input Data.
When D_MODE = 0,
C_DATA[3:0] is synchronous to C_CLK. Data is transferred into the
device on the rising edge of C_CLK.
C_DATA[3:0]
I
C_FS
I
C_ACPT
O
8.5
When D_MODE = 1,
C_DATA[3:0] is latched on the rising edge of C_WR_N.
If DPARINPUT = 1 on the rising edge of RESET_N, data is received in
parallel on C_DATA[3:0]. If DPARINPUT = 0 on the rising edge of
RESET_N, data is received serially on C_DATA[0].
Channel Frame Sync. Only used when D_MODE = 0, C_FS is synchronous
to C_CLK. Indicates to the device that data will be transferred on the next
rising edge of C_CLK.
Channel Data Accept. Indicates that the device can accept C_DATA. The
polarity of this signal is selected with the ACPTPOLARITY pin.
DECODED DATA INTERFACE
SIGNAL
D_CLK
or
D_RD_N
D_DATA
TYPE
DESCRIPTION
I
Decoded Data Clock. Refer to Section 11.2 U_CLK, E_CLK, C_CLK, D_CLK
Clock Timing for timing rules.
O
D_FS
O
D_RDY
O
Page 38 of 58
Decoded Output Data.
When D_MODE = 0,
D_DATA is synchronous to D_CLK. Data is transferred into the device
on the rising edge of D_CLK.
When D_MODE = 1,
D_DATA is transferred on the rising edge of D_RD_N.
Decoded Frame Sync. Only used when D_MODE = 0, D_FS is synchronous
to D_CLK. Indicates to the device that data will be transferred on the next
rising edge of D_CLK.
Decoded Data Ready. Indicates that the device has data ready to be transferred
across D_DATA. The polarity of this signal is selected with the
RDYPOLARITY pin.
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9.0
PINOUT
Table 7:
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PS4524_0204
Pinout - Pin Number Order
SIGNAL
C_ACPT
GNDIO
VDDIO
DPARINPUT
GND
C_CLK
VDD
C_FS
RDYPOLARITY
ACPTPOLARITY
C_DATA[3]
C_DATA[2]
VDD
GND
C_DATA[1]
C_DATA[0]
SCANMODE
E_CS_N
VDD
GND
E_FS
E_DATA
GNDIO
VDDIO
E_CLK
VDD
GND
E_RDY
GND
E_GOUT
VDD
E_MODE
PIN
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SIGNAL
U_ACPT
GNDIO
VDDIO
U_CLK
U_FS
GND
VDD
U_DATA
SYSCLK
AGND
VAD
PLL_BYPASS
VDD
GND
TRISTATE_N
TESTMODE
VDD
GND
RESET_N
D_CS_N
VDD
D_FS
GND
D_DATA
GNDIO
VDDIO
D_CLK
VDD
GND
D_RDY
D_GOUT
D_MODE
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TESTMODE
TRISTATE_N
GND
VDD
PLL_BYPASS
VAD
AGND
SYSCLK
U_DATA
VDD
GND
U_FS
U_CLK
44
43
42
41
40
39
38
37
36
35
34
33
VDDIO
GNDIO
U_ACPT
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LLLLL
YYWWD
E_MODE
VDD
E_GOUT
GND
E_RDY
GND
VDD
E_CLK
VDDIO
GNDIO
E_DATA
E_FS
GND
VDD
E_CS_N
SCANMODE
14
15
16
5
6
7
8
9
10
11
12
13
56
57
58
59
60
61
62
63
64
GND
C_CLK
VDD
C_FS
RDYPOLARITY
ACPTPOLARITY
C_DATA[3]
C_DATA[2]
VDD
GND
C_DATA[1]
C_DATA[0]
D_DATA
GNDIO
VDDIO
D_CLK
VDD
GND
D_RDY
D_GOUT
D_MODE
AHA4524A
031 PTC
1
2
3
4
49
50
51
52
53
54
55
C_ACPT
GNDIO
VDDIO
DPARINPUT
VDD
GND
RESET_N
D_CS_N
VDD
D_FS
GND
48
47
46
45
Figure 26: Pinout
Note: YYWWD = Date Code; LLLLL = Lot Number
Page 40 of 58
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comtech aha corporation
10.0 DC ELECTRICAL SPECIFICATIONS
Information in this section represents design goals. While every effort will be made to meet these goals,
values presented should be considered targets until characterization is complete. Please consult with
Advanced Hardware Architectures for the most up-to-date values.
10.1 OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
Vdd
Vddio
Vad
Idd
Iddio
Idd
Iddio
Idd
Iddio
Ta
Vil
Vih
Iin
Vol
Voh
Iol
Ioh
Ioz
Cin
Cio
Cout
Core Supply voltage (1.8V nominal)
Input/Output Supply Voltage (3.3V nominal)
Analog PLL Supply Voltage (1.8V nominal)
Supply current (static)
Input/Output Supply current (static)
Supply current (active)
Input/output supply current (active)
Supply current (active)
Input/Output Supply current (active)
Ambient temperature
Input low voltage
Input high voltage
Input leakage current
Output low voltage (Iol=-2mA)
Output high voltage (Ioh=2mA)
Output low current
Output high current
Output leakage current during tristate
Input capacitance
Input/Output capacitance
Output load capacitance
1.7
3.0
1.7
1.9
3.6
1.9
1
0.6
110
8
70
6
70
0.8
5.5
5
0.4
V
V
V
mA
mA
mA
7
7
3
0
-0.3
2.0
-5
mA
mA
°C
V
V
uA
V
V
mA
mA
uA
pF
pF
pF
2.4
8
8
5
10
10
30
-5
5
5
6
6
2
4
1
Notes:
1) Timings referenced to this load.
2) May require external heat sink.
3) See Appendix A for Vad recommendations.
4) Measured at 0V and Vddio nominal.
5) At maximum SYSCLK frequency, nominal Vdd and Vddio, and Full Duplex operation.
6) At maximum SYSCLK frequency, nominal Vdd and Vddio, and Encode operation.
7) During power on sequencing, Vdd must reach 1.7V concurrent or before Vddio reaches 1.7V.
10.2 ABSOLUTE MAXIMUM STRESS RATINGS
SYMBOL
Tstg
Vsupply
Vpin
PS4524_0204
PARAMETER
Storage temperature
Supply voltage
Voltage applied to any signal pin
MIN
MAX
UNITS
-50
-0.5
150
4.6
6.0
°C
V
V
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NOTES
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comtech aha corporation
10.3 TEST CONDITIONS
PARAMETER
VALUE
AC timing reference
*
1.4 V
The timing diagrams for these signals assume a capacitive load of 30pF. The specified signal timings must be
derated by the factor shown in Figure 27 when operating at loads other than 30pF.
Multiplication Factor
Figure 27: Signal Timing vs. Output Load
LOAD
MULTIPLICATION
CAPACITANCE
FACTOR
1.15
10 pF
20 pF
30 pF
40 pF
50 pF*
0.86
10
Page 42 of 58
20
30
40
Load Capacitance (pF)
50
0.86
0.92
1.00
1.07
1.15
*Production test conditions
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11.0 AC ELECTRICAL SPECIFICATIONS
11.1 SYSCLK CLOCK TIMING
Figure 28: SYSCLK Clock Timing
1
2
2.0V
1.4V
0.8V
SYSCLK
3
4
5
Table 8:
NUMBER
1
2
3
4
5
Table 9:
NUMBER
1
2
3
4
5
PS4524_0204
SYSCLK Clock Timing with PLLBYPASS = 0
PARAMETER
SYSCLK rise time
SYSCLK fall time
SYSCLK high time
SYSCLK low time
SYSCLK period (Tcp)
SYSCLK frequency
Cycle to cycle jitter
Long term jitter
MIN
MAX
UNITS
1
1
8
8
32
20
-125
-200
50
125
200
ns
ns
ns
ns
ns
MHz
ps
ps
MIN
MAX
UNITS
1
1
ns
ns
ns
ns
ns
MHz
ps
ps
SYSCLK Clock Timing with PLLBYPASS = 1
PARAMETER
SYSCLK rise time
SYSCLK fall time
SYSCLK high time
SYSCLK low time
SYSCLK period (Tcp)
SYSCLK frequency
Cycle to cycle jitter
Long term jitter
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2
2
5
-125
-200
200
125
200
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11.2 U_CLK, E_CLK, C_CLK, D_CLK CLOCK TIMING
Figure 29: Clock Timing
1
2
2.0V
1.4V
0.8V
x_CLK
3
4
5
Table 10:
Clock Timing
NUMBER
1
2
3
4
5
5
PARAMETER
MIN
U_CLK, E_CLK, C_CLK, D_CLK rise time
U_CLK, E_CLK, C_CLK, D_CLK fall time
U_CLK, E_CLK, C_CLK, D_CLK high time
U_CLK, E_CLK, C_CLK, D_CLK low time
U_CLK, E_CLK, C_CLK, D_CLK frequency with
PLLBYPASS = 0.
U_CLK, E_CLK, C_CLK, D_CLK frequency with
PLLBYPASS = 1.
MAX
UNITS
2
2
ns
ns
ns
ns
4
4
1.9*SYSCLK MHz
SYSCLK/2.1
MHz
11.3 U_WR_N, E_RD_N, C_WR_N, D_RD_N STROBE TIMING
Figure 30: Strobe Timing
1
2
2.0V
1.4V
0.8V
x_WR_N, x_RD_N
3
4
5
Table 11:
NUMBER
1
2
3
4
5
5
Page 44 of 58
Strobe Timing with PLLBYPASS = 0
PARAMETER
MIN
U_WR_, E_RD_N, C_WR_N, D_RD_N rise time.
U_WR_, E_RD_N, C_WR_N, D_RD_N fall time.
U_WR_, E_RD_N, C_WR_N, D_RD_N high time.
U_WR_, E_RD_N, C_WR_N, D_RD_N low time.
U_WR_, E_RD_N, C_WR_N, D_RD_N frequency with
PLLBYPASS = 0.
U_WR_, E_RD_N, C_WR_N, D_RD_N frequency with
PLLBYPASS = 1.
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MAX
UNITS
2
2
ns
ns
ns
ns
SYSCLK
MHz
SYSCLK/4
MHz
8
8
PS4524_0204
comtech aha corporation
11.4 SYNCHRONOUS DATA INTERFACE
Figure 31: Encoder Interface Data Input Timing
U_CLK
(input)
t1
t2
U_FS
(input)
t3
t4
U_DATA
(input)
configuration
data
U_ACPT
(output)
t5
E_CS_N
(input)
Table 12:
NUMBER
t1
t2
t3
t4
t5
Encoder Interface Data Input Timing
PARAMETER
U_FS setup to U_CLK.
U_FS hold from U_CLK.
U_DATA setup to U_CLK.
U_DATA hold from U_CLK.
E_CS_N setup to U_CLK rising edge that
U_FS is asserted.
MIN
MAX
UNITS
5
3
5
3
ns
ns
ns
ns
9
ns
NOTES
Notes:
1) U_ACPT is driven from an internal clock domain. There is no timing relationship between U_CLK and U_ACPT.
The function of U_ACPT is to indicate that the encoder can accept a block of data. U_ACPT deasserts following
the first data transfer or after a configuration read is started.
2) There is no timing relationship between U_CLK and SYSCLK.
PS4524_0204
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Figure 32: Decoder Interface Data Input Timing
C_CLK
(input)
t1
t2
C_FS
(input)
t3
t4
C_DATA[0]
(input)
configuration
data
C_ACPT
(output)
t5
D_CS_N
(input)
Table 13:
NUMBER
t1
t2
t3
t4
t5
Decoder Interface Data Input Timing
PARAMETER
C_FS setup to C_CLK.
C_FS hold from C_CLK.
C_DATA[0] setup to C_CLK.
C_DATA[0] hold from C_CLK.
D_CS_N setup to C_CLK rising edge that
C_FS is asserted.
MIN
MAX
UNITS
5
3
5
3
ns
ns
ns
ns
9
ns
NOTES
Notes:
1) C_ACPT is driven from an internal clock domain. There is no timing relationship between C_CLK and C_ACPT.
The function of C_ACPT is to indicate that the encoder can accept a block of data. C_ACPT deasserts following
the first data transfer or after a configuration read is started.
2) There is no timing relationship between C_CLK and SYSCLK.
Page 46 of 58
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Figure 33: Encoder Interface Data Output Timing Using Chip Select
E_CLK
(input)
t1
E_FS
t2
HIGH-Z
HIGH-Z
(output)
t6
E_DATA
t2
HIGH-Z
first
typical
HIGH-Z
last
(output)
t3
t1
t7
E_RDY
(output)
t5
t4
E_CS_N
(input)
Table 14:
Encoder Interface Data Output Timing Using Chip Select
NUMBER
PARAMETER
t1
E_FS, E_DATA delay from E_CLK.
E_FS, E_DATA valid from E_CLK following
E_CS_N asserted.
E_FS, E_DATA hold from E_CLK.
E_RDY delay from E_CLK.
E_CS_N setup to E_CLK.
last E_DATA read to E_CS_N deasserted.
E_CS_N asserted to E_FS, E_DATA valid.
E_CS_N deasserted to E_FS, E_DATA tristate.
t1
t2
t3
t4
t5
t6
t7
MIN
MAX
UNITS
8
ns
8
ns
1
8
9
5
8
8
ns
ns
ns
SYSCLK
ns
ns
NOTES
1
1
Notes:
1) It is valid for E_CS_N to always be asserted.
2) There is no timing relationship between E_CLK and SYSCLK.
PS4524_0204
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Figure 34: Encoder Interface Data Output Timing
E_CLK
(input)
t1
t2
E_FS
(output)
t2
E_DATA
first
typical
last
(output)
t1
t1
E_RDY
(output)
E_CS_N
(input)
Table 15:
Encoder Interface Data Output Timing
NUMBER
PARAMETER
t1
E_FS, E_RDY, E_DATA delay from E_CLK.
E_FS, E_RDY, E_DATA valid from E_CLK
following E_CS_N asserted.
E_FS, E_DATA hold from E_CLK.
E_RDY delay from E_CLK.
t1
t2
t3
MIN
MAX
UNITS
8
ns
8
ns
8
ns
ns
1
NOTES
1
Notes:
1) It is valid for E_CS_N to always be asserted.
2) There is no timing relationship between E_CLK and SYSCLK.
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Figure 35: Decoder Interface Data Output Timing Using Chip Select
D_CLK
(input)
t1
D_FS
t2
HIGH-Z
HIGH-Z
(output)
t6
D_DATA
t2
HIGH-Z
first
typical
HIGH-Z
last
(output)
t3
t1
t7
D_RDY
(output)
t5
t4
D_CS_N
(input)
Table 16:
Decoder Interface Data Output Timing Using Chip Select
NUMBER
PARAMETER
t1
D_FS, D_DATA delay from D_CLK.
D_FS, D_DATA valid from D_CLK following
D_CS_N asserted.
D_FS, D_DATA hold from D_CLK.
D_RDY delay from D_CLK.
D_CS_N setup to D_CLK.
last D_DATA read to D_CS_N deasserted.
D_CS_N asserted to D_FS, D_DATA valid.
D_CS_N deasserted to D_FS, D_DATA tristate.
t1
t2
t3
t4
t5
t6
t7
MIN
MAX
UNITS
8
ns
8
ns
1
8
9
5
8
8
ns
ns
ns
SYSCLK
ns
ns
NOTES
1
1
Notes:
1) It is valid for D_CS_N to always be asserted.
2) There is no timing relationship between D_CLK and SYSCLK.
PS4524_0204
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Figure 36: Decoder Interface Data Output Timing
D_CLK
(input)
t1
t2
D_FS
(output)
t2
D_DATA
first
typical
last
(output)
t1
t1
D_RDY
(output)
D_CS_N
(input)
Table 17:
Decoder Interface Data Output Timing
NUMBER
PARAMETER
t1
D_FS, D_RDY, D_DATA delay from D_CLK.
D_FS, D_RDY, D_DATA valid from D_CLK
following D_CS_N asserted.
D_FS, D_DATA hold from D_CLK.
D_RDY delay from D_CLK.
t1
t2
t3
MIN
MAX
UNITS
8
ns
8
ns
8
ns
ns
1
NOTES
1
Notes:
1) It is valid for D_CS_N to always be asserted.
2) There is no timing relationship between D_CLK and SYSCLK.
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11.5 BUS INTERFACE
Figure 37: Encoder Bus Interface Data Input Timing
U_WR_N
(input)
t2
t1
t3
U_DATA
(input)
configuration
data
U_ACPT
(output)
t4
E_CS_N
(input)
Table 18:
NUMBER
t1
t1
t2
t3
t4
Encoder Bus Interface Data Input Timing
PARAMETER
U_WR_N frequency with PLLBYPASS = 0.
U_WR_N frequency with PLLBYPASS = 1.
U_DATA setup to U_WR_N rising edge.
U_DATA hold from U_WR_N rising edge.
E_CS_N valid before U_WR_N strobe rising
edge.
MIN
MAX
UNITS
NOTES
SYSCLK
SYSCLK/4
2, 3
2, 3
5
3
MHz
MHz
ns
ns
9
ns
Notes:
1) U_ACPT is driven from an internal clock domain. There is no timing relationship between U_WR_N and U_ACPT.
The function of U_ACPT is to indicate that the encoder can accept a block of data. U_ACPT deasserts following
the first data transfer or after a configuration read is started.
2) There is no timing relationship between U_WR_N and SYSCLK.
3) U_WR_N is used internally as a clock. U_WR_N must not glitch.
PS4524_0204
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Figure 38: Decoder Bus Interface Data Input Timing
C_WR_N
(input)
t2
t1
t3
C_DATA
(input)
configuration
data
C_ACPT
(output)
t4
D_CS_N
(input)
Table 19:
Decoder Bus Interface Data Input Timing
NUMBER
PARAMETER
t1
t1
t2
t3
t4
C_WR_N frequency with PLLBYPASS = 0.
C_WR_N frequency with PLLBYPASS = 1.
C_DATA setup to C_WR_N rising edge.
C_DATA hold from C_WR_N rising edge.
D_CS_N valid before C_WR_N strobe rising edge.
MIN
MAX
UNITS
NOTES
SYSCLK
SYSCLK/4
MHz
MHz
ns
ns
ns
2, 3
2, 3
5
3
9
Notes:
1) C_ACPT is driven from an internal clock domain. There is no timing relationship between C_CLK and C_ACPT.
The function of C_ACPT is to indicate that the encoder can accept a block of data. C_ACPT deasserts following
the first data transfer or after a configuration read is started.
2) There is no timing relationship between C_WR_N and SYSCLK.
3) C_WR_N is used internally as a clock. C_WR_N must not glitch.
Page 52 of 58
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Figure 39: Encoder Bus Interface Data Output Timing
E_RD_N
(input)
t1
E_DATA
t2
t3
HIGH-Z
(output)
t4
E_RDY
(output)
t5
E_CS_N
(input)
Table 20:
Encoder Bus Interface Data Output Timing
NUMBER
t1
t1
t2
t3
t4
t5
PARAMETER
MIN
E_RD_N frequency with PLLBYPASS = 0.
E_RD_N frequency with PLLBYPASS = 1.
E_DATA valid from E_RD_N falling edge.
E_DATA hold from E_RD_N rising edge.
E_RDY delay from E_RD_N rising edge.
E_CS_N setup to E_RD_N rising edge.
1
MAX
UNITS
NOTES
SYSCLK
SYSCLK/4
8
5
8
MHz
MHz
ns
ns
ns
ns
1, 2
1, 2
MAX
UNITS
NOTES
SYSCLK
SYSCLK/4
8
5
8
MHz
MHz
ns
ns
ns
ns
1, 2
1, 2
9
Notes:
1) There is no timing relationship between E_RD_N and SYSCLK.
2) E_RD_N is used internally as a clock. E_RD_N must not glitch.
Figure 40: Decoder Bus Interface Data Output Timing
D_RD_N
(input)
t1
D_DATA
t2
t3
HIGH-Z
(output)
t4
D_RDY
(output)
t5
D_CS_N
(input)
Table 21:
Decoder Bus Interface Data Output Timing
NUMBER
PARAMETER
t1
t1
t2
t3
t4
t5
D_RD_N frequency with PLLBYPASS = 0.
D_RD_N frequency with PLLBYPASS = 1.
D_DATA valid from D_RD_N falling edge.
D_DATA hold from D_RD_N rising edge.
D_RDY delay from D_RD_N rising edge.
D_CS_N setup to D_RD_N rising edge.
MIN
1
9
Notes:
1) There is no timing relationship between D_RD_N and SYSCLK.
2) D_RD_N is used internally as a clock. D_RD_N must not glitch.
PS4524_0204
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11.6 RESET_N TIMING
Figure 41: RESET_N Timing
VDD
x_CLK
t2
t1
RESET_N
Table 22:
RESET_N Timing
NUMBER
PARAMETER
t1
RESET_N pulsewidth with E_MODE = 1,
D_MODE = 1, and PLLBYPASS = 0.
RESET_N pulsewidth with E_MODE = 1,
D_MODE = 1, and PLLBYPASS = 1.
RESET_N pulsewidth with E_MODE = 0 or
D_MODE = 0.
PLL lock time
t1
t1
t2
MIN
MAX
UNITS
NOTES
10
SYSCLK
40
SYSCLK
10
TxCLK
1,2,3,4
us
5
10
Notes:
1) If E_MODE = 0 and PLLBYPASS = 0, TxCLK is the period of the lowest frequency of U_CLK, E_CLK and SYSCLK.
2) If E_MODE = 0 and PLLBYPASS = 1, TxCLK is the period of the lowest frequency of U_CLK, E_CLK and SYSCLK/
4.
3) If D_MODE = 0 and PLLBYPASS=0, TxCLK is the period of the lowest frequency of C_CLK, D_CLK and SYSCLK.
4) If D_MODE = 0 and PLLBYPASS=1, TxCLK is the period of the lowest frequency of C_CLK, D_CLK and
SYSCLK/4.
5) SYSCLK must be running for 10us to lock the internal PLL before RESET_N is asserted.
Page 54 of 58
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12.0 PACKAGE SPECIFICATIONS
12.1 PACKAGE DIMENSIONS
Figure 42: Package Dimensions - Top View
D
D1
P
49
50
B
AHA4524A
031 PTC
(LCA)
E1 E
63
64
LLLLL
YYWWD
15 16
(LCB)
Note: YYWWD = Date Code; LLLLL = Lot Number
Figure 43: Package Dimensions - Cross Section View
A
A2 A
L
PS4524_0204
A subsidiary of Comtech Telecommunications Corporation
A1
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comtech aha corporation
Table 23:
TQFP (Thin Quad Flat Pack) 7 x 7 mm Package Dimensions
(All dimensions are in mm)
NUMBER OF PIN AND SPECIFICATION DIMENSION
64
SYMBOL
MIN
(LCA)
(LCB)
A
A1
A2
D
D1
E
E1
L
P
B
Notes:
NOM
16
16
1.1
0.1
1.0
9.0
7.0
9.0
7.0
0.60
0.40
0.18
0.05
0.95
0.45
0.13
MAX
1.2
0.15
1.05
0.75
0.23
All dimensions are in millimeters
More detailed mechanical information is available upon request
13.0 ORDERING INFORMATION
13.1 AVAILABLE PARTS
PART NUMBER
DESCRIPTION
AHA4524A-031 PTC
AHA4524A-031 PTI
4K Block Turbo Product Code Encoder/Decoder
4K Block Turbo Product Code Encoder/Decoder - Industrial Temp
13.2 PART NUMBERING
AHA
4524
A-
031
P
T
C, I
Manufacturer
Device
Number
Revision
Level
Internal
Reference
Package
Material
Package
Type
Temperature
Specification
Device Number:
AHA4524
Revision Letter:
A
Package Material:
P
Plastic
Package Type:
T
Thin Quad Flat Pack
Temperature Specifications:
C Commercial 0°C to +70°C
I Industrial
-40°C to +85°C
Page 56 of 58
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14.0 RELATED TECHNICAL PUBLICATIONS
DOCUMENT #
PB4524
PBGALAXY
PBGALAXY_STK
ANTPC01
ANTPC02
ANTPC03
ANTPC04
ANTPC05
ANTPC06
ANTPC07
ANTPC08
TPCEVAL
PS4524_0204
DESCRIPTION
AHA Product Brief – AHA4524 Astro LE 4K Block Turbo Product Code
Encoder/Decoder
AHA Product Brief – Galaxy Core Generator Turbo Product Code Decoder
Cores
AHA Product Brief – AHA Galaxy Simulation Tool Kit
AHA Application Note – Primer: Turbo Product Codes
AHA Application Note – Use and Performance of Shortened Codes with the
AHA4501 TPC Encoder/Decoder)
AHA Application Note – Turbo Product Code Encoder/Decoder with
Quadrature Amplitude Modulation (QAM)
AHA Application Note – Use and Performance of the AHA4501 TPC Encoder/
Decoder with Differential Phase Shift Keying (DPSK)
AHA Application Note – AHA4501 Turbo Product Code Encoder/Decoder
Designers Guide
AHA Application Note – AHA4501 Turbo Product Code Encoder/Decoder
Frequently Asked Questions (FAQ)
AHA Application Note – Turbo Product Codes for LMDS
AHA Application Note – Using Multiple AHA4501 Devices in Parallel for
Higher Data Rates
AHA Evaluation Software – Turbo Product Codes - Windows Evaluation
Software
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APPENDIX A: VAD RECOMMENDATIONS
Analog Power Supply Filter for PLL usage
The analog power supply for the internal PLL
(Vad) ideally comes from an analog power supply
having low pass filter characteristics of -3dB at <
1KHz, and < -70dB in the absorption band. Actual
component selection will limit the -3dB point and
good board layout is vital to achieving good high
frequency absorption. An R-C or R-L-C filter can be
used, with the “C” being composed of multiple
devices to achieve a wide spectrum of noise
absorption.
For DC reasons the series resistance of this filter
should be limited. There should be considerably
less than 5% voltage drop across the resistor under
worst-case conditions. High quality series inductors
should be used with a series resistor to prevent a
high gain series resonator from being created.
For the low-frequency cutoff an electrolytic
capacitor should be used in the filter design. The
filter also needs to sustain its attenuation into high
frequencies, (e.g. > 100 MHz), so additional nonelectrolytic capacitance should be added in parallel.
All leads of the high frequency capacitor(s) should
be kept short. This includes the board wires, vias,
and component leads, and within the component
package (so select the component carefully). Board
layout around the high-frequency capacitance and
the path from there to the pads is critical. It is vital
that the quiet ground and power are treated like
analog signals.
The power (Vad) path must be a single trace
from the IC package pin to the high frequency
capacitance, then to the low frequency capacitance,
then through the series element (e.g. resistor) then to
board power (Vdd). The distance from the IC pin to
the high frequency cap should be kept as short as
possible.
Figure A1:
The ground (AGND) path should be from the IC
pin to the high frequency capacitance, to the low
frequency capacitance, with the distances being very
short. The PLL has the DC ground connection made
on chip, so the external Gnd pin must not be
connected to PCB ground, but only to the power
supply filter. The power and ground traces should be
run close and parallel as far as possible, with large
spacing between adjacent traces. This will help
minimize noise, especially non common-mode noise
The power loop consisting of the high
frequency capacitor, Vad and Gnd traces to the IC,
and the IC itself must be designed to keep area and
impedance to a minimum. Layout the board to
enable the total analog power circuit to be small
with short and adjacent wire traces. No extra
connections should be made to board power planes;
only connect as described above.
Care should be exercised in component
selection to insure that there are no resonant
absorptions or resonant non-absorptions throughout
the attenuating frequency range,. This means that
the series element will either be a resistor or a very
poor (i.e. resistive) inductor. For a series element
with high impedance (eg. 100 ohms), the
electrolytic is often chosen as the biggest
capacitance tantalum available which fits
reasonably on the board (e.g. 25uF). Similarly, the
other capacitor is typically the largest value high
frequency capacitor available in a small package
(e.g. 100nF).
Example Schematic
This schematic represents an example of both
the circuit and the device placement. Actual
component values may be different.
Example External Circuit Component Configuration
100 Ω
Vad
Vdd
Board
25µF
100nF
Chip
AGND
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PS4524_0204