ETC LD7552IN

2/21/2005
Green-Mode PWM Controller
General Description
Features
The LD7552 is a low cost, low startup current, current mode
High-Voltage CMOS Process with Excellent ESD
PWM controller with green-mode power-saving operation.
Protection
The integrated functions such as the leading-edge blanking
Very Low Startup Current (Typical 5 A)
of the current sensing, internal slope compensation and the
Under Voltage Lockout (UVLO)
small package provide the users a high efficiency, minimum
Current Mode Control with Cycle-by-Cycle Peak
external component counts, and low cost solution for AC/DC
Current Limiting
power applications.
Leading-Edge Blanking on CS Pin
Programmable Switching Frequency
The special green-mode control does not only achieve low
Internal Slope Compensation
power consumption but also offer a non-audible-noise
Proprietary Green-Mode Control for Power Saving
operation when the LD7552 operates under light load or no
Non-audible-noise Green Mode Control
load condition.
500mA Driving Capability
Applications
The LD7552 is designed for the switching adaptor with
30W~60W output. The LD7552 is offered in both SOP-8 and
Switching AC/DC Adaptor and Battery Charger
DIP-8 package.
Open Frame Switching Power Supply
384X Replacement
Note: Please see Application Information
Patent pending
Typical Application
AC
input
EMI
Filter
VCC
40V
OUT
UVLO
16.0V/
11.4V
RT
COMP
LD7552
OSC
Control
Logic
Divider
photocoupler
CS
GND
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TL431
Pin Configuration
OUT
VCC
CS
NC
SOP-8 & DIP-8 (TOP VIEW)
8
7
6
5
YY: Year code (D: 2004, E: 2005…..)
WW: week code
PP: production code
TOP MARK
3
4
RT
2
COMP
GND
1
VCC
YYWWPP
Ordering Information
Part number
Package
TOP MARK
Shipping
LD7552 IS
SOP-8
LD7552IS
2500 /tape & reel
LD7552 BS
SOP-8 (PB Free)
LD7552BS
2500 /tape & reel
LD7552 IN
DIP-8
LD7552IN
3600 /tube /carton
LD7552 BN
DIP-8 (PB Free)
LD7552BN
3600 /tube /carton
Pin Descriptions
PIN
NAME
1
GND
FUNCTION
2
COMP
3
VCC
4
RT
5
NC
Unconnected pin
6
CS
Current sense pin, connect to sense the MOSFET current
7
VCC
Supply voltage pin
8
OUT
Gate drive output to drive the external MOSFET
Ground
Voltage feedback pin (same as the COMP pin in UC384X), By connecting a
photo-coupler to close the control loop and achieve the regulation.
Supply voltage pin
This pin is to program the switching frequency. By connecting a resistor to ground
to set the switching frequency.
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Block Diagram
VCC
UVLO
40V
internal bias
& Vref
16.0V/
11.4V
RT
OSC
EN
Vref OK
EN
OUT
Green-Mode
Oscillator
S
COMP
R
2R
R
CS
Leading
Edge
Blanking
Q
PWM
Comparator
+
+
Ramp from
Oscillator
GND
Absolute Maximum Ratings
Supply Voltage VCC
36V
COMP, RT, CS
-0.3 ~7V
Operating Junction Temperature
150 C
Storage Temperature Range
-65 C to 150 C
Package thermal resistance (DIP-8)
100 C/W
Package thermal resistance (SOP-8)
160 C/W
Lead temperature (LD7552IS & LD7552IN, Soldering, 10sec)
230 C
Lead temperature (LD7552BS & LD7552BN, Soldering, 10sec)
260 C
Caution:
Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.
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Electrical Characteristics
o
(TA = +25 C unless otherwise stated, VCC=15.0V)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage (Vcc Pin)
Startup Current
Operating Current
5
25
A
VCOMP=0V
3
4
mA
VCOMP=3V
2
VCOMP=open
mA
0.7
mA
UVLO (off)
10.4
11.4
12.4
V
UVLO (on)
14.8
16.0
17.5
V
2.2
3.0
mA
Voltage Feedback (Comp Pin)
Short Circuit Current
VCOMP=0V
Open Loop Voltage
COMP pin open
Green Mode Threshold VCOMP
5.0
V
2.35
V
Current Sensing (CS Pin)
Maximum Input Voltage
0.80
0.85
0.90
V
Leading Edge Blanking Time
250
nS
Input impedance
50
K
Delay to Output
300
nS
Oscillator (RT pin)
Frequency
RT=100K
Green Mode Frequency
Fs=66.5KHz
61.5
66.5
71.5
Temp. Stability
(-30 C ~85 C)
5
%
Voltage Stability
(VCC=12V-30V)
2
%
1
V
20
KHz
KHz
Gate Drive Output (OUT Pin)
Output Low Level
VCC=15V, Io=20mA
Output High Level
VCC=15V, Io=20mA
Rising Time
Load Capacitance=1000pF
160
nS
Falling Time
Load Capacitance=1000pF
60
nS
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9
V
Typical Performance Characteristics
17.0
12.2
16.8
16.4
11.8
UVLO (On) (V)
UVLO (Off) (V)
12.0
11.6
11.4
16.0
15.6
15.2
14.8
11.2
14.4
11.0
-40
-20
0
20
40
60
80
100
14.0
-40
120
-20
0
Temperature ( C)
Fig. 2
UVLO (Off) vs. Temperature
72.0
18.2
71.0
18.0
Frequency (KHz)
Frequency (KHz)
Fig. 1
70.0
69.0
68.0
-20
0
20
Fig. 3
40
60
80
100
80
100
120
17.6
17.4
17.0
-40
120
-20
Fig. 4
Frequency vs. Temperature
75.9
75.6
Max. Duty-Cycle (%)
60
17.8
Temperature ( C)
75.3
75.0
74.7
74.4
-40
40
17.2
67.0
66.0
-40
20
Temperature ( C)
UVLO (On) vs. Temperature
-20
0
20
40
60
80
100
120
Temperature ( C)
Fig. 5
Duty-Cycle (max.) vs. Temperature
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0
20
40
60
80
100
120
Temperature ( C)
Green-Mode Frequency vs. Temperature
Application Information
special circuit design, the maximum startup current of
Operation Overview
LD7552 is only 25 A.
The LD7552 is optimized to achieve power saving and
minimize the external components counts. The device
Theoretically, R1 can be very high resistance value.
incorporated several functions to make it ideal to use in
However, higher R1 will cause longer startup time. By
switching power supplies and switching adaptors.
properly select the value of R1 and C1, it can be optimized
Under Voltage Lockout (UVLO)
under the consideration of R1 power consumption and the
An UVLO comparator is included to detect the voltage on
startup time.
the Vcc pin to ensure the supply voltage enough to power
on the LD7552 PWM controller and in addition to drive the
power MOSFET.
AC
input
As shown in Fig. 6, a hysteresis is
EMI
Filter
provided to prevent the shutdown from the voltage dip
R1
Cbulk
during startup. The turn-on and turn-off threshold level are
D1
set at 16V and 11.4V, respectively.
C1
Vcc
VCC
UVLO(on)
OUT
UVLO(off)
LD7552
GND
t
I(Vcc)
operating current
(~ mA)
CS
Fig. 7
startup current
(~uA)
Current Sensing and Leading-edge Blanking
The typical current mode PWM controller feedbacks both
t
current signal and voltage signal to close the control loop
Fig. 6
and achieve regulation. As shown in Fig. 8, the LD7552
detects the primary MOSFET current from the CS pin, which
Startup Current and Startup Circuit
is not only for the peak current mode control but also for the
The typical startup circuit as shown in Fig. 7 powers ups the
pulse-by-pulse
LD7552.
threshold of the current sensing pin is set as 0.85V. Thus
During the startup transient, the Vcc is lower than
the UVLO threshold thus there is no gate pulse generated
from LD7552 to drive power MOSFET.
current
limit.
maximum
voltage
the MOSFET peak current can be calculated as:
Therefore, the
current through R1 is to provide the startup current as well
as charge the capacitor C1.
The
IPEAK (MAX)
Whenever the Vcc voltage is
0 .85 V
RS
higher enough to power on the LD7552 and further to
deliver the gate drive signal, the supply current is provided
from the auxiliary winding of the transformer.
A 250nS leading-edge blanking time is included in the input
The lower
of CS pin to prevent the false-trigger caused by the current
startup current requirement on the PWM controller will help
spike and further to eliminate the need of R-C filter which is
to increase the R1 value and then reduce the power
usually needed in the typical UC384X application (Fig. 9).
consumption on R1. By using CMOS process and the
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Oscillator and Switching Frequency
Vin
Connecting a resistor from RT pin to GND according to the
R1
Cbulk
equation can program the normal switching frequency:
D1
fSW
C1
VCC
The suggested operating frequency range of LD7552 is
OUT
within 50KHz to 130KHz.
LD7552
Comp
66.5
100(KHz)
RT(K )
CS
GND
Rs
Voltage Feedback Loop
The voltage feedback signal is provided from the TL431 in
the secondary side through the photocoupler to the COMP
Fig. 8
pin of LD7552.
The input stage of LD7552, like the
UC384X, is with 2 diodes voltage offset then feeding into the
voltage divider with 1/3 ratio, that is,
1
( VCOMP
3
V (PWMCOMPARATOR )
2 VF )
A pull-high resistor is embedded internally thus can be
eliminated on the external circuit.
250ns
blanking
time
VCC
Internal Slope Compensation
OUT
A fundamental issue of current mode control is the stability
problem when its duty-cycle is operated more than 50%. To
LD7552
stabilize the control loop, the slope compensation is needed
in the traditional UC384X design by injecting the ramp signal
CS
from the RT/CT pin through a coupling capacitor. In LD7552,
GND
the
internal
slope
compensation
circuit
has
been
implemented to simplify the external circuit design.
remove
On/Off Control
Fig. 9
The LD7552 can be controlled to turn off by pulling COMP
pin to lower than 1.2V. The gate output pin of LD7552 will
Output Stage and Maximum Duty-Cycle
be disabled immediately under such condition. The off mode
An output stage of a CMOS buffer, with typical 500mA
can be released when the pull-low signal is removed.
driving capability, is incorporated to drive a power MOSFET
directly.
And the maximum duty-cycle of LD7552 is limited
Dual-Oscillator Green-Mode Operation
to 75% to avoid the transformer saturation.
There
are
many
difference
topologies
has
been
implemented in different chips for the green-mode or power
saving
requirements
such
as
“burst-mode
control”,
“skipping-cycle Mode”, “variable off-time control “…etc. The
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basic operation theory of all these approaches intended to
By using this dual-oscillator control, the green-mode
reduce the switching cycles under light-load or no-load
frequency can be well controlled and further to avoid the
condition either by skip some switching pulses or reduce the
generation of audible noise.
switching frequency.
What LD7552 used to implement the power-saving
"Set" Signal
(to OSC & Nor gate)
from OSC
operation is Leadtrend Technology’s own IP .
In such
approach, as shown in the block diagram, 2 oscillators are
implemented in LD7552. The first oscillator is to take care
the normal switching frequency, which can be set by the RT
Level-detector
& Counter
VCO
Green-Mode
Oscillator
Vgreen
pin through an external resistor. Under this operation mode,
(V+ -Vgreen) >=0, VCO disabled
(V+ -Vgreen) <0, VCO activated
as shown in Fig. 10, the 2nd oscillation (green-mode
oscillator) is not activated. Therefore, the rising-time and the
V+
V+
falling-time of the internal ramp will be constant to achieve
good stability over all temperature range.
Normal Mode
Under the
normal operation, this oscillator is dominated the switching
frequency.
Ramp of
OSC
Green-Mode Osc is not activated
under normal operation.
OSC
Green-Mode
Oscillator activated
EN=1
EN
OUT
Green-Mode
Osc
Ramp of
VCO
Set
Reset
2R
R
V-
R
CS
S
V+
COMP
LEB
Fig. 11
Q
PWM
Comparator
+
+
Ramp from
Oscillator
Note: Patent pending
Fig. 10
As shown in Fig. 11, the green-mode oscillator detects the
Comp pin signal to determine if it is within the green-mode
operation. When the detected signal V+ is lower than the
green-mode threshold Vgreen, the green-mode oscillator is
on. The green-mode oscillator, implemented by a VCO
(voltage controlled oscillator), is a variable frequency
oscillator. The rising time of the VCO is proportional to
(Vgreen-V+), thus the lower voltage on V+ will generate
longer rising time on VCO as well as lower frequency on
VCO.
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Vgreen
Green Mode
V-
Package Information
SOP-8
H
A
M
J
B
F
C
I
D
Dimensions in Millimeters
Dimensions in Inch
Symbols
MIN
MAX
MIN
MAX
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.178
0.229
0.007
0.009
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
M
0.406
1.270
0.016
0.050
0°
8°
0°
8°
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DIP-8
A
B
E
J
C
F
Dimension in Millimeters
Dimensions in Inches
Symbol
Min
Max
Min
Max
A
9.017
10.160
0.355
0.400
B
6.096
7.112
0.240
0.280
C
-----
5.334
------
0.210
D
0.356
0.584
0.014
0.023
E
1.143
1.778
0.045
0.070
F
2.337
2.743
0.092
0.108
I
2.921
3.556
0.115
0.14
J
7.366
8.255
0.29
0.325
L
0.381
------
0.015
--------
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should
verify the datasheets are current and complete before placing order.
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