LM1212 230 MHz Video Amplifier System with OSD Blanking Y General Description Y The LM1212 is a very high frequency video amplifier system intended for use in high resolution monochrome or RGB color monitor applications with OSD. In addition to the wideband video amplifier the LM1212 contains a gated differential input black level clamp comparator for brightness control, a DC controlled attenuator for contrast control and a DC controlled sub contrast attenuator for drive control. The DC control for the contrast attenuator is pinned out separately to provide a more accurate control system for RGB color monitor applications. All DC controls offer a high input impedance and operate over a 0V–4V range for easy interface to bus controlled alignment systems. During the OSD window, the output is blanked to k 0.4V. The LM1212 operates from a nominal 12V supply but can be operated with supply voltages down to 8V for applications that require reduced IC package power dissipation characteristics. Y Y Y Y Y Applications Y Y Y Y Features Y Y Externally gated comparator for brightness control 0V to 4V high input impedance DC contrast control (l 40 dB range) 0V to 4V high input impedance DC drive control ( g 3 dB range) Ouput blanked to k 0.4V for OSD window Easy to parallel three LM1212s for optimum color tracking in RGB systems Output stage clamps to 0.65V and provides up to 9V output voltage swing Output stage directly drives most hybrid or discrete CRT amplifier stages High resolution CRT monitors with OSD Video switches Video AGC amplifier Wideband amplifier with gain and DC offset control Wideband video amplifier (fb3 dB e 230 MHz at VO e 4 VPP) tr, tf e 1.5 ns at VO e 4 VPP Block and Connection Diagram TL/H/12354 – 1 Order Number LM1212N See NS Package Number N20A C1996 National Semiconductor Corporation TL/H/12354 RRD-B30M86/Printed in U. S. A. http://www.national.com LM1212 230 MHz Video Amplifier System with OSD Blanking August 1996 Absolute Maximum Ratings (Note 1) Junction Temperature (TJ) Storage Temperature Range (Tstg) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage VCC Pins 4, 7, 16 to Ground Pins 5, 13, 15 Voltage at Any Input Pin (VIN) 150§ C b 65§ C to a 150§ C Lead Temperature N Package (Soldering, 10 sec.) 15V 265§ C ESD Susceptibility Human Body Model: 100 pF Discharged through a 1.5k Resistor VCC t VIN t GND Video Output Current (I17) 28 mA 1.56W Package Power Dissipation at TA e 25§ C (Above 25§ C Derate Based iJA and TJ) Package Thermal Resistance (iJA) N20A 68§ C/W 2 kV Operating Ratings (Note 2) Temperature Range Supply Voltage (VCC) b 20§ C to a 80§ C 8V s VCC s 13.2V DC Electrical Characteristics See Test Circuit (Figure 1) , TA e 25§ C, V4 e V7 e V16 e 12V, S1 Open, V19 e 4V, V8 e 4V, V9 e 4V, V14 e 0V unless otherwise noted. Symbol Parameter Conditions RLoad e % (Note 5) Typical (Note 3) Limit (Note 4) Units 51 80 mA (max) 2.9 2 V (min) 0.8 V (max) 2 V (min) IS 4, 7, 16 Total Supply Current V6 Video Input Bias Voltage V14L Clamp Gate Low Input Voltage Clamp Comparator On V14H Clamp Gate High Input Voltage Clamp Comparator Off I14L Clamp Gate Low Input Current V14 e 0V b 0.5 I14H Clamp Gate High Input Current V14 e 12V 0.005 I12 a Clamp Cap Charge Current I12b Clamp Cap Discharge Current V17L Video Output Low Voltage V17H Video Output High Voltage 10 9 V (min) VOS Comparator Input Offset Voltage V18 b V19 30 g 75 mV (max) V20L Blank Gate Low Input Voltage Blank Gate Off 1.2 0.8 V (max) V20H Blank Gate High Input Voltage Blank Gate On 2.6 3 V (min) I20L Blank Gate Low Input Current V20 e 0.8V 0.01 1 mA (max) I20H Blank Gate High Input Current V20 e 3V 33 200 mA (max) V17(blanked) Blanked Output Voltage V20 e 3V 0.3 0.8 V (max) mA mA 800 500 mA (min) b 800 b 500 mA (min) 0.2 0.65 V (max) AC Electrical Characteristics See Test Circuit (Figure 1) , TA e 25§ C, V4 e V7 e V16 e 12V, S1 Closed, V19 e 4V, V8 e 4V, V9 e 4V, V14 e 0V unless otherwise noted. Symbol Parameter Conditions Typical (Note 3) Limit (Note 4) Units 14 V/V (min) b 38 b 20 dB (min) 6 4.5 dB (min) RIN Video Amplifier Input Resistance fIN e 12 kHz 20 AV max Video Amplifier Gain V8 e 4V, V9 e 4V 20 DAV 2V Attenuation at 2V Ref: AV max, V8 e 2V b6 DAV 0.5V Attenuation at 0.5V Ref: AV max, V8 e 0.5V kX dB D Drive D Gain Range V9 e 0V to 4V THD Video Amplifier Distortion VO e 4 VPP, fIN e 12 kHz 0.5 % fb3 dB Video Amplifier Bandwidth (Note 6) VO e 4 VPP 230 MHz tr Output Rise Time (Note 6) VO e 4 VPP 1.5 ns tf Output Fall Time (Note 6) VO e 4 VPP 1.5 ns http://www.national.com 2 Electrical Characteristics (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. For guaranteed specifications and test conditions see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: Typical specifications are specified at a 25§ C and represent the most likely parametric norm. Note 4: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 5: The supply current specified is the quiescent current for VCC1, VCC2 and VCC3 with RLoad e % , see Figure 1’s test circuit. The total supply current also depends on the output load, RLoad. The increase in device power dissipation due to RLoad must be taken into account when operating the device at the maximum ambient temperature. Note 6: When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit board is recommended. The measured rise and fall times are effective rise and fall times, taking into account the rise and fall times of the generator and the oscilloscope. Test Circuit TL/H/12354 – 2 FIGURE 1. LM1212 Test Circuit 3 http://www.national.com Typical Performance Characteristics (VCC e 12V, TA e 25§ C unless otherwise specified) Attenuation vs Drive Control Voltage Quiescent Supply Current vs Supply Voltage TL/H/12354–3 TL/H/12354 – 4 Contrast vs Frequency Drive vs Frequency TL/H/12354 – 6 TL/H/12354–5 Attenuation vs Contrast Control Voltage TL/H/12354 – 7 http://www.national.com 4 Circuit Description Figure 2 shows a block diagram of the LM1212 video amplifier along with contrast and brightness (black level) control. Contrast control is a DC-operated attenuator which varies the AC gain of the amplifier. Signal attenuation (contrast) is achieved by varying the base drive to a differential pair and thereby unbalancing the current through the differential pair. As shown in Figure 2 , a 5.3V bias voltage is internally connected to the positive input of the attenuator and to Pin 1. Pin 3 provides a control voltage for the negative input (pin 2) of the attenuator. The voltage at pin 3 varies as the voltage at the contrast control input (pin 8) varies thus providing signal attenuation. The gain is maximum (0 dB attenuation) if the voltage at pin 8 is 4V and is minimum (maximum attenuation) if the voltage at pin 8 is 0V. The 0V to 4V DC-operated drive control at pin 9 provides a 6 dB gain adjustment range. This feature is necessary for RGB applications where independent gain adjustment of each channel is required. The brightness or black level clamping requires a ‘‘sample and hold’’ circuit which holds the DC bias of the video amplifier constant during the black level reference portion of the video waveform. Black level clamping, often referred to as DC restoration, is accomplished by applying a back porch clamp signal to the clamp gate input pin (pin 14). The clamp comparator is enabled when the clamp signal goes low during the black level reference period (see Figure 2 ). When the clamp comparator is enabled, the clamp capacitor connected to pin 12 is either charged or discharged until the voltage at the minus input of the comparator matches the voltage set at the plus input of the comparator. During the video portion of the signal, the clamp comparator is disabled and the clamp capacitor holds the proper DC bias. In a DC coupled cathode drive application, picture brightness function can be achieved by varying the voltage at the comparator’s plus input. Note that the back porch clamp pulse width (tW in Figure 2 ) must be greater than 100 ns for proper operation. OSD blanking is activated through an active high TTL signal at pin 20. When pin 20 has a high logic level the video output at pin 17 drops to k 100 mV. During this time an external signal can be applied to the output, driving the video level to the desired level for the OSD window. This OSD signal will back bias the emitter of the internal output transistor, Q23 (see Figure 4 ). The maximum voltage to this transistor under this condition is 5V. This signal must also supply enough current to the pull-down transistor, Q24, which is about 100 mA. The OSD blanking can only be done during the active video period. If activated during the clamp pulse period, the OSD blanking will interfere with the DC restoration. VIDEO AMPLIFIER SECTION (Input Stage) A simplified schematic of LM1212’s video amplifier input stage is shown in Figure 3 . The 5.4V zener diode, Q1, Q6 and R2 bias the base of Q7 at 2.6V. The AC coupled video signal applied to pin 6 is referenced to the 2.6V bias voltage. TL/H/12354 – 8 FIGURE 2. Block Diagram of the LM1212 Video Amplifier with Contrast and Brightness (Black Level) Control 5 http://www.national.com Circuit Description (Continued) a control voltage at pin 3 which drives the base of Q9. By varying the voltage at the base of Q9, Q8’s collector current (IC8) is diverted away from the load resistors R10 and R11, thereby providing signal attenuation. Maximum attenuation is achieved when all of IC8 flows through Q9 and no current flows through the load resistors. The differential pair Q11 and Q12 provide drive control. Q12’s base is internally biased at 7.3V. Adjusting the voltage at the drive control input (pin 9) produces a control voltage at the base of Q11. With Q9 off and Q12 off, all of IC8 flows through R10, thus providing a gain of AV1 e b (R10/R9) c VIN e b 1. Drive control thus provides a 6 dB attenuation range. Transistor Q7 buffers the video signal, VIN, and Q8 converts the voltage to current. The AC collector current through Q8 is IC8 e VIN/R9. Under maximum gain condition, transistors Q9 and Q11 are off and all of IC8 flows through the load resistors R10 and R11. The maximum signal gain at the base of Q13 is, AV1 e b(R10 a R11)/R9 e b2. Signal attenuation is achieved by varying the base drive to the differential pairs Q9, Q10 and Q11, Q12 thereby unbalancing the collector currents through the transistor pairs. Base of Q10 is biased at 5.3V by its connection to the emitter of Q41 (see Figure 5 ). Pin 2 is connected to pin 3 through a 10X resistor. Adjusting the contrast voltage at pin 8 produces TL/H/12354 – 9 FIGURE 3. Simplified Schematic of the LM1212 Video Amplifier Input Stage http://www.national.com 6 Circuit Description (Continued) and level shift the contrast voltage to the base of Q36. The voltage at the emitter of Q36 equals the contrast voltage (Vcont) and the current through Q36’s collector is given by IC36 e Vcont/R28. Transistor Q36’s collector current is used to unbalance the current through the differential pair comprised of Q38 and Q40. Q40’s base is internally biased at 5.3V. The 5.3V reference is also connected to pin 1 and to the base of Q10 (see Figure 3 ). The base of Q38 (pin 3) is externally connected to pin 2 through a 10X resistor (see Figures 2 and 3 ). With Vcont e 2V, the differential pair (Q38, Q40) is balanced and the voltage at pins 1 and 2 is 5.3V. Under this condition, Q8’s collector current is equally split between Q9 and Q10 (see Figure 3 ) and the amplifier’s gain is half the maximum gain. If contrast voltage at pin 8 is greater than 2V then Q36’s collector current increases, thus pulling Q38’s collector node lower and consequently moving Q38’s base below 5.3V. With pin 2 at a lower voltage than pin 1, current through Q10 (see Figure 3 ) increases and the amplifier’s gain increases. With Vcont e 4V, the amplifier’s gain is maximum. If the contrast voltage at pin 8 is less than 2V then Q36’s collector current decreases and Q38’s base is pulled above 5.3V. With pin 2 voltage greater than pin 1 voltage, less current flows through Q10 (see Figure 3 ), consequently the amplifier’s gain decreases. With Vcont e 0V, the amplifier’s gain is minimum (i.e., maximum attenuation). VIDEO AMPLIFIER SECTION (Output Stage) A simplified schematic of LM1212’s video amplifier output stage is shown in Figure 4 . The output stage is the second gain stage. Ideally the gain of the second gain stage would be AV2 e bR21/R18 e b16. Because of the output stage’s low open loop gain, the gain is approximately AV2 e b10. Thus the maximum gain of the video amplifier is AV e AV1 c AV2 e 20. Transistors Q23 and Q24 provide a push-pull drive to the load. The output voltage can swing from 0.2V to 10V. Q82 is the OSD blanking transistor. Its base is connected to pin 20 via R34. A high TTL signal at pin 20 turns on Q82. This forces a current flow-through R20 and R31. These two resistors form a voltage divider from the emitter of Q82. If the input at pin 20 ia a minimum TTL high of 2.0V, then the juction of R20 and R31 will have a voltage of 0.6V. This voltage is applied to the bases of Q22 and Q24. 0.6V is just enough voltage to drive transistors Q22 and Q24 into saturation, forcing the output voltage at pin 17 to drop below 100 mV. The OSD video signal is applied during this period. The emitter-base junction of Q82 can withstand a maximum reverse bias voltage of 5V, thus pin 17 must not be driven above 5V during OSD blanking. CONTRAST CONTROL SECTION A simplified schematic of LM1212’s contrast control section is shown in Figure 5 . A 0V to 4V DC voltage is applied at the contrast input (pin 8). Transistors Q29, Q30 and Q34 buffer TL/H/12354 – 10 FIGURE 4. Simplified Schematic of LM1212 Video Amplifier Output Stage 7 http://www.national.com FIGURE 5. Simplified Schematic of LM1212 Contrast Control TL/H/12354 – 11 Circuit Description (Continued) http://www.national.com 8 Circuit Description (Continued) CLAMP GATE AND CLAMP COMPARATOR SECTION Figures 7 and 8 show simplified schematics of the clamp gate and clamp comparator circuits. The clamp gate circuit (Figure 7) consists of a PNP input buffer transistor (Q82), a PNP emitter coupled pair (Q85 and Q86) referenced on one side to 2.1V and an output switch transistor Q89. When the clamp gate input at pin 14 is high (l 1.5V) the Q89 switch is on and shunts the 200 mA current from current source Q90 to ground. When pin 14 is low (k 1.3V) the Q89 switch is off and the 200 mA current is mirrored by the current mirror comprised of Q91 and Q75 (see Figure 8 ). Consequently the clamp comparator comprised of the differential pair Q74 and Q77 is enabled. The input of the clamp comparator is similar to the clamp gate except that an NPN emitter coupled pair is used to control the current that will charge or discharge the clamp capacitor externally connected from pin 12 to ground. PNP transistors are used at the inputs because they offer a number of advantages over NPNs. PNPs will operate with base voltages at or near ground and will usually have a greater emitter base breakdown voltage (BVebo). Because the differential input voltage to the clamp comparator during the video scan period could be greater than the BVebo of NPN transistors, a resistor (R63) with a value one half that of R60 or R68 is connected between the bases of Q71 and Q79. The clamp comparator’s common mode range is from ground to approximately 9V and the maximum differential input voltage is VCC. DRIVE CONTROL SECTION A simplified schematic of the LM1212’s drive control section is shown in Figure 6 . A 0V to 4V DC voltage is applied at the drive control input (pin 9). Transistors Q49, Q50 and Q54 buffer and level shift the contrast voltage to the base of Q56. The voltage at the emitter of Q56 equals the drive voltage, Vdrive and the current through Q56’s collector is given by IC56 e Vdrive/R43. Transistor Q56’s collector current is used to unbalance the current through the differential pair comprised of Q58 and Q60. Q60’s base is internally biased at 7.1V and connected to the base of Q12 (see Figure 3 ). Q58’s base is internally connected to the base of Q11 (see Figure 3 ). With Vcont e 2V, the differential pair (Q58, Q60) is balanced and the voltage at the bases of Q11 and Q12 is 7.1V. Under this condition, Q10’s collector current is equally split between Q11 and Q12 (see Figure 3 ). If the drive voltage at pin 9 is greater than 2V then Q56’s collector current increases, thus pulling Q58’s collector node lower and consequently moving Q58’s base below 7.1V. With base of Q11 below 7.1V, current through Q12 (see Figure 3 ) increases and the amplifier’s gain increases. With Vdrive e 4V, the amplifier’s gain is maximum under maximum contrast condition (i.e., Vcont e 4V). If the drive voltage at pin 8 is less than 2V then Q56’s collector current decreases and Q58’s base is pulled above 7.1V. With base of Q11 greater than 7.1V, less current flows through Q12 (see Figure 3 ), consequently the amplifier’s gain decreases. With Vdrive e 0V, the amplifier’s gain is 6 dB less than the maximum gain. 9 http://www.national.com FIGURE 6. Simplified Schematic of the LM1212 Drive Control TL/H/12354 – 12 Circuit Description (Continued) http://www.national.com 10 Circuit Description (Continued) TL/H/12354 – 13 FIGURE 7. Simplified Schematic of the LM1212 Clamp Gate Circuit 11 http://www.national.com Circuit Description (Continued) TL/H/12354 – 14 FIGURE 8. Simplified Schematic of the LM1212 Clamp Comparator Circuit http://www.national.com 12 Applications of the LM1212 RGB VIDEO PREAMPLIFIER Figure 10 shows an RGB video preamplifier circuit using three LM1212s. Note that pin 2 of IC1 is connected to pin 2 of IC2 and IC3 respectively. This allows IC1 to provide a master contrast control and optimum contrast tracking. Connecting pin 1 of all 3 ICs together provides the reference voltage for the contrast control. Adjusting the contrast voltage at pin 8 of IC1 will vary the gain of all three video channels. Drive control input (pin 9) of each LM1212 allows individual gain adjustment for achieving white balance. The black level of each video channel can be individually adjusted to the desired voltage by adjusting the voltage at pin 19. In a DC-coupled cathode drive application, adjusting the voltage at pin 19 of each IC will provide cutoff adjustment. In an AC-coupled cathode drive application, the video signal is AC coupled and DC restored at the cathode. In such an application, the video signal’s black level may be clamped to the desired level by simply biasing pin 19 to the black level voltage by using a voltage divider at pin 19. SINGLE VIDEO CHANNEL A typical application for a single video channel is shown in Figure 9 . The video signal is AC coupled to pin 6. The LM1212 internally biases the video signal to 2.6 VDC. Contrast control is achieved by applying a 0V to 4V DC voltage at pin 8. The amplifier’s gain is minimum (i.e., maximum signal attenuation) if pin 8 is at 0V and is maximum if pin 8 is at 4V. With pin 9 (drive control) at 0V, the amplifier has a maximum gain of 10. For DC restoration, a clamp signal must be applied to the clamp gate input (pin 14). The clamp signal should be logic low (less than 0.8V) only during the back porch (black level reference period) interval (see Figure 2 ). The clamp gate input is TTL compatible. Brightness control is provided by applying a 0V to 4V DC voltage at pin 19. For example, if pin 19 is biased at 1V then the video signal’s black level will be clamped at 1V. A 510X load resistor is connected from the video output pin (pin 17) to ground. This resistor biases the output stage of the amplifier. For power dissipation considerations, the load resistor should not be much less than 510X. 13 http://www.national.com Applications of the LM1212 (Continued) TL/H/12354 – 15 FIGURE 9. Typical LM1212 Application (Single Video Channel) http://www.national.com 14 Applications of the LM1212 (Continued) TL/H/12354 – 16 * Note: All video inputs must have a series 30X resistor for protection against EOS (Electrical Over Stress). FIGURE 10. LM1212 Video Preamp Demonstration Board Schematic 15 http://www.national.com Applications of the LM1212 (Continued) TL/H/12354 – 17 FIGURE 10. LM1212 Video Preamp Demonstration Board Schematic (Continued) Power Down Characteristics PC Board Layout Considerations The LM1212 includes a built-in power down spot killer to prevent a flash on the screen upon power down. The LM1212’s output voltage decreases as the device is being powered down, thus preventing a flash on the screen. In some preamplifiers, the video output signal may go high as the device is being powered down. This may cause a whiterthan-white level at the output of the CRT driver, thus causing a flash on the screen. For optimum performance and stable operation, a doublesided printed circuit board with adequate ground plane and power supply decoupling as close to the VCC pins as possible is recommended. For suggestions on optimum PC board layout, please see the reference section below. http://www.national.com Reference Ott, Henry W, Noise Reduction Techniques in Electronic Systems , John Wiley & Sons, New York, 1976. 16 17 http://www.national.com LM1212 230 MHz Video Amplifier System with OSD Blanking Physical Dimensions inches (millimeters) unless otherwise noted Order Number LM1212N NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: a49 (0) 180-530 85 86 Email: europe.support @ nsc.com Deutsch Tel: a49 (0) 180-530 85 85 English Tel: a49 (0) 180-532 78 32 Fran3ais Tel: a49 (0) 180-532 93 58 Italiano Tel: a49 (0) 180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2308 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.