LMS75LBC176 Differential Bus Transceivers General Description Features The LMS75LBC176 is a differential bus/line transceiver designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines. It meets TIA/EIA RS485 and ISO 8482:1987(E). The LMS75LBC176 combines a TRI-STATE™ differential line driver and differential input receiver, both of which operate from a single 5.0V power supply. The driver and receiver have an active high and active low enable, respectively, that can be externally connected to function as a direction control. The driver and receiver differential inputs are internally connected to form differential input/output (I/O) bus ports that are designed to offer minimum loading to bus whenever the driver is disabled or when VCC = 0V. These ports feature wide positive and negative common mode voltage ranges, making the device suitable for multipoint applications in noisy environments. The LMS75LBC176 is available in a 8-Pin SOIC package. It is a drop-in socket replacement to TI’s SN75LBC176. n n n n n n n n n n n n n n Bidirectional transceiver Meet ANSI standard RS-485 Low skew, 6ns Low supply current, 8mA (max) Wide input and output voltage range High output drive capacity ± 60mA Thermal shutdown protection Open circuit fail-safe for receiver Receiver input sensitivity ± 200mV Receiver input hysteresis 10mV (min.) Single supply voltage operation, 5V Glitch free power-up and power-down operation Pin and functional compatible with TI’s SN75LBC176 8-Pin SOIC Applications n n n n n Network hubs, bridges, and routers Point of sales equipment (ATM, barcode readers,…) Industrial programmable logic controllers High speed parallel and serial applications Multipoint applications with noisy environment Typical Application 20047901 A typical multipoint application is shown in the above figure. Terminating resistors, RT, are typically required but only located at the two ends of the cable. Pull up and pull down resistors maybe required at the end of the bus to provide failsafe biasing. The biasing resistors provide a bias to the cable when all drivers are in TRI-STATE, See National Application Note, AN-847 for further information. © 2003 National Semiconductor Corporation DS200479 www.national.com LMS75LBC176 Differential Bus Transceivers April 2003 LMS75LBC176 Connection Diagram 8-Pin SOIC 20047902 Top View Ordering Information Package 8-Pin SOIC Part Number LMS75LBC176M LMS75LBC176MX Package Marking LMS75LBC176 Transport Media Rail 2.5k Units Tape and Reel NSC Drawing M08A Truth Table DRIVER SECTION RE DE DI A X H H H L X H L L H X L X Z Z B RECEIVER SECTION RE DE A-B RO L L ≥ +0.2V H L L ≤ −0.2V L H X X Z L L OPEN * H Note: * = Non Terminated, Open Input only X = Irrelevent Z = TRI-STATE H = High level L = Low level www.national.com 2 Operating Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VCC (Note 2) Min Nom Max Supply Voltage, VCC −0.3V to VCC + 0.3V Package Thermal Impedance, θJA 125C/W Junction Temperature (Note 3) High-Level Input Voltage, VIH (Note 5) 150˚C Operating Free-Air Temperature Range, TA 0˚C to 70˚C Storage Temperature Range 12 −7 −65˚C to 150˚C 2 V Low-Level Input Voltage, VIL (Note 5) 0.8 V Differential Input Voltage, VID (Note 6) ± 12 V High-Level Output Soldering Information Driver, IOH Infrared or Convection (20 sec.) 235˚C ESD Rating (Note 4) V V VIN or VIC −7V to 12V Input Voltage, VIN (DI, DE, or RE) 5.0 5.25 Voltage at any Bus Terminal (Separately or Common Mode) 7V Voltage Range at Any Bus Terminal 4.75 −60 mA Receiver, IOH 2KV −400 µA Low-Level Output Driver, IOL 60 mA Receiver, IOL 8 mA Electrical Characteristics VCC = 5V, TA = 0˚C to 70˚C Symbol Parameter Conditions Min Typ Max Units −1.5 V 6 V Driver Section VCL Input Clamp Voltage II = −18mA VO Output Voltage IO = 0 | VOD1 | Differential Output Voltage IO = 0 1.5 6 V | VOD2 | Differential Output Voltage RL = 54Ω 1.5 5 V 1.5 5 V ± 0.2 V VOD3 Differential Output Voltage VTEST = −7V to 12V ∆VOD Change in Magnitude of Differential Output Voltage (Note 8) RL = 54Ω or 100Ω VOC Common-Mode Output Voltage RL = 54Ω or 100Ω ∆VOC Change in Magnitude of Differential Output Voltage (Note 8) RL = 54Ω or 100Ω IO Output Current Output Disabled (Note 8) 0 3 −1 ± 0.2 VO = 12V 1 VO = −7V −0.8 V V mA IIH High-Level Input Current VIN = 2.4V −100 µA IIL Low-Level Input Current VIN = 0.4V −100 µA IOSD Short-Circuit Output Current VO = −7V −250 VO = 0 −150 VO = VCC 250 VO = 12V ICC Supply Current mA 250 VIN = 0 or VCC, No Load 3 Receiver Disabled and Driver Enabled 8 Receiver and Driver Disabled 8 mA www.national.com LMS75LBC176 Absolute Maximum Ratings LMS75LBC176 Electrical Characteristics (Continued) VCC = 5V, TA = 0˚C to 70˚C Symbol Parameter Conditions Min Typ Max Units 25 ns Switching Characteristics td (OD) Differential Output Delay Time tt (OD) Differential Output Transition RL = 54Ω, CL = 50pF Time 8 tsk(p) Pulse Skew, (|td(ODH) - td(ODL)|) RL = 54Ω, CL = 50pF 0 tPZH Output Enable Time to High Level tPZL RL = 54Ω , CL = 50pF 3 ns 6 ns RL = 110Ω, CL = 50pF 35 ns Output Enable Time to Low Level RL = 110Ω, CL = 50pF 35 ns tPHZ Output Disable Time from High Level RL = 110Ω, CL = 50pF 60 ns tPLZ Output Disable Time from Low Level RL = 110Ω, CL = 50pF 35 ns 0.2 V Receiver Section VTH+ Positive-Going Input Threshold Voltage VO = 2.7V, IO = −0.4mA VTH− Negative-Going Input Threshold Voltage VO = 0.5V, IO = 8mA ∆VTH Hysteresis Voltage (VTH+ - VTH−) VCL Enable-Input Clamp Voltage II = −18mA −0.2 V 10 mV −1.5 V VOH High-Level Output Voltage VID = 200mV, IOH = −400µA VOL Low-Level Output Voltage VID = −200mV, IOL = 8mA 0.45 V IOZ High-Impedance-State Output Current VO = 0.4V to 2.4V ± 20 µA IIN Line Input Current Other Input = 0V, See (Note 8) 2.7 V VIN = 12V 1 VIN = −7V −0.8 mA IIH High-Level Enable-Input Current VIH = 2.7V −100 µA IIL Low-Level Enable-Input Current VIL = 0.4V −100 µA RIN Input Resistance ICC Supply Current 12 VIN = 0 or VCC, No Load kΩ Receiver Enabled and Driver Disabled 8 Receiver and Driver Disabled 8 mA Switching Characteristics TPLH Propagation Delay Time, Low-to High-Level Single-Ended Output VID = −1.5V to 1.5V 8 33 ns TPHL Propagation Delay Time, High-to Low-Level Single-Ended Output VID = −1.5V to 1.5V 8 33 ns tsk(p) Pulse Skew (|tPLH - tPHL|) VID = −1.5V to 1.5V www.national.com 2 4 ns (Continued) VCC = 5V, TA = 0˚C to 70˚C Max Units tPZH Symbol Output Enable Time to High Level Parameter Conditions Min Typ 35 ns tPZL Output Enable Time to Low Level 30 ns tPHZ Output Disable Time from High Level 35 ns tPLZ Output Disable Time from Low Level 30 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Note 2: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 4: ESD rating based upon human body model, 100pF discharged through 1.5kΩ. Note 5: Voltage limits apply to DI, DE, RE pins. Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B Note 7: ∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC , respectively when the input changes from high to low levels. Note 8: Applies to both power on and off (ANSI Standard RS-485 conditions)|. 5 www.national.com LMS75LBC176 Electrical Characteristics LMS75LBC176 Parameter Measuring Information 20047903 FIGURE 1. Test Circuit for VOD2 and VOC 20047904 FIGURE 2. Test Circuit for VOD2 20047905 FIGURE 3. Test Circuit for Driver Differential Output Delay and Transition Times 20047906 FIGURE 4. Test Circuit for Driver TPZH and TPHZ www.national.com 6 LMS75LBC176 Parameter Measuring Information (Continued) 20047907 FIGURE 5. Test Circuit for Driver TPZL and TPLZ 20047908 FIGURE 6. Test Circuit for Receiver VOH and VOL 20047909 FIGURE 7. Test Circuit for Receiver TPLH and TPHL 7 www.national.com LMS75LBC176 Parameter Measuring Information (Continued) Test Circuit 20047910 Voltage Waveforms 20047911 FIGURE 8. Test Circuit for Receiver TPZH/ TPZL and TPHZ/TPLZ www.national.com 8 POWER LINE NOISE FILTERING A factor to consider in designing power and ground is noise filtering. A noise filtering circuit is designed to prevent noise generated by the integrated circuit (IC) as well as noise entering the IC from other devices. A common filtering method is to place by-pass capacitors (Cbp) between the power and ground lines. Placing a by-pass capacitor (Cbp) with the correct value at the proper location solves many power supply noise problems. Choosing the correct capacitor value is based upon the desired noise filtering range. Since capacitors are not 20047912 FIGURE 9. Placement of by-pass Capacitors, Cbp 9 www.national.com LMS75LBC176 ideal, they may act more like inductors or resistors over a specific frequency range. Thus, many times two by-pass capacitors may be used to filter a wider bandwidth of noise. It is highly recommended to place a larger capacitor, such as 10µF, between power supply pin and ground to filter out low frequencies and a 0.1µF to filter out higher frequencies. By-pass capacitors must be mounted as close as possible to the IC to be effective. Long leads produce higher impedance at higher frequencies due to stray inductance. Thus, this will reduce the by-pass capacitor’s effectiveness. Surface mounting chip capacitors are the best solution because they have lower inductance. Application Information LMS75LBC176 Differential Bus Transceivers Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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