LT1999-10/LT1999-20/ LT1999-50 High Voltage, Bidirectional Current Sense Amplifier Features Description Buffered Output with 3 Gain Options: 10V/V, 20V/V, 50V/V n Gain Accuracy: 0.5% Max n Input Common Mode Voltage Range: –5V to 80V n AC CMRR > 80dB at 100kHz n Input Offset Voltage: 1.5mV Max n –3dB Bandwidth: 2MHz n Smooth, Continuous Operation Over Entire Common Mode Range n 4kV HBM Tolerant and 1kV CDM Tolerant n Low Power Shutdown <10µA n –55°C to 150°C Operating Temperature Range n 8-Lead MSOP and 8-Lead SO (Narrow) Packages The LT®1999 is a high speed precision current sense amplifier, designed to monitor bidirectional currents over a wide common mode range. The LT1999 is offered in three gain options: 10V/V, 20V/V, and 50V/V. n The LT1999 senses current via an external resistive shunt and generates an output voltage, indicating both magnitude and direction of the sensed current. The output voltage is referenced halfway between the supply voltage and ground, or an external voltage can be used to set the reference level. With a 2MHz bandwidth and a common mode input range of –5V to 80V, the LT1999 is suitable for monitoring currents in H-Bridge motor controls, switching power supplies, solenoid currents, and battery charge currents from full charge to depletion. Applications n n n n n n The LT1999 operates from an independent 5V supply and draws 1.55mA. A shutdown mode is provided for minimizing power consumption. High Side or Low Side Current Sensing H-Bridge Motor Control Solenoid Current Sense High Voltage Data Acquisition PWM Control Loops Fuse/MOSFET Monitoring The LT1999 is available in an 8-lead MSOP or SOP package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application V+ 1 8 + V 0.8k V–IN VOUT VSHDN 2.5V RG – + 7 VOUT + V 3 5V 4 4k V+ 0.8k 160k 6 160k V+IN VREF 0.1µF 5 V+IN (20V/DIV) + – 4k V+IN 2 RS 2µA SHDN VOUT (2V/DIV) 5V Full Bridge Armature Current Monitor V+ LT1999 VS TIME (10µs/DIV) 1999 TA01b 0.1µF 1999 TA01a 1999fb 1 LT1999-10/LT1999-20/ LT1999-50 Absolute Maximum Ratings (Note 1) Differential Input Voltage +IN to –IN (Notes 1, 3).................................. ±60V, 10ms +IN to GND, –IN to GND (Note 2).............. –5.25V to 88V Total Supply Voltage (V+ to GND).................................6V Input Voltage Pins 6 and 8 .................... V+ + 0.3V, –0.3V Output Short-Circuit Duration (Note 4)............. Indefinite Operating Ambient Temperature (Note 5) LT1999C...............................................–40°C to 85°C LT1999I.................................................–40°C to 85°C LT1999H............................................. –40°C to 125°C LT1999MP.......................................... –55°C to 150°C Specified Temperature Range (Note 6) LT1999C................................................... 0°C to 70°C LT1999I.................................................–40°C to 85°C LT1999H............................................. –40°C to 125°C LT1999MP.......................................... –55°C to 150°C Junction Temperature............................................ 150°C Storage Temperature Range................... –65°C to 150°C Pin Configuration TOP VIEW TOP VIEW V+ +IN –IN V+ 1 2 3 4 8 7 6 5 V+ SHDN OUT REF GND MS8 PACKAGE 8-LEAD PLASTIC MSOP 1 8 SHDN +IN 2 7 OUT –IN 3 6 REF V+ 4 5 GND S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, ΘJA = 300°C/W TJMAX = 150°C, ΘJA = 190°C/W Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1999CMS8-10#PBF LT1999CMS8-10#TRPBF LTFPB 8-Lead Plastic MSOP 0°C to 70°C LT1999IMS8-10#PBF LT1999IMS8-10#TRPBF LTFPB 8-Lead Plastic MSOP –40°C to 85°C LT1999HMS8-10#PBF LT1999HMS8-10#TRPBF LTFPB 8-Lead Plastic MSOP –40°C to 125°C LT1999MPMS8-10#PBF LT1999MPMS8-10#TRPBF LTFQP 8-Lead Plastic MSOP –55°C to 150°C LT1999CS8-10#PBF LT1999CS8-10#TRPBF 199910 8-Lead Plastic SO 0°C to 70°C LT1999IS8-10#PBF LT1999IS8-10#TRPBF 199910 8-Lead Plastic SO –40°C to 85°C LT1999HS8-10#PBF LT1999HS8-10#TRPBF 199910 8-Lead Plastic SO –40°C to 125°C LT1999MPS8-10#PBF LT1999MPS8-10#TRPBF 99MP10 8-Lead Plastic SO –55°C to 150°C LT1999CMS8-20#PBF LT1999CMS8-20#TRPBF LTFNZ 8-Lead Plastic MSOP 0°C to 70°C LT1999IMS8-20#PBF LT1999IMS8-20#TRPBF LTFNZ 8-Lead Plastic MSOP –40°C to 85°C LT1999HMS8-20#PBF LT1999HMS8-20#TRPBF LTFNZ 8-Lead Plastic MSOP –40°C to 125°C LT1999MPMS8-20#PBF LT1999MPMS8-20#TRPBF LTFQQ 8-Lead Plastic MSOP –55°C to 150°C 1999fb 2 LT1999-10/LT1999-20/ LT1999-50 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1999CS8-20#PBF LT1999CS8-20#TRPBF 199920 8-Lead Plastic SO 0°C to 70°C LT1999IS8-20#PBF LT1999IS8-20#TRPBF 199920 8-Lead Plastic SO –40°C to 85°C LT1999HS8-20#PBF LT1999HS8-20#TRPBF 199920 8-Lead Plastic SO –40°C to 125°C LT1999MPS8-20#PBF LT1999MPS8-20#TRPBF 99MP20 8-Lead Plastic SO –55°C to 150°C LT1999CMS8-50#PBF LT1999CMS8-50#TRPBF LTFPC 8-Lead Plastic MSOP 0°C to 70°C LT1999IMS8-50#PBF LT1999IMS8-50#TRPBF LTFPC 8-Lead Plastic MSOP –40°C to 85°C LT1999HMS8-50#PBF LT1999HMS8-50#TRPBF LTFPC 8-Lead Plastic MSOP –40°C to 125°C LT1999MPMS8-50#PBF LT1999MPMS8-50#TRPBF LTFQR 8-Lead Plastic MSOP –55°C to 150°C LT1999CS8-50#PBF LT1999CS8-50#TRPBF 199950 8-Lead Plastic SO 0°C to 70°C LT1999IS8-50#PBF LT1999IS8-50#TRPBF 199950 8-Lead Plastic SO –40°C to 85°C LT1999HS8-50#PBF LT1999HS8-50#TRPBF 199950 8-Lead Plastic SO –40°C to 125°C LT1999MPS8-50#PBF LT1999MPS8-50#TRPBF 99MP50 8-Lead Plastic SO –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, 0°C < TA < 70°C for C-grade parts, –40°C < TA < 85°C for I-grade parts, and –40°C < TA < 125°C for H-grade parts, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, VCM = 12V, VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2. SYMBOL PARAMETER CONDITIONS VSENSE Full-Scale Input Sense Voltage (Note 7) VSENSE = V+IN – V–IN LT1999-10 LT1999-20 LT1999-50 VCM CM Input Voltage Range MIN MAX UNITS –0.35 –0.2 –0.08 0.35 0.2 0.08 V V V l –5 80 V l l l TYP RIN(DIFF) Differential Input Impedance ΔVINDIFF = ±2V/Gain l 6.4 8 RINCM CM Input Impedance ΔVCM = 5.5V to 80V ΔVCM = –5V to 4.5V l l 5 3.6 20 4.8 VOSI Input Referred Voltage Offset –750 –1500 ±500 l LT1999-10 LT1999-20 LT1999-50 l l l 9.95 19.9 48.75 10 20 50 ΔVOSI /ΔT Input Referred Voltage Offset Drift AV Gain 9.6 kΩ 6 MΩ kΩ 750 1500 μV μV 5 μV/°C 10.05 20.1 50.25 V/V V/V V/V AV Error Gain Error ΔVOUT = ±2V l –0.5 ±0.2 0.5 % IB Input Bias Current I(+IN) = I(–IN) (Note 8) VCM > 5.5V VCM = –5V VSHDN = 0.5V, 0V < VCM < 80V l l l 100 –2.35 137.5 –1.95 0.001 175 –1.5 2.5 μA mA μA IOS Input Offset Current IOS = I(+IN) – I(–IN) (Note 8) VCM > 5.5V VCM = –5V VSHDN = 0.5V, 0V < VCM < 80V l l l –1 –10 –2.5 1 10 2.5 μA μA μA PSRR Supply Rejection Ratio V+ = 4.5V to 5.5V l 68 77 dB 1999fb 3 LT1999-10/LT1999-20/ LT1999-50 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, 0°C < TA < 70°C for C-grade parts, –40°C < TA < 85°C for I-grade parts, and –40°C < TA < 125°C for H-grade parts, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, VCM = 12V, VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2. SYMBOL PARAMETER CONDITIONS CMRR Sense Input Common Mode Rejection VCM = –5V to 80V VCM = –5V to 5.5V VCM = 12V, 7VP-P, f = 100kHz, VCM = 0V, 7VP-P, f = 100kHz en Differential Input Referred Noise Voltage Density f = 10kHz f = 0.1Hz to 10Hz REFRR REF Pin Rejection, V+ = 5.5V ΔVREF = 3.0V ΔVREF = 3.25V ΔVREF = 3.25V l l l l MIN TYP MAX UNITS 96 96 75 80 105 120 90 100 dB dB dB dB 97 8 nV/√Hz μVP-P dB dB dB LT1999-10 LT1999-20 LT1999-50 l l l 62 62 62 70 70 70 VSHDN = 0.5V l l 60 0.15 80 0.4 100 0.65 kΩ MΩ VSHDN = 0.5V l l 2.45 1 2.5 2.5 2.55 2.75 V V l l l 1.25 1.125 1.125 V+ – 1.25 V+ – 1.125 V+ – 1.125 V V V RREF REF Pin Input Impedance VREF Open Circuit Voltage VREFR REF Pin Input Range (Note 9) LT1999-10 LT1999-20 LT1999-50 ISHDN Pin Pull-Up Current V+ = 5.5V, VSHDN = 0V l –6 V+ – 0.5 –2 μA VIH SHDN Pin Input High l VIL SHDN Pin Input Low l f3dB Small Signal Bandwidth SR Slew Rate ts Settling Time due to Input Step, ΔVOUT = ±2V 0.5% Settling 2.5 μs tr Common Mode Step Recovery Time ΔVCM = ±50V, 20ns (Note 10) LT1999-10 LT1999-20 LT1999-50 0.8 1 1.3 μs μs μs VS Supply Voltage (Note 11) IS Supply Current VCM > 5.5V VCM = –5V V+ = 5.5V, VSHDN = 0.5V, VCM > 0V RO Output Impedance ΔIO = ±2mA ISRC Sourcing Output Current RLOAD = 50Ω to GND ISNK Sinking Output Current VOUT LT1999-10 LT1999-20 LT1999-50 l V 0.5 4.5 l l l V 2 2 1.2 MHz MHz MHz 3 V/μs 5 5.5 V 1.55 5.8 3 1.9 7.1 10 mA mA μA 40 mA 0.15 31 Ω l 6 RLOAD = 50Ω to V+ l 15 26 40 mA Swing Output High (with Respect to V+) RLOAD = 1kΩ to Mid-Supply RLOAD = Open l l 125 5 250 125 mV mV Swing Output Low (with Respect to V–) RLOAD = 1kΩ to Mid-Supply RLOAD = Open l l 250 150 400 225 mV mV tON Turn-On Time VSHDN = 0V to 5V 1 μs tOFF Turn-Off Time VSHDN = 5V to 0V 1 μs 1999fb 4 LT1999-10/LT1999-20/ LT1999-50 Electrical Characteristics The l denotes the specifications which apply over the full operating + temperature range, –55°C < TA < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C. V = 5V, GND = 0V, VCM = 12V, VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2. SYMBOL PARAMETER CONDITIONS VSENSE Full-Scale Input Sense Voltage (Note 7) VSENSE = V+IN – V–IN LT1999-10 LT1999-20 LT1999-50 VCM CM Input Voltage Range MAX UNITS l l l –0.35 –0.2 –0.08 MIN TYP 0.35 0.2 0.08 V V V l –5 80 V RIN(DIFF) Differential Input Impedance ΔVINDIFF = ±2V/GAIN l 6.4 8 RINCM CM Input Impedance ΔVCM = 5.5V to 80V ΔVCM = –5V to 4.5V l l 5 3.6 20 4.8 VOSI Input Referred Voltage Offset ±500 l –750 –2000 9.6 kΩ 6 MΩ kΩ 750 2000 μV μV ΔVOSI /ΔT Input Referred Voltage Offset Drift 8 AV Gain LT1999-10 LT1999-20 LT1999-50 l l l 9.95 19.9 48.75 AV Error Gain Error ΔVOUT = ±2V l –0.5 ±0.2 0.5 % IB Input Bias Current I(+IN) = I(–IN) (Note 8) VCM > 5.5V VCM = –5V VSHDN = 0.5V, 0V < VCM < 80V l l l 100 –2.35 137.5 –1.95 0.001 180 –1.5 10 μA mA μA IOS Input Offset Current IOS = I(+IN) – I(–IN) (Note 8) VCM > 5.5V VCM = –5V VSHDN = 0.5V, 0V < VCM < 80V l l l –1 –10 –10 1 10 10 μA μA μA PSRR Supply Rejection Ratio V+ = 4.5V to 5.5V l 68 77 dB CMRR Sense Input Common Mode Rejection VCM = –5V to 80V VCM = –5V to 5.5V VCM = 12V, 7VP-P, f = 100kHz, VCM = 0V, 7VP-P, f = 100kHz l l l l 96 96 75 80 105 120 90 100 dB dB dB dB en Differential Input Referred Noise Voltage Density f= 10kHz f = 0.1Hz to 10Hz 97 8 nV/√Hz μVP-P REFRR REF Pin Rejection, V+ = 5.5V ΔVREF = 2.75V ΔVREF = 3.25V ΔVREF = 3.25V dB dB dB 10 20 50 μV/°C 10.05 20.1 50.25 V/V V/V V/V LT1999-10 LT1999-20 LT1999-50 l l l 62 62 62 70 70 70 VSHDN = 0.5V l l 60 0.15 80 0.4 100 0.65 kΩ MΩ VSHDN = 0.5V l l 2.45 0.25 2.5 2.5 2.55 2.75 V V 1.5 1.125 1.125 V+ – 1.25 V+ – 1.125 V+ – 1.125 V V V RREF REF Pin Input Impedance VREF Open Circuit Voltage VREFR REF Pin Input Range (Note 9) LT1999-10 LT1999-20 LT1999-50 l l l ISHDN Pin Pull-Up Current V+ = 5.5V, VSHDN = 0V l –6 V+ – 0.5 VIH SHDN Pin Input High l VIL SHDN Pin Input Low l f3dB Small Signal Bandwidth SR Slew Rate tS Settling Time Due to Input Step, ΔVOUT = ±2V –2 μA V 0.5 V LT1999-10 LT1999-20 LT1999-50 2 2 1.2 MHz MHz MHz 3 V/μs 0.5% Settling 2.5 μs 1999fb 5 LT1999-10/LT1999-20/ LT1999-50 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, –55°C < TA < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C. V+ = 5V, GND = 0V, VCM = 12V, VREF = floating, VSHDN = floating, unless otherwise specified. See Figure 2. SYMBOL PARAMETER CONDITIONS MIN tr Common Mode Step Recovery Time ΔVCM = ±50V, 20ns (Note 10) LT1999-10 LT1999-20 LT1999-50 VS Supply Voltage (Note 11) IS Supply Current VCM > 5.5V VCM = –5V V+ = 5.5V, VSHDN = 0.5V, VCM > 0V TYP MAX 0.8 1 1.3 l 4.5 l l l UNITS μs μs μs 5 5.5 V 1.55 5.8 3 1.9 7.1 25 mA mA μA 40 mA RO Output Impedance ΔIO = ±2mA ISRC Sourcing Output Current RLOAD = 50Ω to GND l 3 ISNK Sinking Output Current RLOAD = 50Ω to V+ l 10 26 40 mA VOUT Swing Output High (with Respect to V+) RLOAD = 1kΩ to Mid-Supply RLOAD = Open l l 125 5 250 125 mV mV Swing Output Low (with Respect to V –) RLOAD = 1kΩ to Mid-Supply RLOAD = Open l l 250 150 400 225 mV mV tON Turn-On Time VSHDN = 0V to 5V 1 μs tOFF Turn-Off Time VSHDN = 5V to 0V 1 μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Pin 2 (+IN) and Pin 3 (–IN) are protected by ESD voltage clamps which have asymmetric bidirectional breakdown characteristics with respect to the GND pin (Pin 5). These pins can safely support common mode voltages which vary from –5.25V to 88V without triggering an ESD clamp. Note 3: Exposure to differential sense voltages exceeding the normal operating range for extended periods of time may degrade part performance. A heat sink may be required to keep the junction temperature below the Absolute Maximum Rating when the inputs are stressed differentially. The amount of power dissipated in the LT1999 due to input overdrive can be approximated by: PDISS = ( V+IN − V−IN )2 8kΩ Note 4: A heat sink may be required to keep the junction temperature below the absolute maximum rating. Note 5: The LT1999C/LT1999I are guaranteed functional over the operating temperature range –40°C to 85°C. The LT1999H is guaranteed functional over the operating temperature range –40°C to 125°C. The LT1999MP is guaranteed functional over the operating temperature range –55°C to 150°C. Junction temperatures greater than 125°C will promote accelerated aging. The LT1999 has a demonstrated typical life beyond 1000 hours at 150°C. Note 6: The LT1999C is guaranteed to meet specified performance from 0°C to 70°C. The LT1999C is designed, characterized, and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1999I is guaranteed to meet specified performance from –40°C to 85°C. The LT1999H is guaranteed to meet specified performance from –40°C to 125°C. The LT1999MP is guaranteed to meet specified performance from –55°C to 150°C. 0.15 31 Ω Note 7: Full-scale sense (VSENSE) gives indication of the maximum differential input that can be applied with better than 0.5% gain accuracy. Gain accuracy is degraded when the output saturates against either power supply rail. VSENSE is verified with V+ = 5.5V, VCM = 12V, with the REF pin set to it’s voltage range limits. The maximum VSENSE is verified with the REF pin set to it’s minimum specified limit, verifying the gain error is less than 0.5% at the output. The minimum VSENSE is verified with the REF pin set to its maximum specified limit, verifying the gain error at the output is less than 0.5%. See Note 9 for more information. Note 8: IB is defined as the average of the input bias currents to the +IN and –IN pins (Pins 2 and 3). A positive current indicates current flowing into the pin. IOS is defined as the difference of the input bias currents. IOS = I(+IN) – I(–IN) Note 9: The REF pin voltage range is the minimum and maximum limits that ensures the input referred voltage offset does not exceed ±3mV over the I, C, and H temperature ranges, and ±3.5mV over the MP temperature range. Note 10: Common mode recovery time is defined as the time it takes the output of the LT1999 to recover from a 50V, 20ns input common mode voltage transition, and settle to within the DC amplifier specifications. Note 11: Operating the LT1999 with V+ < 4.5V is possible, although the LT1999 is not tested or specified in this condition. See the Applications Information section. 1999fb 6 LT1999-10/LT1999-20/ LT1999-50 Typical Performance Characteristics Supply Current vs Input Common Mode 7 Supply Current vs Temperature 1.8 V+ = 5V 6 VSHDN = OPEN VINDIFF = 0V VCM = 12V 150°C 130°C 90°C 25°C –45°C –55°C 3.5 1.7 5 3.0 3 2 IS (mA) 2.5 4 IS (mA) IS (mA) Supply Current vs Supply Voltage 4.0 1.6 V+ = 5.5V 1.5 VCM = 12V 2.0 1.5 V+ = 4.5V 1.0 1 0.5 0 –5 5 15 25 35 45 VCM (V) 55 65 1.4 –55 –30 75 80 20 45 70 95 TEMPERATURE (°C) 0 120 145 0 2 3 SUPPLY VOLTAGE (V) 1 10 V+ = 5V VCM = 12V 8 1 Shutdown Input Bias Current vs Input Common Mode 1000 VSHDN = 0V VINDIFF = 0V VCM = 12V V+ = 5V VSHDN = 0V VSENSE = 0V TA = 150°C TA =130°C 6 V+ = 5.5V 4 TA =110°C IB (nA) IS (µA) IS (mA) 100 TA = 150°C TA = 90°C 10 0.01 0.001 TA = 25°C 0 1 TA = 70°C TA = –55°C 3 2 VSHDN (V) 4 0 –55 –30 5 –5 20 45 70 95 TEMPERATURE (°C) 1999 G04 146 V+ = 5V IMPEDANCE (kΩ) IB (µA) IB (mA) VCM = 80V 140 138 VCM = 5.5V 136 –1.5 5 15 25 35 45 VCM (V) 55 65 75 80 1999 G07 132 –55 –30 –5 100 80 1999 G06 1000 100 DIFFERENTIAL INPUT IMPEDANCE 10 134 –5 60 40 VCM (V) COMMON MODE INPUT IMPEDANCE 10000 142 –1.0 20 100000 VSHDN = OPEN VINDIFF = 0V 144 V+ = 5V –0.5 0 Input Impedance vs Input Common Mode Voltage Input Bias Current vs Temperature 0 –2.0 1 120 145 1999 G05 Input Bias Current vs Input Common Mode 0.5 V+ = 4.5V 2 5 1999 G03 Shutdown Supply Current vs Temperature 0.1 4 1999 G02 1999 G01 Supply Current vs SHDN Pin Voltage 10 –5 20 45 70 95 TEMPERATURE (°C) 120 145 1999 G08 1 –5 5 15 25 35 45 VCM (V) 55 65 75 1999 G09 1999fb 7 LT1999-10/LT1999-20/ LT1999-50 Typical Performance Characteristics Input Referred Voltage Offset vs Temperature and Gain Option 1500 Input Referred Voltage Offset vs Input Common Mode Voltage 1500 VCM = 12V 12 UNITS PLOTTED 1000 1000 500 VOSI (µV) 500 VOSI (µV) V+ = 5V TA = 25°C 12 UNITS PLOTTED 0 0 –500 –500 –1000 –1500 –55 –30 –5 LT1999-10 LT1999-20 LT1999-50 –1000 LT1999-10 LT1999-20 LT1999-50 20 45 70 95 TEMPERATURE (°C) –1500 120 145 –5 5 15 25 1999 G10 25 GAIN GAIN (dB) 135 30 90 25 45 20 0 VOUT = 0.5VP-P AT 1kHz 10 100 1000 FREQUENCY (kHz) 135 GAIN 90 45 PHASE 15 0 –90 5 –90 –135 0 0 –5 180 –45 –45 1 1999 G11 10 5 –10 –5 –180 10000 –135 VOUT = 0.5VP-P AT 1kHz 1 10 LT1999-50 Small Signal Frequency Response 1999 G13 135 90 45 PHASE 20 0 15 –45 10 –90 5 GAIN ERROR (%) 25 VOUT = 0.5VP-P AT 1kHz 10 100 1000 FREQUENCY (kHz) –180 10000 1999 G14 0 –0.25 –0.25 –0.50 –55 –30 V+ = 5V TA = 25°C 12 UNITS PLOTTED 0.25 0 –135 1 0.50 VCM = 12V 12 UNITS PLOTTED 0.25 PHASE (DEG) GAIN (dB) 30 0 0.50 GAIN ERROR (%) GAIN 35 Gain Error vs Input Common Mode Voltage Gain Error vs Temperature 180 –180 10000 100 1000 FREQUENCY (kHz) 1999 G12 40 75 PHASE (DEG) PHASE 35 PHASE (DEG) 15 180 GAIN (dB) 30 10 65 55 LT1999-20 Small Signal Frequency Response LT1999-10 Small Signal Frequency Response 20 35 45 VCM (V) LT1999-10 LT1999-20 LT1999-50 –5 20 45 70 95 TEMPERATURE (°C) 120 145 1999 G15 –0.50 LT1999-10 LT1999-20 LT1999-50 –5 5 15 25 35 45 VCM (V) 55 65 75 1999 G16 1999fb 8 LT1999-10/LT1999-20/ LT1999-50 Typical Performance Characteristics VSENSE VSENSE VSENSE 4.5 VOUT 0.100 4.5 0.075 4.0 2.5 0 2.0 1.5 –0.025 OUTPUT ERROR 1.0 0.5 1999 G20 TIME (1µs/DIV) VOUT (V) 0.025 0.15 VOUT 0.10 3.0 0.05 2.5 0 –0.05 2.0 –0.050 1.5 –0.075 1.0 –0.100 0.5 OUTPUT ERROR OUTPUT ERROR (V) 3.0 0.20 3.5 0.050 OUTPUT ERROR (V) VOUT (V) 3.5 1999 G19 TIME (2µs/DIV) LT1999-20 2V Step Response Settling Time LT1999-10 2V Step Response Settling Time 4.0 VOUT 1999 G18 TIME (2µs/DIV) VOUT (1V/DIV) VOUT 1999 G17 TIME (2µs/DIV) VOUT (1V/DIV) VOUT (1V/DIV) VOUT VSENSE (0.1V/DIV) LT1999-50 Pulse Response VSENSE (0.2V/DIV) LT1999-20 Pulse Response VSENSE (0.5V/DIV) LT1999-10 Pulse Response –0.01 –0.15 –1 0 1 2 3 4 5 6 TIME (1µs/DIV) 7 8 9 10 –0.20 1999 G21 LT1999-50 2V Step Response Settling Time 0.500 4.0 0.375 VOUT 0 2.0 –0.125 OUTPUT ERROR –0.250 –0.375 1.0 TIME (1µs/DIV) LT1999-10 LT1999-20 LT1999-50 LT1999-10 LT1999-20 LT1999-50 100 1999 G22 –0.500 80 80 CMRR (dB) 2.5 OUTPUT ERROR (V) 0.125 0.5 100 CMRR vs Frequency 120 0.250 3.0 1.5 120 CMRR (dB) 3.5 VOUT (V) CMRR vs Frequency 4.5 60 40 40 VCM = 12V 20 V+ = 5V TA = 25°C 6 UNITS PLOTTED 0 1000 1 10 100 FREQUENCY (kHz) 60 VCM = 0V V+ = 5V TA = 25°C 6 UNITS PLOTTED 20 10000 1999 G23 0 1 10 100 1000 FREQUENCY (kHz) 10000 1999 G24 1999fb 9 LT1999-10/LT1999-20/ LT1999-50 Typical Performance Characteristics LT1999-10 Common Mode Rising Edge Step Response LT1999-10 Common Mode Falling Edge Step Response VCM , tRISE ≈ 20ns VOUT (0.5V/DIV) VOUT TIME (0.5µs/DIV) VCM (25V/DIV) VCM (25V/DIV) VOUT (0.5V/DIV) VCM , tFALL ≈ 20ns VOUT 1999 G25 1999 G26 TIME (0.5µs/DIV) LT1999-20 Common Mode Rising Edge Step Response LT1999-20 Common Mode Falling Edge Step Response VOUT (0.5V/DIV) VOUT TIME (0.5µs/DIV) VCM , tFALL ≈ 20ns VCM (25V/DIV) VCM (25V/DIV) VOUT (0.5V/DIV) VCM , tRISE ≈ 20ns VOUT 1999 G27 1999 G28 TIME (0.5µs/DIV) LT1999-50 Comm Step Response LT1999-50 Common Mode Falling Edge Step Response VCM tRISE20ns VOUT (0.5V/DIV) VCM , tFALL ≈ 20ns VCM (25V/DIV) VCM (25V/DIV) VOUT (0.5V/DIV) VCM , tRISE ≈ 20ns VOUT VOUT (0.5 V / div) LT1999-50 Common Mode Rising Edge Step Response TIM VOUT TIME (0.5µs/DIV) 1999 G29 TIME (0.5µs/DIV) 1999 G30 1999fb 10 LT1999-10/LT1999-20/ LT1999-50 Typical Performance Characteristics LT1999 Input Referred Noise Density vs Frequency Short-Circuit Current vs Temperature 1000 3.0 40 30 SINKING REF PIN VOLTAGE (V) ISC (mA) 100 10 0 –10 –20 SOURCING 0.1 1 10 FREQUENCY (kHz) 1000 10000 –5 20 45 70 95 TEMPERATURE (°C) 1999 G31 0 1.5 1.0 V+ = 5V 0 –55 –30 –5 120 145 20 45 70 95 TEMPERATURE (°C) Turn-On/Turn-Off Time vs SHDN Voltage V+ = 5V VCM = 12V VCM = 12V IS (1mA/DIV) TA = 150°C TA = 25°C TA = –55°C SHDN PIN VOLTAGE (5V/DIV) IS –1 –2 SHUTDOWN –3 VSHDN –4 6 0 1 2 3 VSHDN (V) 4 5 1999 G35 TIME (1µs/DIV) 1999 G34 VOUT vs VSENSE Over the Sense ABSMAX Range VOUT vs VSENSE 6 VREF = 2.5V 5 4 4 3 3 VOUT (V) 5 2 1 VOUT PHASE REVERSAL FOR VSENSE < –25V 2 1 LT1999-10 LT1999-20 LT1999-50 0 –1 –0.25 120 145 1999 G33 1999 G32 SHDN Pin Current vs SHDN Pin Voltage and Temperature ISHDN (µA) 0.01 –40 –55 –30 SHDN MODE 2.0 0.5 –30 10 0.001 ACTIVE MODE 2.5 20 VOUT (V) NOISE DENSITY (nV/√Hz) REF Open Circuit Voltage vs Temperature –0.15 0.05 –0.05 VSENSE (V) 0.15 0.25 1999 G36 LT1999-10 LT1999-20 LT1999-50 0 VREF = 2.5V –1 –60 –30 0 VSENSE (V) 30 60 1999 G37 1999fb 11 LT1999-10/LT1999-20/ LT1999-50 Pin Functions V+ (Pins 1, 4): Power Supply Voltage. Pins 1 and 4 are tied internally together. The specified range of operation is 4.5V to 5.5V, but lower supply voltages (down to approximately 4V) is possible although the LT1999 is not tested or characterized below 4.5V. See the Applications Information section. OUT (Pin 7): Voltage Output. VOUT = AV •(VSENSE ± VOSI), where AV is the gain, and VOSI is the input referred offset voltage. The output amplifier has a low impedance output and is designed to drive up to 200pF capacitive loads directly. Capacitive loads exceeding 200pF should be decoupled with an external resistor of at least 100Ω. +IN (Pin 2): Positive Sense Input Pin. SHDN (Pin 8): Shutdown Pin. When pulled to within 0.5V of GND (Pin 5), will place the LT1999 into low power shutdown. If the pin is left floating, an internal 2µA pullup current source will place the LT1999 into the active (amplifying) state. –IN (Pin 3): Negative Sense Input Pin. GND (Pin 5): Ground Pin. REF (Pin 6): Reference Pin Input. The REF pin sets the output common mode level and is set halfway between V+ and GND using a divider made of two 160k resistors. The default open circuit potential of the REF pin is mid-supply. It can be overdriven by an external voltage source cable of driving 80k to a mid-supply potential (see the Electrical Characteristics table for its specified input voltage range). 1999fb 12 LT1999-10/LT1999-20/ LT1999-50 Block Diagram V+ 2µA V+ 4.5k V(G+IN) R +IN 2 2k 2k +IN CF 4pF 3 8 SHDN 1 2k –IN 2k + GIN – V(G–IN) 0.8k R +S RG – + AO V+ D1 OUT 7 V+ 0.8k R –S 300Ω 160k REF 6 160k R –IN V+ GND 4 5 1999 BD Figure 1. Simplified Block Diagram Test Circuit V+ LT1999 V+ 5V 2µA 1 VCM + – + – V + + – 4k 2 + – 8 V SHDN SHDN + 0.8k RG – + V+ VIN(DIFF) – 4k 3 0.8k 160k 6 V+ 5V 7 V OUT 160k 4 VREF 0.1µF 5 0.1µF 1999 F02 Figure 2. Test Circuit 1999fb 13 LT1999-10/LT1999-20/ LT1999-50 Applications Information The LT1999 current sense amplifier provides accurate bidirectional monitoring of current through a user-selected sense resistor. The voltage generated by the current flowing in the sense resistor is amplified by a fixed gain of 10V/V, 20V/V or 50V/V (LT1999-10, LT1999-20, or LT1999-50 respectively) and is level shifted to the OUT pin. The voltage difference and polarity of the OUT pin with respect to REF (Pin 6) indicates magnitude and direction of the current in the sense resistor. Theory of Operation Refer to the Block Diagram (Figure 1). Case 1: V+ < VCM < 80V For input common mode voltages exceeding the power supply, one can assume D1 of Figure 1 is completely off. The sensed voltage (VSENSE) is applied across Pin 2 (+IN) and Pin 3 (–IN) to matched resistors R+IN and R– IN (nominally 4k each). The opposite ends of R+IN and R– IN are forced to equal potentials by transconductor GIN, which convert the differentially sensed voltage into a sensed current. The sensed current in R+IN and R– IN is combined, level-shifted, and converted back into a voltage by transresistance amplifier AO and resistor RG. Amplifier AO provides high open loop gain to accurately convert the sensed current back into a voltage and to drive external loads. The theoretical output voltage is determined by the sensed voltage (VSENSE), and the ratio of two on-chip resistors: VOUT − VREF = VSENSE • RG RIN Case 2: –5V < VCM < V+ For common mode inputs which transition or are set below the supply voltage, diode D1 will turn on and will provide a source of current through R+S and R –S to bias the inputs of transconductance amplifier GIN at least 2.25V above GND. The transition is smooth and continuous; there are negligible changes to either gain or amplifier voltage offset. The only difference in amplifier operation is the bias currents provided by D1 through R+S and R– S are steered through the input pins, otherwise amplifier operation is identical. The inputs to transconductance amplifier GIN are still forced to equal potentials forcing any differential voltages appearing at the +IN and –IN pins into a differential current. This differential current is combined, level-shifted, and converted back into a voltage by trans-resistance amplifier AO and Resistor RG. Resistors R+S and R– S are trimmed to match R+IN and R– IN respectively, to prevent common mode to differential conversion from occurring (to the extent of the matched trim) when the input common mode transitions below V+. As described in case 1, the output is determined by the sense voltage and the ratio of two on-chip resistors: VOUT − VREF = VSENSE • RG RIN where where RIN = The voltage difference between the OUT pin and the REF pin represent both polarity and magnitude of the sensed voltage. The noninverting input of amplifier AO is biased by a resistive 160k to 160k divider tied between V+ and GND to set the default REF pin bias to mid-supply. R +IN + R −IN nominally 4k 2 RIN = R +IN + R −IN 2 For the LT1999-10, RG is nominally 40k. For the LT1999-20, RG is nominally 80k, and for the LT1999-50, RG is nominally 200k. 1999fb 14 LT1999-10/LT1999-20/ LT1999-50 Applications Information Input Common Mode Range –2.0 With the V+ supply configured within the specified and tested range (4.5V < V+ < 5.5V), the LT1999’s common mode range extends from –5V to 80V. Pushing +IN and –IN beyond the limits specified in the Absolute Maximum table can turn on the voltage clamps designed to protect the +IN and –IN pins during ESD events. It is possible to operate the LT1999 on power supplies as low as 4V (although it is not tested or specified below 4.5V). Operating the LT1999 on supplies below 4V will produce erratic behavior. When operating the LT1999 with supplies as low as 4V, the common mode range for inputs which extend below GND is reduced. Refer to the Block Diagram (Figure 1). For inputs driven below V+, diode D1 conducts. For proper operation, the input to the transconductor V(G+IN) must be biased at approximately 2.25V above the GND pin. V(G+IN) sits on the centertap of a voltage divider comprised of R+S and R+IN V(G –IN) likewise sits in the middle of the voltage divider comprised of R – S , and R–IN). The voltage on V(G+IN) input is given by the following equation: R +S R +IN V(G ) = V • + V + −VD1 • +IN +IN R +S + R +IN R +S + R +IN ( ) Setting V(G+IN) = 2.25V, the ratio (R+IN /R+S) to 5, and VD1 equal to 0.8V (cold temperatures), a plot of the lower input common mode range plotted against supply is shown in Figure 3. –2.5 VCM(LOWER LIMIT) (V) The LT1999 was optimized for high common mode rejection. Its input stage is balanced and fully differential, designed to amplify differential signals and reject common mode signals. There is negligible crossover distortion due to sense voltage reversals. The amplifier is most linear in the zero-sense region. BELOW GROUND INPUT COMMON MODE RANGE LIMITED BY V+ SUPPLY VOLTAGE –3.0 –3.5 –4.0 BELOW GROUND INPUT COMMON MODE RANGE LIMITED BY ESD CLAMPS –4.5 –5.0 –5.5 –6.0 TYPICAL ESD CLAMP VOLTAGE 4 4.25 4.5 5 4.75 SUPPLY VOLTAGE (V) 5.25 5.5 1999 F03 Figure 3. Lower Input Common Mode vs Supply Voltage Output Common Mode Range The LT1999’s output common mode level is set by the voltage on the REF pin. The REF pin sits in the middle of a 160k to 160k voltage divider connected between V+ and GND which sets the default open circuit potential of the REF pin to mid-supply. It can be overdriven by an external voltage source capable of driving 80k tied to a mid-supply potential. See the Electrical Characteristics table for the REF pin’s specified input voltage range. Differential sampling of the OUT pin with respect the REF pin provides the best noise immunity. Measurements of the output voltage made differentially with respect to the REF pin will provide the highest power supply and common mode rejection. Otherwise, power supply or GND pin disturbances are divided by the REF pin’s voltage divider and appear directly at the noninverting input of the transresistance amplifier AO and are not rejected. If not driven by a low impedance (<100Ω), the REF pin should be filtered with at least 1nF of capacitance to a low impedance, low noise ground plane. This external capacitance will also provide a charge reservoir during high frequency sampling of the REF pin by ADC inputs attached to this pin. 1999fb 15 LT1999-10/LT1999-20/ LT1999-50 Applications Information Shutdown Capability If SHDN (Pin 8) is driven to within 0.5V of GND, the LT1999 is placed into a low power shutdown state in which the part will draw about 3μA from the V+ supply. The input pins (+IN and –IN) will draw approximately 1nA if biased within the range of 0V to 80V (with no differential voltage applied). If the input pins are pulled below the GND pin, each input appears as a diode tied to GND in series with approximately 4k of resistance. The REF pin appears as approximately 0.4MΩ tied to a mid-supply potential. The output appears as reverse biased diodes tied between the output to either V+ or GND pins. EMI Filtering and Layout Practices An internal 1st order differential lowpass noise/EMI suppression filter with a –3dB bandwidth of 10MHz (approximately 5× the LT1999’s –3dB bandwidth) is included to help improve the LT1999’s EMI susceptibility and to assist with the rejection of high frequency signals beyond the bandwidth of the LT1999 that may introduce errors. The pole is set by the following equation: ffilt = 1/(π•(R+IN + R–IN)•CF) ≈ 10MHz Both the resistors and capacitors have a ±15% variation so the pole can vary by approximately ±30% over manufacturing process and temperature variations. The layout for lowest EMI/noise susceptibility is achieved by keeping short direct connections and minimizing loop areas (see Figure 4). If the user-supplied sense resistor cannot be placed in close proximity to the LT1999, the surface area of the loop comprising connections of +IN to RSENSE and back to –IN should be minimized. This requires routing PCB traces connecting +IN to RSENSE and –IN to RSENSE adjacent with one another with minimal separation. The metal traces connecting +IN to the sense resistor and –IN to the sense resistor should match and use the same trace width. Bypassing the V+ pin to the GND pin with a 0.1µF capacitor with short wiring connection is recommended. † 1 V+ FROM DC SOURCE RSENSE * TO LOAD SHDN 8 2 +IN OUT 7 3 –IN REF 6 4 V+ GND 5 DIFFERENTIAL ANALOG OUT ** SUPPLY BYPASS CAPACITOR 1999 F03 * KEEP LOOP AREA COMPRISING RSENSE, +IN AND –IN PINS AS SMALL AS POSSIBLE. ** REF BYPASS TIED TO A LOW NOISE, LOW IMPEDANCE SIGNAL GROUND PLANE. † OPTIONAL 10pF CAPACITOR TO PREVENT dV/dt EDGES ON INPUT COUPLING TO FLOATING SHDN PIN. Figure 4. Recommended Layout 1999fb 16 LT1999-10/LT1999-20/ LT1999-50 Applications Information The REF pin should be either driven by a low source impedance (<100Ω) or should be bypassed with at least 1nF to a low impedance, low noise, signal ground plane (see Figure 4). Larger bypass capacitors on both V+ pins, and the REF pin, will extend enhanced AC CMRR, and PSRR performance to lower frequencies. Bypassing the REF pin to a quiet ground plane filters the V+ pin or GND pin noise that is sensed by the REF pin voltage divider and applied to the noninverting input of output amplifier AO. Any common I•R drops generated by pulsating ground currents in common with the REF pin filter capacitor can compromise the filtering performance and should be avoided. If the SHDN pin is not driven and is left floating, routing a PCB trace connecting Pins 1 and 8 under the part will act as a shield, and will help limit edge coupling from the inputs (Pins 2 and 3) to the SHDN pin. Periodic pulses on the inputs with fast edges may glitch the high impedance SHDN pin, periodically putting the part into low power shutdown. Additional precaution against this may be taken by adding an optional small (~10pF) capacitor may be tied between V+ (Pin 1) and Pin 8. Finally, when connecting the LT1999 inputs to the sense resistor, it is important to use good Kelvin sensing practices (sensing the resistor in a way that excludes PCB trace I•R voltage drops). For sense resistors less than 1Ω, one might consider using a 4-wire sense resistor to sense the resistive element accurately. Selection of the Current Sense Resistor The external sense resistor selection presents a delicate trade-off between power dissipation in the resistor and current measurement accuracy. In high current applications, the user may want to minimize the power dissipated in the sense resistor. The sense resistor current will create heat and voltage loss, degrading efficiency. As a result, the sense resistor should be as small as possible while still providing adequate dynamic range required by the measurement. The dynamic range is the ratio between the maximum accurately produced signal generated by the voltage across the sense resistor, and the minimum accurately reproduced signal. The minimum accurately reproduced signal is primarily dictated by the voltage offset of the LT1999. The maximum accurately reproduced signal is dictated by the output swing of the LT1999. Thus the dynamic range for the LT1999 can be thought of the maximum sense voltage divided by the input referred voltage offset or: Dynamic Range = ∆VOUT(MAX) GAIN • VOSI The above equation tells us that the dynamic range is inversely proportional to the gain of the LT1999. Thus, if accuracy is of greater importance than efficiency or power loss, the LT1999-10 used with the highest valued sense resistor possible is recommended. If efficiency, heat generated, and power loss in the resistive shunt is the primary concern, the LT1999-50 and the lowest value sense resistor possible is recommended. The LT1999-20 is available for applications somewhere in between these two extremes. 1999fb 17 LT1999-10/LT1999-20/ LT1999-50 Applications Information Fuse Monitor The inputs can be overdriven without fear of damaging the LT1999. This makes the LT1999 ideal for monitoring fuses if either +IN or –IN are shorted to ground while the other is at the full common mode supply voltage (see Figure 5). If the fuse in Figure 5 opens with the +IN tied to the positive supply, the load will pull –IN to GND. The output will be forced to the positive V+ supply rail. If it is desired that the output be near ground if the fuse opens, it is a simple matter of swapping the inputs. Precautions should be followed: First, when the inputs are stressed differentially due to the fuse blowing open, a large voltage drop will be placed across the +IN to –IN pins, dissipating VS V+ LT1999 2µA 1 VSHDN + – 4k V+IN 2 VOUT VREF STEERING DIODE V+ FUSE 8 SHDN ILOAD LOAD Finally, the user should be aware that in fuse monitoring applications with the sense voltage (VSENSE = V+IN – V–IN) being driven in excess of –25V, the output of the LT1999 will undergo phase reversal (see Figure 6). V+ 5V ON OFF power in the precision on-chip input resistors. Precaution should be taken to prevent junction temperatures from exceeding the Absolute Maximum ratings (see Note 3 in the Electrical Characteristics section). Secondly, if the load is inductive, and the fuse blows open without a clamp diode, energy stored in the inductive load will be dissipated in the LT1999, which could cause damage. A simple steering diode as shown in Figure 5 will prevent this from happening, and will protect the LT1999 from damage. VSHDN RG – + 0.8k 7 VOUT V+ RSENSE V–IN 3 4k 0.8k 160k 6 V+ 5V 160k 4 VREF 0.1µF 5 0.1µF 1999 F05 Figure 5. Using the LT1999 to Monitor a Fuse VOUT (1V/DIV) VOUT PHASE REVERSAL FOR VSENSE < –25V VREF = 2.5V –60 –45 –30 –15 0 15 VSENSE (V) 30 45 60 1999 F06 Figure 6. A Plot of the LT1999’s Output Voltage vs VSENSE (VSENSE = V+IN – V– IN). In Applications Where the Sense Voltage Is Driven in Excess of –25V, the Output of the LT1999 Will Undergo Phase Reversal 1999fb 18 LT1999-10/LT1999-20/ LT1999-50 Typical Applications Solenoid Current Monitor Bidirectional PWM Motor Monitor The solenoid of Figure 7 consists of a coil of wire in an iron case with permeable plunger that acts as a movable element. When the MOSFET turns on, the diode is reversed biased off, and current flows through RSENSE to actuate the solenoid. If the MOSFET is turned off, the current in the MOSFET is interrupted, but the energy stored in the solenoid causes the diode to turn on and current to freewheel in the loop consisting of the diode, RSENSE and the solenoid. Pulse width modulation is commonly used to efficiently vary the average voltage applied across a DC motor. The H-bridge topology of Figure 9 allows full 4-quadrant control: clockwise control, counter-clockwise control, clockwise regeneration, and counter-clockwise regeneration. The LT1999 in conjunction with a non-inductive current shunt is used to monitor currents in the rotor. The LT1999 can be used to detect stuck rotors, provide detection of overcurrent conditions in general, or provide current mode feedback control. Figure 7 shows the LT1999 monitoring currents in a ground referenced solenoid used when the coil is hard tied to the case, and is tied to ground. Figure 8 shows a supply referenced solenoid whose coil is insulated from the case. The LT1999 will interface equally well to either of these two configurations. VS V+ LT1999 V+ 5V 2µA 1 V+IN + – 4k 2 V + 0.8k VSHDN RG – + 7 VOUT V–IN 4k 3 5V V+ 0.8k 160k 6 0.1µF 160k 4 VREF 2.5V VOUT V+IN (10V/DIV) V+ RSENSE SOLENOID 8 SHDN VOUT (0.5V/DIV) OFF ON Figure 10 shows a plot of the output voltage of the LT1999. SOLENOID RELEASES SOLENOID PLUNGER PULLS IN V+IN 5 0.1µF 1999 F07a TIME (50ms/DIV) 1999 F07b Figure 7. Solenoid Current Monitor for Ground Tied Solenoid. The Common Mode Inputs to the LT1999 Switch Between VS and One Diode Drop Below Ground 1999fb 19 LT1999-10/LT1999-20/ LT1999-50 Typical Applications V+ LT1999 VS 1 2µA V+ SOLENOID V+IN + – 4k 2 + V 0.8k – + 7 VOUT 3 5V 4 4k V+ 0.8k 160k 6 VREF 160k 0.1µF 2.5V VOUT V+IN (10V/DIV) V–IN ON VSHDN RG V+ RSENSE OFF 8 SHDN VOUT (0.5V/DIV) 5V SOLENOID RELEASES SOLENOID PLUNGER PULLS IN V+IN 5 0.1µF 1999 F08a TIME (50ms/DIV) 1999 F08b Figure 8. Solenoid Current Monitor for Non-Grounded Solenoids. This Circuit Performs the Same Function as Figure 7 Except One End of the Solenoid Is Tied to VS. The Common Mode Voltage of Inputs of the LT1999 Switch Between Ground and One Diode Drop Above VS 1999fb 20 LT1999-10/LT1999-20/ LT1999-50 Typical Applications 5V V+ 10µF V+ LT1999-20 1 2µA SHDN + – 24V 4k 2 V+IN C4 1000µF 0.8k 80k V–IN 3 0.1µF – + 7 4k 0.8k 160k 6 160k 5V V+ 5V OUTA DIRECTION VOUT VREF 0.1µF 5 4 PWM INPUT VSHDN V+ VBRIDGE H-BRIDGE RSENSE 0.025Ω 1999 F09 24V MOTOR OUTB BRAKE INPUT GND Figure 9. Armature Current Monitor for DC Motor Applications VOUT 2.5V V+IN (20V/DIV) VOUT (2V/DIV) PWM IN V+ 8 V+IN TIME (20µs/DIV) 1999 F10 Figure 10. LT1999 Output Waveforms for the Circuit of Figure 9 1999fb 21 LT1999-10/LT1999-20/ LT1999-50 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 0.254 (.010) 8 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.52 (.0205) REF 0° – 6° TYP GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 1 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 4 0.86 (.034) REF 0.18 (.007) 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ± .0015) TYP 2 3 1.10 (.043) MAX SEATING PLANE RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.22 – 0.38 (.009 – .015) TYP 0.1016 ± 0.0508 (.004 ± .002) 0.65 (.0256) BSC MSOP (MS8) 0307 REV F S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .050 BSC .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) NOTE: 1. DIMENSIONS IN 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) 6 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP .008 – .010 (0.203 – 0.254) 7 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 2 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 0303 1999fb 22 LT1999-10/LT1999-20/ LT1999-50 Revision History REV DATE DESCRIPTION PAGE NUMBER A 5/11 Revised +IN and –IN pin descriptions in Pin Functions section 12 B 3/12 Revised Voltage Output Swing Low specification (VOUT) under a loaded condition of 1kΩ to mid-supply. 4, 6 Updated Figure 4 to multicolor. 16 1999fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LT1999-10/LT1999-20/ LT1999-50 Typical Application Battery Charge Current and Load Current Monitor VOUT = 0.25V/A, Maximum Measured Current ±9.5A 0.025Ω CHARGER BAT 42V V+ 5V 2µA 1 V+IN SHDN + – 4k 2 + V 0.8k 8 VSHDN 7 VOUT 4k 3 0.8k V+ 5V 0.1µF 0.1µF 10µF 40k – + V+ V–IN 5V V+ LT1999-10 LOAD 160k + +IN VOUT 6 160k VREF – VCC VREF LTC2433-1 –IN CS SCK SDO 0.1µF 5 4 0.1µF 1999 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LT1787/ LT1787HV Precision, Bidirectional High Side Current Sense Amplifier 2.7V to 60V Operation, 75μV Offset, 60μA Current Draw LT6100 Gain-Selectable High Side Current Sense Amplifier 4.1V to 48V Operation, Pin-Selectable Gain: 10V/V, 12.5V/V, 20V/V, 25V/V, 40V/V, 50V/V LTC6101/ LTC6101HV High Voltage High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, External Resistor Set Gain, SOT23 LTC6102/ LTC6102HV Zero Drift High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, ±10μV Offset, 1μs Step Response, MSOP8/DFN Packages LTC6103 Dual High Side Precision Current Sense Amplifier 4V to 60V, Gain Configurable, 8-Pin MSOP Package LTC6104 Bidirectional, High Side Current Sense 4V to 60V, Gain Configurable, 8-Pin MSOP Package LT6106 Low Cost, High Side Precision Current Sense Amplifier 2.7V to 36V, Gain Configurable, SOT23 Package LT6105 Precision, Extended Input Range Current Sense Amplifier –0.3 to 44V, Gain Configurable, 8-Pin MSOP Package LTC4150 Coulomb Counter/Battery Gas Gauge Indicates Charge Quantity and Polarity LT1990 Precision, 100μA Gain Selectable Amplifier 2.7V to 36V Operation, CMRR > 70dB, Input Voltage = ±250V LT1991 ±250V Input Range Difference Amplifier 2.7V to 36V Operation, 50μV Offset, CMRR > 75B, Input Voltage = ±60V LT1637/LT1638 1.1/1.2MHz, 0.4V/μs Over-The-Top, Rail-to-Rail Input and Output Amplifier 0.4V/μs Slew Rate, 230μA per Amplifier 1999fb 24 Linear Technology Corporation LT 0312 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com LINEAR TECHNOLOGY CORPORATION 2010