LINER LT3460ES5

LT3460
1.3MHz Step-Up DC/DC
Converter in SC70 and ThinSOT
U
DESCRIPTIO
FEATURES
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1.3MHz Switching Frequency
High Output Voltage: Up to 36V
300mA Integrated Switch
12V at 70mA from 5V Input
5V at 60mA from 3.3V Input
Wide Input Range: 2.5V to 16V
Uses Small Surface Mount Components
Low Shutdown Current: <1µA
Low Profile (1mm) SC70 and SOT-23 (ThinSOTTM)
Packages
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APPLICATIO S
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The high voltage switch in the LT3460 is rated at 38V,
making the device ideal for boost converters up to 36V.
The LT3460 can generate 12V at up to 70mA from a 5V
supply.
The LT3460 is available in SC70 and SOT-23 packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation
Digital Cameras
CCD Bias Supply
XDSL Power Supply
TFT-LCD Bias Supply
Local 5V or 12V Supply
Medical Diagnostic Equipment
Battery Backup
U
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The LT®3460 is a general purpose step-up DC/DC converter. The LT3460 switches at 1.3MHz, allowing the use
of tiny, low cost and low height capacitors and inductors.
The constant frequency results in low, predictable output
noise that is easy to filter.
TYPICAL APPLICATIO
Efficiency
90
5V to 12V, 70mA Step-Up DC/DC Converter
22µH
VIN
5V
4.7µF
VIN
VOUT
12V
70mA
SW
130k
22pF
EFFICIENCY (%)
85
80
75
70
65
LT3460
OFF ON
SHDN
60
FB
GND
1µF
15k
0
20
40
60
LOAD CURRENT (mA)
80
3460 F01a
Switching Waveforms
3460 F01
VSW
5V/DIV
IL
100mA/DIV
0.2µs/DIV
3460 F01b
3460f
1
LT3460
U
W W
W
ABSOLUTE
AXI U RATI GS
(Note 1)
Input Voltage (VIN) .................................................. 16V
SW Voltage .............................................................. 38V
FB Voltage ................................................................. 5V
SHDN Voltage .......................................................... 16V
Operating Ambient
Temperature Range (Note 2) .................. – 40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
ORDER PART
NUMBER
TOP VIEW
SW 1
5 VIN
LT3460ES5
GND 2
FB 3
4 SHDN
SW 1
6 VIN
GND 2
5 GND
FB 3
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
S5 PART MARKING
TJMAX = 125°C, θJA = 256°C/W IN FREE AIR
θJA = 120°C ON BOARD OVER
GROUND PLANE
LTB1
LT3460ESC6
4 SHDN
SC6 PART MARKING
SC6 PACKAGE
6-LEAD PLASTIC SC70
LAAF
TJMAX = 125°C, θJA = 400°C/W IN FREE AIR
θJA = 270°C/W ON BOARD OVER GROUND
PLANE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 3V, VSHDN = 3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Minimum Operating Voltage
TYP
UNITS
2.5
V
Maximum Operating Voltage
Feedback Voltage
●
Feedback Line Regulation
MAX
1.235
1.225
2.5V < VIN < 16V
FB Pin Bias Current
V
1.275
1.280
V
V
0.015
●
5
Supply Current
SHDN = 0V
Switching Frequency
1.255
16
1.0
%/V
25
80
nA
2.0
0.1
3.0
0.5
mA
µA
1.3
1.7
MHz
Maximum Duty Cycle
85
90
Switch Current Limit
300
420
600
mA
320
450
mV
0.01
1
µA
Switch VCESAT
ISW = 250mA
Switch Leakage Current
VSW = 5V
SHDN Voltage High
1.5
V
SHDN Voltage Low
SHDN Pin Bias Current
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
%
0.4
40
V
µA
Note 2: The LT3460E is guaranteed to meet specifications from 0°C to
70°C. Specifications over the –40°C to 85°C operating temperature range
are assured by design, characterization and correlation with statistical
process controls.
3460f
2
LT3460
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TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current
SHDN Pin Bias Current
Switching Frequency
2.5
1.4
400
1.2
350
25°C
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
–50
15
10
5
SHDN = 16V
300
250
200
150
100
50
–25
VIN (V)
50
25
0
TEMPERATURE (°C)
3460 G01
0
–50
100
75
SHDN = 3V
–25
50
25
0
TEMPERATURE (°C)
3460 G02
Feedback Bias Current
75
100
3460 G03
Feedback Voltage
30
1.260
25
1.255
20
VFB (V)
FEEDBACK BIAS CURRENT (nA)
0
15
1.250
10
1.245
5
0
–50
–25
50
25
0
TEMPERATURE (°C)
75
1.240
–50
100
–25
50
25
0
TEMPERATURE (°C)
75
3460 G04
Current Limit vs Duty Cycle
400
350
450
400
IC = 250mA
350
300
250
IC = 200mA
200
150
100
IC = 100mA
300
250
200
150
100
50
0
–50
100
3460 G05
Switch Saturation Voltage
(VCESAT)
VCESAT (mV)
IQ (mA)
100°C
CURRENT LIMIT (mA)
2.0
SHDN PIN BIAS CURRENT (µA)
SWITCHING FREQUENCY (MHz)
–50°C
50
0
–25
50
25
0
TEMPERATURE (°C)
75
100
3460 G06
0
0.2
0.6
0.4
DUTY CYCLE
0.8
1.0
3460 G07
3460f
3
LT3460
U
U
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PI FU CTIO S
(ThinSOT/SC70 Packages)
SW (Pin 1/Pin 1): Switch Pin. Connect inductor/diode
here. Minimize trace at this pin to reduce EMI.
SHDN (Pin 4/Pin 4): Shutdown Pin. Tie to 1.5V or higher
to enable device; 0.4V or less to disable device. Also
functions as soft-start. Use RC filter (47k, 47nF typ) as
shown in Figure 1.
GND (Pin 2/Pins 2 and 5): Ground Pin. Tie directly to local
ground plane.
VIN (Pin 5/Pin 6): Input Supply Pin. Must be locally
bypassed.
FB (Pin 3/Pin 3): Feedback Pin. Reference
voltage is 1.255V. Connect resistor divider tap here.
Minimize trace area at FB. Set VOUT according to
VOUT = 1.255V (1 + R1/R2).
W
BLOCK DIAGRA
VIN
(PIN 6 SC70 PACKAGE) 5
1.255V
REFERENCE
COMPARATOR
+
–
A1
VOUT
–
A2
RC
3 FB
R2 (EXTERNAL)
SW
R
Q
Q1
S
+
R1 (EXTERNAL)
FB
1
DRIVER
CC
+
∑
0.1Ω
–
SHUTDOWN
RS (EXTERNAL)
4 SHDN
RAMP
GENERATOR
CS (EXTERNAL)
RS, CS OPTIONAL SOFT-START COMPONENTS
1.3MHz
OSCILLATOR
2
GND
(PINS 2 AND 5 SC70 PACKAGE)
3460 BD
Figure 1. Block Diagram
U
OPERATIO
The LT3460 uses a constant frequency, current mode
control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the
block diagram in Figure 1. At the start of each oscillator
cycle, the SR latch is set, which turns on the power switch
Q1. A voltage proportional to the switch current is added
to a stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A2. When this
voltage exceeds the level at the negative input of A2, the SR
latch is reset turning off the power switch. The level at the
negative input of A2 is set by the error amplifier A1, and is
simply an amplified version of the difference between the
feedback voltage and the reference voltage of 1.255V. In
this manner, the error amplifier sets the correct peak
current level to keep the output in regulation. If the error
amplifier’s output increases, more current is delivered to
the output; if it decreases, less current is delivered.
3460f
4
LT3460
U
OPERATIO
Feedback Loop Compensation
is about 70kHz.
The LT3460 has an internal feedback compensation network as shown in Figure 1 (RC and CC). However, because
the small signal characteristics of a boost converter change
with operation conditions, the internal compensation network cannot satisfy all applications. A properly designed
external feed forward capacitor from VOUT to FB (CF in
Figure 2) will correct the loop compensation for most
applications.
The feedback loop gain T(s) = K3 • GP(s) • GC(s). If it
crosses over 0dB far before fZ, the phase margin will be
small. Figure 3 is the Bode plot of the feedback loop gain
measured from the converter shown in Figure 2 without
the feedforward capacitor CF. The result agrees with
the previous discussion: Phase margin of about 20° is
insufficient.
60
VIN
5V
5
1
VIN
SW
R2
130k
CF
22pF
VOUT
12V
70mA
LT3460
OFF ON
4
SHDN
FB
3
GND
2
R1
15k
C1: TAIYO YUDEN X5R JMK212BJ475KG
C2: TAIYO YUDEN X5R EMK316BJ105
D1: CENTRAL SEMICONDUCTOR CMDSH2-3
L1: MURATA LQH32CN-220 OR EQUIVALENT
C2
1µF
90
50
45
GAIN
40
0
30
–45
20
–90
PHASE
10
–135
0
–180
–10
–225
–20
–270
–30
–315
1
10
100
FREQUENCY (kHz)
Figure 2. 5V to 12V Step-Up Converter
The LT3460 uses peak current mode control. The current
feedback makes the inductor very similar to a current
source in the medium frequency range. The power stage
transfer function in the medium frequency range can be
approximated as:
GP(s ) =
K1
,
s • C2
where C2 is the output capacitance, and K1 is a constant
based on the operating point of the converter. In continuous current mode, K1 increases as the duty cycle decreases.
The internal compensation network RC, CC can be approximated as follows in medium frequency range:
GC(s ) = K2 •
s • RC • CC + 1
s • CC
The zero
fZ =
1
2 • π • RC • CC
–360
1000
–40
3460 F02
PHASE (DEG)
C1
4.7µF
D1
GAIN (dB)
L1
22µH
3460 F03
Figure 3
In order to improve the phase margin, a feed-forward
capacitor CF in Figure 2 can be used.
Without the feed-forward capacitor, the transfer function
from VOUT to FB is:
FB
R1
=
VOUT R1 + R2
With the feed-forward capacitor CF, the transfer function
becomes:
FB
R1
s • R2 • CF + 1
•
=
VOUT R1 + R2 s • R1 • R2 • C + 1
F
R1 + R2
The feed-forward capacitor CF generates a zero and a pole.
The zero always appears before the pole. The frequency
distance between the zero and the pole is determined only
by the ratio between VOUT and FB. To give maximum phase
3460f
5
LT3460
U
OPERATIO
margin, CF should be chosen so that the midpoint frequency between the zero and the pole is at the cross over
frequency.
With CF = 20pF, the feedback loop Bode plot is reshaped
as shown in Figure 4. The phase margin is about 60°.
90
60
45
GAIN
40
0
30
–45
–90
20
PHASE
10
–135
0
–180
–10
–225
–20
–270
–30
–315
10
100
FREQUENCY (kHz)
The high speed operation of the LT3460 demands careful
attention to board layout. You will not get advertised
performance with careless layout. Figure 5 shows the
recommended component placement.
3460 F04
Figure 4.
L1
D1
For most of the applications of LT3460, the output capacitor ESR zero is at very high frequency and can be ignored.
If a low frequency ESR zero exists, for example, when a
high-ESR Tantalum capacitor is used at the output, the
phase margin may be enough even without a feed-forward
capacitor. In these cases, the feed-forward capacitor should
not be added because it may cause the feedback loop to
not have enough attenuation at the switching frequency.
Layout Hints
–360
1000
–40
1
PHASE (DEG)
GAIN (dB)
50
The feed-forward capacitor increases the gain at high
frequency. The feedback loop therefore needs to have
enough attenuation at the switching frequency to reject the
switching noise. Additional internal compensation components have taken this into consideration.
C1
L1
D1
C1
+
+
VOUT
VIN
VOUT
VIN
+
+
C2
C2
SHUTDOWN
R2
GND
SHUTDOWN
R2
R1
CF
GND
(SOT-23 PACKAGE)
R1
CF
(SC70 PACKAGE)
3460 F05
Figure 5. Suggested Layout
3460f
6
LT3460
U
TYPICAL APPLICATIO S
Efficiency
5V to 12V Step-Up Converter
90
VIN
5V
D1
5
C1
4.7µF
VOUT
12V
70mA
1
VIN
130k
SW
85
22pF
EFFICIENCY (%)
L1
22µH
LT3460
SHDN
4
SHDN
3
FB
C2
1µF
15k
GND
2
C1: TAIYO YUDEN X5R JMK212BJ475
C2: TAIYO YUDEN X5R EMK212BJ105
D1: CENTRAL SEMICONDUCTOR CMDSH2-3
L1: MURATA LQH32CN-220 OR EQUIVALENT
80
75
70
65
60
3460 TA01
0
20
40
60
LOAD CURRENT (mA)
80
3460 TA01a
Load Step Response
VOUT
100mV/DIV
58mA
ILOAD
34mA
100µs/DIV
3460 TA01b
Input Current and Output Voltage
5V to 12V with Soft-Start Circuit
L1
22µH
VIN
5V
C1
4.7µF
D1
VOUT
12V
70mA
CONTROL
SIGNAL
VIN
47k
SW
SHDN
47nF
130k
FB
GND
C1: TAIYO YUDEN X5R JMK212BJ475
C2: TAIYO YUDEN X5R EMK212BJ105
D1: CENTRAL SEMICONDUCTOR CMDSH2-3
L1: MURATA LQH32CN-220 OR EQUIVALENT
22pF
C2
1µF
16V
LT3460
IIN
100mA/DIV
15k
VO
5V/DIV
CONTROL
SIGNAL
2V/DIV
3460 TA02
500µs/DIV
3460 TA02b
3460f
7
LT3460
U
TYPICAL APPLICATIO S
3.3V to 12V Step-Up Converter
C1
4.7µF
VIN
D1
VOUT
12V
40mA
130k
SW
22pF
C2
1µF
16V
LT3460
SHDN
FB
80
EFFICIENCY (%)
L1
22µH
VIN
3.3V
Efficiency
85
15k
GND
75
70
65
60
C1: TAIYO YUDEN X5R JMK212BJ475
C2: TAIYO YUDEN X5R EMK212BJ105
D1: CENTRAL SEMICONDUCTOR CMDSH2-3
L1: MURATA LQH32CN-220 OR EQUIVALENT
3460 TA03
55
0
20
30
10
LOAD CURRENT (mA)
40
3460 TA03a
Li-Ion to 5V Step-Up Converter
D1
VOUT
5V
88
VIN = 4.2V
86
VIN
SW
39.2k
C2
4.7µF
6.3V
LT3460
4.7µF
SHDN
FB
GND
50pF
13k
EFFICIENCY (%)
+
C1
90
L1
10µH
VIN
2.7V
TO
4.2V
Efficiency
84
VIN = 3.6V
82
VIN = 3V
80
VIN = 2.7V
78
76
74
C1: TAIYO YUDEN X5R JMK212BJ475
C2: TAIYO YUDEN X5R JMK212BJ475
D1: PHILIPS PMEG2010
L1: MURATA LQH32CN-100 OR EQUIVALENT
3460 TA07
72
70
0
50
200
150
100
LOAD CURRENT (mA)
250
3460 TA07a
3460f
8
LT3460
U
TYPICAL APPLICATIO S
12V to 36V Step-Up Converter
L1
47µH
VIN
12V
C1
1µF
16V
D1
Load Step Response
VOUT
36V
4mA
D2
VIN
278k
SW
C2
0.22µF
50V
LT3460
SHDN
VOUT
100mV/DIV
22pF
FB
10k
GND
ILOAD
C1: TAIYO YUDEN X5R EMK212BJ105
C2: TAIYO YUDEN X7R UMK212BJ224
D1, D2: CENTRAL SEMICONDUCTOR CMOD4448
L1: TAIYO YUDEN LB2012
4mA
2mA
3460 TA04
100µs/DIV
3460 TA04a
5V to 36V Step-Up Converter
L1
47µH
VIN
5V
C1
1µF
6.3V
D1
Load Step Response
VOUT
36V
4mA
D2
VIN
SW
278k
C2
0.22µF
50V
LT3460
SHDN
FB
GND
VOUT
100mV/DIV
22pF
10k
ILOAD
C1: TAIYO YUDEN X5R JMK107BJ105
C2: TAIYO YUDEN X7R UMK212BJ224
D1, D2: CENTRAL SEMICONDUCTOR CMOD4448
L1: TAIYO YUDEN LB2012
3460 TA05
4mA
2mA
100µs/DIV
3460 TA05a
3460f
9
LT3460
U
PACKAGE DESCRIPTIO
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1.90 BSC
S5 TSOT-23 0302
3460f
10
LT3460
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PACKAGE DESCRIPTIO
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.16 REF
0.96 MIN
3.26 MAX 2.1 REF
INDEX AREA
(NOTE 6)
1.80 – 2.40 1.15 – 1.35
(NOTE 4)
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.65 BSC
0.15 – 0.30
6 PLCS (NOTE 3)
0.10 – 0.40
0.80 – 1.00
0.00 – 0.10
REF
1.00 MAX
0.10 – 0.30
0.10 – 0.18
(NOTE 3)
SC6 SC70 0802
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 INDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
3460f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT3460
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TYPICAL APPLICATIO S
5V to 5V SEPIC
VIN
3V TO 10V
C1
1µF
VIN
C3
0.22µF
SW
D1
VOUT
5V
50mA
L2
22µH
30k
50pF
LT3460
SHDN
C2
1µF
FB
VIN = 6.5V
75
VIN = 4V
EFFICIENCY (%)
L1
22µH
Efficiency
80
VIN = 5V
70
65
60
10k
GND
55
C1, C2: TAIYO YUDEN X5R LMK107BJ105
C3: TAIYO YUDEN X7R LMK107BJ224
D1: ON SEMICONDUCTOR MBR0520
L1, L2: MURATA LQH32CN-220 OR EQUIVALENT
3460 TA06
50
0
100
50
LOAD CURRENT (mA)
150
3460 TA06a
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VIN: 2.7V to 16V, VOUT(MAX) = 30V, IQ = 1.9mA, ISD <1µA,
ThinSOT Package
3460f
12
Linear Technology Corporation
LT/TP 0204 1K • PRINTED IN USA
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