LT3957A Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch DESCRIPTION FEATURES Wide Input Voltage Range: 3V to 40V n Single Feedback Pin for Positive or Negative Output Voltage n Internal 5A/40V Power Switch n Current Mode Control Provides Excellent Transient Response n Programmable Operating Frequency (100kHz to 1MHz) with One External Resistor n Synchronizable to an External Clock n Low Shutdown Current < 1µA n Internal 5.2V Low Dropout Voltage Regulator n Programmable Input Undervoltage Lockout with Hysteresis n Programmable Soft-Start n Thermally Enhanced QFN (5mm × 6mm) Package The LT®3957A is a wide input range, current mode DC/DC converter which is capable of generating either positive or negative output voltages. It can be configured as either a boost, flyback, SEPIC or inverting converter. It features an internal low side N-channel power MOSFET rated for 40V at 5A and driven from an internal regulated 5.2V supply. The fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. APPLICATIONS The LT3957A features soft-start and frequency foldback functions to limit inductor current during start-up. The LT3957A has improved load transient performance compared to the LT3957. n The operating frequency of LT3957A can be set with an external resistor over a 100kHz to 1MHz range, and can be synchronized to an external clock using the SYNC pin. A minimum operating supply voltage of 3V, and a low shutdown quiescent current of less than 1µA, make the LT3957A ideally suited for battery-powered systems. Automotive Telecom n Industrial n n L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7825665. TYPICAL APPLICATION High Efficiency Output Boost Converter Efficiency vs Output Current VIN 4.5V TO 16V 10µF 200k VIN 10µF ×2 SW GND EN/UVLO 95.3k LT3957A SGND SENSE1 SYNC SENSE2 226k FBX RT 41.2k 300kHz VC SS 0.33µF INTVCC 6.8k 15.8k 4.7µF 22nF VOUT 24V 600mA 100 VIN = 12V 95 EFFICIENCY (%) 10µH 90 85 80 75 70 0 100 600 400 500 200 300 OUTPUT CURRENT (mA) 3957A TA01b 3957A TA01a 3957af 1 LT3957A VC FBX SS RT TOP VIEW SYNC VIN, EN/UVLO (Note 5), SW.......................................40V INTVCC.......................................................VIN + 0.3V, 8V SYNC...........................................................................8V VC, SS..........................................................................3V RT.............................................................................1.5V SENSE1, SGND................... Internally Connected to GND SENSE2...................................................................±0.3V FBX.................................................................. –6V to 6V Operating Junction Temperature Range (Note 2)................................................... –40°C to 125°C Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –65°C to 125°C PIN CONFIGURATION NC (Note 1) NC ABSOLUTE MAXIMUM RATINGS 36 35 34 33 32 31 30 NC 1 28 INTVCC NC 2 27 VIN SENSE2 3 SGND 37 SGND 4 25 EN/UVLO 24 SGND 23 SGND SENSE1 6 SW 38 SW 8 SW 9 21 SW 20 SW NC 10 GND GND GND GND GND GND 12 13 14 15 16 17 UHE PACKAGE 36-LEAD (5mm × 6mm) PLASTIC QFN TJMAX = 125°C, θJA = 42°C/W, θJC = 3°C/W EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3957AEUHE#PBF LT3957AEUHE#TRPBF 3957A 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C LT3957AIUHE#PBF LT3957AIUHE#TRPBF 3957A 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3957af 2 LT3957A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted. PARAMETER CONDITIONS MIN VIN Operating Range TYP 3 MAX UNITS 40 V VIN Shutdown IQ EN/UVLO = 0V EN/UVLO = 1.15V 0.1 1 6 µA µA VIN Operating IQ VC = 0.3V, RT = 41.2k 1.7 2.3 mA VIN Operating IQ with Internal LDO Disabled VC = 0.3V, RT = 41.2k, INTVCC = 5.5V 350 400 µA 5.9 6.8 A SW Pin Current Limit l 5 SW Pin On Voltage ISW = 3A 100 mV SENSE2 Input Bias Current Current Out of Pin –65 µA Error Amplifier FBX Regulation Voltage (VFBX(REG)) FBX > 0V (Note 3) FBX < 0V (Note 3) FBX Overvoltage Lockout FBX > 0V (Note 4) FBX < 0V (Note 4) FBX Pin Input Current FBX = 1.6V (Note 3) FBX = –0.8V (Note 3) l l 1.569 –0.816 1.6 –0.800 1.631 –0.784 V V 6 7 8 11 10 14 % % 70 100 10 nA nA –10 Transconductance gm (∆IVC /∆FBX) (Note 3) 230 µS VC Output Impedance (Note 3) 5 MΩ VFBX Line Regulation (∆VFBX /[∆VIN • VFBX(REG)]) FBX > 0V, 3V < VIN < 40V (Notes 3, 6) FBX < 0V, 3V < VIN < 40V (Notes 3, 6) 0.04 0.03 VC Current Mode Gain (∆VVC /∆VSENSE) 0.06 0.06 %/V %/V 10 V/V VC Source Current VC = 1.5V, FBX = 0V, Current Out of Pin –15 µA VC Sink Current FBX = 1.7V FBX = –0.85V 12 11 µA µA Oscillator Switching Frequency RT = 140k to SGND, FBX = 1.6V, VC = 1.5V RT = 41.2k to SGND, FBX = 1.6V, VC = 1.5V RT = 10.5k to SGND, FBX = 1.6V, VC = 1.5V RT Voltage FBX = 1.6V 80 270 850 100 300 1000 120 330 1200 1.2 kHz kHz kHz V SW Minimum Off-Time 220 275 ns SW Minimum On-Time 240 320 ns SYNC Input Low 0.4 SYNC Input High SS Pull-Up Current 1.5 SS = 0V, Current Out of Pin –10 µA Low Dropout Regulator INTVCC Regulation Voltage INTVCC Undervoltage Lockout Threshold l Falling INTVCC UVLO Hysteresis 5 5.2 5.45 V 2.6 2.7 0.15 2.85 V V 3957af 3 LT3957A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX INTVCC Current Limit VIN = 40V VIN = 15V 32 40 95 55 INTVCC Load Regulation (∆VINTVCC / VINTVCC) 0 < IINTVCC < 20mA, VIN = 8V –1 –0.5 UNITS mA mA % INTVCC Line Regulation (∆VINTVCC / [∆VIN • VINTVCC]) 6V < VIN < 40V 0.02 Dropout Voltage (VIN – VINTVCC) VIN = 5V, IINTVCC = 20mA, VC = 0V 450 mV INTVCC Current in Shutdown EN/UVLO = 0V, INTVCC = 6V 17 µA INTVCC Voltage to Bypass Internal LDO 0.05 %/V 5.5 V Logic Inputs VIN = INTVCC = 6V EN/UVLO Threshold Voltage Falling 1.17 l EN/UVLO Voltage Hysteresis IVIN Drops Below 1µA EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V EN/UVLO Pin Bias Current High EN/UVLO = 1.33V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3957AE is guaranteed to meet performance specifications from the 0°C to 125°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3957AI is guaranteed over the full –40°C to 125°C operating junction temperature range. 1.7 VIN = 40V VIN = 24V VIN = 8V 1590 VIN = INTVCC = 3V, SHDN/UVLO = 1.33V 1580 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3957A G01 Negative Feedback Voltage vs Temperature, VIN –790 1.8 VIN = INTVCC = 3V SHDN/UVLO = 1.33V –792 –794 VIN = 8V –796 –798 –800 VIN = 24V 0.4 V 2 2.5 µA 20 100 nA TA ≈ TJ = 25°C, unless otherwise noted. QUIESCENT CURRENT (mA) –788 REGULATED FEEDBACK VOLTAGE (mV) REGULATED FEEDBACK VOLTAGE (mV) Positive Feedback Voltage vs Temperature, VIN 1585 V mV Note 3: The LT3957A is tested in a feedback loop which servos VFBX to the reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V. Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOLTAGE) relative to regulated VFBX(REG). Note 5: For 3V ≤ VIN < 6V, the EN/UVLO pin must not exceed VIN. Note 6: EN/UVLO = 1.33V when VIN = 3V. TYPICAL PERFORMANCE CHARACTERISTICS 1600 1.27 20 EN/UVLO Input Low Voltage 1605 1.22 VIN = 40V Quiescent Current vs Temperature, VIN 1.7 VIN = 40V VIN = 24V 1.6 VIN = INTVCC = 3V 1.5 –802 –804 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3957A G02 1.4 –50 –25 50 0 25 75 TEMPERATURE (°C) 100 125 3957A G03 3957af 4 LT3957A TYPICAL PERFORMANCE CHARACTERISTICS Dynamic Quiescent Current vs Switching Frequency 1000 12 TA ≈ TJ = 25°C, unless otherwise noted. Normalized Switching Frequency vs FBX RT vs Switching Frequency 120 NORMALIZED FREQUENCY (%) 10 RT (kΩ) IQ(mA) 8 6 100 4 2 10 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) 40 20 310 305 300 295 290 285 0 0.4 0.8 FBX VOLTAGE (V) 1.2 1.6 SW Pin Current Limit vs Duty Cycle 6.6 6.6 6.4 6.4 SW PIN CURRENT LIMIT (A) RT = 41.2k 315 –0.4 3957A G06 SW Pin Current Limit vs Temperature SW PIN CURRENT LIMIT (A) SWITCHING FREQUENCY (kHz) 60 3957A G05 Switching Frequency vs Temperature 320 80 0 –0.8 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) 3957A G04 325 100 6.2 6.0 5.8 5.6 6.2 6.0 5.8 5.6 280 275 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 5.4 –50 125 –25 50 25 0 75 TEMPERATURE (°C) EN/UVLO Threshold vs Temperature 1.24 EN/UVLO FALLING 1.20 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3957A G10 20 40 60 DUTY CYCLE (%) 40 2.4 30 2.2 20 2.0 1.8 10 0 100 80 EN/UVLO Hysteresis Current vs Temperature IEN/UVLO (µA) EN/UVLO CURRENT (µA) EN/UVLO VOLTAGE (V) 1.26 EN/UVLO RISING 0 3957A G09 EN/UVLO Current vs Voltage 1.28 1.18 –50 5.4 125 3957A G08 3957A G07 1.22 100 0 10 20 30 EN/UVLO VOLTAGE (V) 40 3957A G11 1.6 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3957A G12 3957af 5 LT3957A TYPICAL PERFORMANCE CHARACTERISTICS INTVCC vs Temperature INTVCC Minimum Output Current Limit vs VIN 90 5.4 5.1 INTVCC Load Regulation VIN = 6V 5.2 70 INTVCC VOLTAGE (V) INTVCC CURRENT (mA) INTVCC (V) 5.2 5.3 TJ = 125°C INTVCC = 3V 80 5.3 TA ≈ TJ = 25°C, unless otherwise noted. 60 50 40 30 20 5.1 5.0 4.9 10 5.0 –50 50 25 0 75 TEMPERATURE (°C) –25 100 0 125 1 10 VIN (V) INTVCC Dropout Voltage vs Current, Temperature INTVCC Line Regulation 700 5.20 5.15 VIN = 5V 10 15 20 25 VIN (V) 30 35 40 40 75°C 25°C 400 0°C 300 –40°C 200 35 30 25 20 15 10 5 5 0 10 15 20 0 –50 –25 0 25 50 125 SEPIC FBX Frequency Foldback Waveforms During Overcurrent VIN = 12V VIN = 12V VOUT 10V/DIV 28.0 ON-RESISTANCE (mΩ) 100 3957A G18 SEPIC Typical Start-Up Waveforms Internal Switch On-Resistance vs INTVCC 75 TEMPERATURE (°C) INTVCC LOAD (mA) 3957A G16 3957A G17 28.2 60 45 100 5 50 50 125°C 500 0 40 30 20 INTVCC LOAD (mA) Internal Switch On-Resistance vs Temperature ON-RESISTANCE (mΩ) DROPOUT VOLTAGE (mV) INTVCC VOLTAGE (V) 5.25 0 10 3957A G15 600 5.10 0 3957A G14 3957A G13 5.30 4.8 100 27.8 27.6 VOUT 5V/DIV 27.4 27.2 IL1A + IL1B 5A/DIV IL1A + IL1B 2A/DIV 27.0 26.8 26.6 VSW 20V/DIV 5ms/DIV 3 4 5 6 7 8 3957A G20 SEE TYPICAL APPLICATION: 5V TO 16V INPUT, 12V OUTPUT SEPIC CONVERTER 50µs/DIV 3957A G21 SEE TYPICAL APPLICATION: 5V TO 16V INPUT, 12V OUTPUT SEPIC CONVERTER INTVCC (V) 3957A G19 3957af 6 LT3957A PIN FUNCTIONS NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave these pins open or connect them to the adjacent pins. SENSE2 (Pin 3): The Current Sense Input for the Control Loop. Connect this pin to SENSE1 pin directly or through a low pass filter (connect this pin to SENSE1 pin through a resistor, and to SGND through a capacitor). SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal Ground. All small-signal components should connect to this ground. SGND is connected to GND inside the IC to ensure Kelvin connection for the internal switch current sensing. Do not connect SGND and GND externally. SENSE1 (Pin 6): The Current Sense Output of the Internal N-channel MOSFET. Connect this pin to SENSE2 pin directly or through a lowpass filter (connect this pin to SENSE1 pin through a resistor, then connect SENSE2 to SGND through a capacitor). SW (Pins 8, 9, 20, 21, Exposed Pad Pin 38): Drain of Internal Power N-channel MOSFET. GND (Pins 12, 13, 14, 15, 16, 17): Ground. These pins connect to the source terminal of internal power N-channel MOSFET through an internal sense resistor. GND is connected to SGND inside the IC to ensure Kelvin connection for the internal switch current sensing. Do not connect GND and SGND externally. EN/UVLO (Pin 25): Shutdown and Undervoltage Detect Pin. An accurate 1.22V (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2µA pull-down current. An undervoltage condition resets soft-start. Tie to 0.4V, or less, to disable the device and reduce VIN quiescent current below 1µA. VIN (Pin 27): Input Supply Pin. The VIN pin can be locally bypassed with a capacitor to GND (not SGND). INTVCC (Pin 28): Regulated Supply for Internal Loads and Gate Driver. Supplied from VIN and regulated to 5.2V (typical). INTVCC must be bypassed to SGND with a minimum of 4.7µF capacitor placed close to pin. INTVCC can be connected directly to VIN, if VIN is less than 8V. INTVCC can also be connected to a power supply whose voltage is higher than 5.5V, and lower than VIN, provided that supply does not exceed 8V. VC (Pin 30): Error Amplifier Compensation Pin. Used to stabilize the voltage loop with an external RC network. Place compensation components between the VC pin and SGND. FBX (Pin 31): Positive and Negative Feedback Pin. Receives the feedback voltage from the external resistor divider between the output and SGND. Also modulates the switching frequency during start-up and fault conditions when FBX is close to SGND. SS (Pin 32): Soft-Start Pin. This pin modulates compensation pin voltage (VC) clamp. The soft-start interval is set with an external capacitor between SS pin and SGND. The pin has a 10µA (typical) pull-up current source to an internal 2.5V rail. The soft-start pin is reset to SGND by an undervoltage condition at EN/UVLO, an INTVCC undervoltage or overvoltage condition or an internal thermal lockout. RT (Pin 33): Switching Frequency Adjustment Pin. Set the frequency using a resistor to SGND. Do not leave this pin open. SYNC (Pin 34): Frequency Synchronization Pin. Used to synchronize the switching frequency to an outside clock. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than the SYNC pulse frequency. Tie the SYNC pin to SGND if this feature is not used. SYNC is bypassed when FBX is close to SGND. 3957af 7 LT3957A BLOCK DIAGRAM CDC L1 R4 R3 25 A10 IS1 2µA 2.5V IS2 10µA 1.72V –0.88V – + – + –0.8V VIN CURRENT LIMIT M2 5.2V LDO 28 2.7V INTVCC CVCC IS3 A11 TLO 165˚C G6 A12 VC DRIVER SR1 – +A7 G5 R S G2 O + A1 – 6 RSENSE A6 VISENSE SLOPE RAMP + A2 – 1.28V FBX 30 VC 32 SS M1 PWM COMPARATOR RAMP GENERATOR – +A3 + + 34 SYNC – + + A5 – A4 RC CSS 12, 13, 14, 15, 16, 17 3 SENSE2 Q1 FREQ PROG 33 RT SGND 4, 23, 24, 37 R2 CC2 GND 48mV SENSE SENSE1 100kHz-1MHz OSCILLATOR G1 – R1 SW 1.22V A8 1.2V VOUT 27 COUT • 8, 9, 20, 21, 38 UVLO FREQUENCY FOLDBACK 31 – + L2 EN/UVLO G4 Q2 1.6V VOUT CIN INTERNAL REGULATOR AND UVLO Q3 2.5V D1 • VIN 3957A F01 RT CC1 Figure 1. LT3957A Block Diagram Working as a SEPIC Converter 3957af 8 LT3957A APPLICATIONS INFORMATION Main Control Loop The LT3957A uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block Diagram in Figure 1. The start of each oscillator cycle sets the SR latch (SR1) and turns on the internal power MOSFET switch M1 through driver G2. The switch current flows through the internal current sensing resistor RSENSE and generates a voltage proportional to the switch current. This current sense voltage VISENSE (amplified by A5) is added to a stabilizing slope compensation ramp and the resulting sum (SLOPE) is fed into the positive terminal of the PWM comparator A7. When SLOPE exceeds the level at the negative input of A7 (VC pin), SR1 is reset, turning off the power switch. The level at the negative input of A7 is set by the error amplifier A1 (or A2) and is an amplified version of the difference between the feedback voltage (FBX pin) and the reference voltage (1.6V or –0.8V, depending on the configuration). In this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. The LT3957A has a switch current limit function. The current sense voltage is input to the current limit comparator A6. If the SENSE2 pin voltage is higher than the sense current limit threshold VSENSE(MAX) (48mV, typical), A6 will reset SR1 and turn off M1 immediately. The LT3957A is capable of generating either positive or negative output voltage with a single FBX pin. It can be configured as a boost, flyback or SEPIC converter to generate positive output voltage, or as an inverting converter to generate negative output voltage. When configured as a SEPIC converter, as shown in Figure 1, the FBX pin is pulled up to the internal bias voltage of 1.6V by a voltage divider (R1 and R2) connected from VOUT to SGND. Comparator A2 becomes inactive and comparator A1 performs the inverting amplification from FBX to VC. When the LT3957A is in an inverting configuration, the FBX pin is pulled down to –0.8V by a voltage divider connected from VOUT to SGND. Comparator A1 becomes inactive and comparator A2 performs the noninverting amplification from FBX to VC. The LT3957A has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. An overvoltage comparator A11 (with 20mV hysteresis) senses when the FBX pin voltage exceeds the positive regulated voltage (1.6V) by 8% and provides a reset pulse. Similarly, an overvoltage comparator A12 (with 10mV hysteresis) senses when the FBX pin voltage exceeds the negative regulated voltage (–0.8V) by 11% and provides a reset pulse. Both reset pulses are sent to the main RS latch (SR1) through G6 and G5. The power MOSFET switch M1 is actively held off for the duration of an output overvoltage condition. Programming Turn-On and Turn-Off Thresholds with the EN/UVLO Pin The EN/UVLO pin controls whether the LT3957A is enabled or is in shutdown state. A micropower 1.22V reference, a comparator A10 and a controllable current source IS1 allow the user to accurately program the supply voltage at which the IC turns on and off. The falling value can be accurately set by the resistor dividers R3 and R4. When EN/UVLO is above 0.4V, and below the 1.22V threshold, the small pull-down current source IS1 (typical 2µA) is active. The purpose of this current is to allow the user to program the rising hysteresis. The Block Diagram of the comparator and the external resistors is shown in Figure 1. The typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: (R3 + R4) R4 VVIN,RISING = 2µA • R3 + VIN,FALLING VVIN,FALLING = 1.22 • For applications where the EN/UVLO pin is only used as a logic input, the EN/UVLO pin can be connected directly to the input voltage VIN for always-on operation. 3957af 9 LT3957A APPLICATIONS INFORMATION INTVCC Regulator Bypassing and Operation An internal, low dropout (LDO) voltage regulator produces the 5.2V INTVCC supply which powers the gate driver, as shown in Figure 1. The LT3957A contains an undervoltage lockout comparator A8 for the INTVCC supply. The INTVCC undervoltage (UV) threshold is 2.7V (typical), with 0.1V hysteresis, to ensure that the internal MOSFET has sufficient gate drive voltage before turning on. When INTVCC is below the UV threshold, the internal power switch will be turned off and the soft-start operation will be triggered. The logic circuitry within the LT3957A is also powered from the internal INTVCC supply. The INTVCC regulator must be bypassed to SGND immediately adjacent to the IC pins with a minimum of 4.7µF ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. In an actual application, most of the IC supply current is used to drive the gate capacitance of the internal power MOSFET. The on-chip power dissipation can be significant when the internal power MOSFET is being driven at a high frequency and the VIN voltage is high. An effective approach to reduce the power consumption of the internal LDO for gate drive and to improve the efficiency is to tie the INTVCC pin to an external voltage source high enough to turn off the internal LDO regulator. In SEPIC or flyback applications, the INTVCC pin can be connected to the output voltage VOUT through a blocking diode, as shown in Figure 2, if VOUT meets the following conditions: 1. VOUT < VIN (pin voltage) 2. VOUT < 8V A resistor RVCC can be connected, as shown in Figure 2, to limit the inrush current from VOUT. Regardless of whether or not the INTVCC pin is connected to an external voltage source, it is always necessary to have the driver circuitry bypassed with a 4.7µF low ESR ceramic capacitor to ground immediately adjacent to the INTVCC and SGND pins. If LT3957A operates at a low VIN and high switching frequency, the voltage drop across the drain and the source of the LDO PMOS (M2 in Figure 1) could push INTVCC to be below the UV threshold. To prevent this from happening, the INTVCC pin can be shorted directly to the VIN pin. VIN must not exceed the INTVCC Absolute Maximum Rating (8V). In this condition, the internal LDO will be turned off and the gate driver will be powered directly from VIN. It is recommended that INTVCC pin be shorted to the VIN pin if VIN is lower than 3.5V at 1MHz switching frequency, or VIN is lower than 3.2V at 100kHz switching frequency. With the INTVCC pin shorted to VIN, however, a small current (around 16µA) will load the INTVCC in shutdown mode. DVCC INTVCC LT3957A RVCC VOUT CVCC 4.7µF SGND 3957A F02 Figure 2. Connecting INTVCC to VOUT 3957af 10 LT3957A APPLICATIONS INFORMATION Operating Frequency and Synchronization Duty Cycle Consideration The choice of operating frequency may be determined by on-chip power dissipation (a low switching frequency may be required to ensure IC junction temperature does not exceed 125°C), otherwise it is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing gate drive current and MOSFET and diode switching losses. However, lower frequency operation requires a physically larger inductor. Switching frequency also has implications for loop compensation. The LT3957A uses a constant-frequency architecture that can be programmed over a 100kHz to 1000kHz range with a single external resistor from the RT pin to SGND, as shown in Figure 1. A table for selecting the value of RT for a given operating frequency is shown in Table 1. Switching duty cycle is a key variable defining converter operation. As such, its limits must be considered. Minimum on-time is the smallest time duration that the LT3957A is capable of turning on the power MOSFET. This time is typically about 240ns (see Minimum On-Time in the Electrical Characteristics table). In each switching cycle, the LT3957A keeps the power switch off for at least 220ns (typical) (see Minimum Off-Time in the Electrical Characteristics table). Table 1. Timing Resistor (RT ) Value SWITCHING FREQUENCY (kHz) RT (kΩ) 100 140 200 63.4 300 41.2 400 30.9 500 24.3 600 19.6 700 16.5 800 14 900 12.1 1000 10.5 The operating frequency of the LT3957A can be synchronized to an external clock source. By providing a digital clock signal into the SYNC pin, the LT3957A will operate at the SYNC clock frequency. The LT3957A detects the rising edge of each clock cycle. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than SYNC pulse frequency. It is recommended that the SYNC pin has a minimum pulse width of 200ns. Tie the SYNC pin to SGND if this feature is not used. The minimum on-time, minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: Minimum duty cycle = minimum on-time • frequency Maximum duty cycle = 1 – (minimum off-time • frequency) Programming the Output Voltage The output voltage VOUT is set by a resistor divider, as shown in Figure 1. The positive and negative VOUT are set by the following equations: R2 VOUT,POSITIVE = 1.6V • 1+ R1 R2 VOUT,NEGATIVE = –0.8V • 1+ R1 The resistors R1 and R2 are typically chosen so that the error caused by the current flowing into the FBX pin during normal operation is less than 1% (this translates to a maximum value of R1 at about 158k). 3957af 11 LT3957A APPLICATIONS INFORMATION Soft-Start The LT3957A contains several features to limit peak switch currents and output voltage (VOUT) overshoot during start-up or recovery from a fault condition. The primary purpose of these features is to prevent damage to external components or the load. High peak switch currents during start-up may occur in switching regulators. Since VOUT is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. A large surge current may cause inductor saturation or power switch failure. The LT3957A addresses this mechanism with the SS pin. As shown in Figure 1, the SS pin reduces the power MOSFET current by pulling down the VC pin through Q2. In this way the SS allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. The typical start-up waveforms are shown in the Typical Performance Characteristics section. The inductor current IL slewing rate is limited by the soft-start function. Besides start-up (with EN/UVLO), soft-start can also be triggered by the following faults: 1. INTVCC < 2.85V 2. Thermal lockout (TLO > 165°C) Any of these three faults will cause the LT3957A to stop switching immediately. The SS pin will be discharged by Q3. When all faults are cleared and the SS pin has been discharged below 0.2V, a 10µA current source IS2 starts charging the SS pin, initiating a soft-start operation. The soft-start interval is set by the soft-start capacitor selection according to the equation: TSS = CSS • 1.25V 10µA FBX Frequency Foldback When VOUT is very low during start-up, or an output shortcircuit on a SEPIC, an inverting, or a flyback converter, the switching regulator must operate at low duty cycles to keep the power switch current below the current limit, since the inductor current decay rate is very low during switch off time. The minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. So, the switch current may keep increasing through each switch cycle, exceeding the programmed current limit. To prevent the switch peak currents from exceeding the programmed value, the LT3957A contains a frequency foldback function to reduce the switching frequency when the FBX voltage is low (see the Normalized Switching Frequency vs FBX graph in the Typical Performance Characteristics section). During frequency foldback, external clock synchronization is disabled to prevent interference with frequency reducing operation. Loop Compensation Loop compensation determines the stability and transient performance. The LT3957A uses current mode control to regulate the output which simplifies loop compensation. The LT3957A improves the no-load to heavy load transient response, compared to the LT3957. New internal circuits ensure that the transition from not switching to switching at high current can be made in a few cycles. The optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). To compensate the feedback loop of the LT3957A, a series resistor-capacitor network is usually connected from the VC pin to SGND. Figure 1 shows the typical VC compensation network. For most applications, the capacitor should be in the range of 470pF to 22nF, and the resistor should be in the range of 5k to 50k. A small capacitor is often connected in parallel with the RC compensation network to attenuate the VC voltage ripple induced from the output voltage ripple through the internal error amplifier. The parallel capacitor usually ranges in value from 10pF to 100pF. A practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. Application Note 76 is a good reference on loop compensation. 3957af 12 LT3957A APPLICATIONS INFORMATION The Internal Power Switch Current On-Chip Power Dissipation and Thermal Lockout (TLO) For control and protection, the LT3957A measures the internal power MOSFET current by using a sense resistor (RSENSE) between GND and the MOSFET source. Figure 3 shows a typical waveform of the internal switch current (ISW). The on-chip power dissipation of LT3957A can be estimated using the following equation: Due to the current limit (minimum 5A) of the internal power switch, the LT3957A should be used in the applications that the switch peak current ISW(PEAK) during steady state normal operation is lower than 5A by a sufficient margin (10% or higher is recommended). The LT3957A switching controller incorporates 100ns timing interval to blank the ringing on the current sense signal across RSENSE immediately after M1 is turned on. This ringing is caused by the parasitic inductance and capacitance of the PCB trace, the sense resistor, the diode, and the MOSFET. The 100ns timing interval is adequate for most of the LT3957A applications. In the applications that have very large and long ringing on the current sense signal, a small RC filter can be added to filter out the excess ringing. Figure 4 shows the RC filter on the SENSE1 and SENSE2 pins. It is usually sufficient to choose 22Ω for RFLT and 2.2nF to 10nF for CFLT. Keep RFLT’s resistance low. Remember that there is 65µA (typical) flowing out of the SENSE2 pin. Adding RFLT will affect the internal power switch current limit threshold: PIC ≈ I2SW • D • RDS(ON) + V2PEAK • ISW • ƒ • 200pF/A + VIN • (1.6mA + ƒ • 10nC) where RDS(ON) is the internal switch on-resistance which can be obtained from the Typical Performance Characteristics section. VSW(PEAK) is the peak switch off-state voltage. The maximum power dissipation PIC(MAX) can be obtained by comparing PIC across all the VIN range at the maximum output current . The highest junction temperature can be estimated using the following equation: TJ(MAX) ≈ TA + PIC(MAX) • 42°C/W It is recommended to measure the IC temperature in steady state to verify that the junction temperature limit is not exceeded. A low switching frequency may be required to ensure TJ(MAX) does not exceed 125°C. If LT3957A die temperature reaches thermal lockout threshold at 165°C (typical), the IC will initiate several protective actions. The power switch will be turned off. A soft-start operation will be triggered. The IC will be enabled again when the junction temperature has dropped by 5°C (nominal). LT3957A SENSE1 65µA • RFLT ISW _ILIM = 1− • 5A 48mV RFLT SENSE2 CFLT SGND ISW 3957A F04 ∆ISW Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin ISW(PEAK) t DTS TS 3957A F03 Figure 3. The Switch Current During a Switching Cycle 3957af 13 LT3957A APPLICATIONS INFORMATION APPLICATION CIRCUITS The LT3957A can be configured as different topologies. The first topology to be analyzed will be the boost converter, followed by the flyback, SEPIC and inverting converters. Due to the current limit of its internal power switch, the LT3957A should be used in a boost converter whose maximum output current (IO(MAX)) is less than the maximum output current capability by a sufficient margin (10% or higher is recommended): Boost Converter: Switch Duty Cycle and Frequency The LT3957A can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. Remember that boost converters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability. For applications requiring a step-up converter that is short-circuit protected, please refer to the Applications Information section covering SEPIC converters. The conversion ratio as a function of duty cycle is VOUT 1 = VIN 1− D in continuous conduction mode (CCM). For a boost converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT) and the input voltage (VIN). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: DMAX = VOUT − VIN(MIN) VOUT Discontinuous conduction mode (DCM) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents. Boost Converter: Maximum Output Current Capability and Inductor Selection For the boost topology, the maximum average inductor current is: I L(MAX) = IO(MAX) • 1 1− DMAX I O(MAX) < VIN(MIN) VOUT • ( 5A − 0.5 • ∆ISW ) The inductor ripple current ∆ISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of ∆ISW increases output current capability, but requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ∆ISW provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses, and reduces output current capability. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: L= VIN(MIN) ∆ISW • ƒ • DMAX The peak inductor current is the switch current limit (5.9A typical), and the RMS inductor current is approximately equal to IL(MAX). The user should choose the inductors having sufficient saturation and RMS current ratings. Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. The average forward current in normal operation is equal to the output current. It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT by a safety margin (a 10V safety margin is usually sufficient). 3957af 14 LT3957A APPLICATIONS INFORMATION The power dissipated by the diode is: tON PD = IO(MAX) • VD ∆VCOUT VOUT (AC) where VD is diode’s forward voltage drop, and the diode junction temperature is: ∆VESR TJ = TA + PD • RθJA The RθJA to be used in this equation normally includes the RθJC for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Boost Converter: Output Capacitor Selection Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. The effect of these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform for a typical boost converter is illustrated in Figure 5. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step ∆VESR and the charging/discharging ∆VCOUT. For the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ∆VESR and ∆VCOUT. This percentage ripple will change, depending on the requirements of the application, and the following equations can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: ESRCOUT ≤ 0.01• VOUT ID(PEAK) For the bulk C component, which also contributes 1% to the total ripple: COUT ≥ tOFF RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 3957A F05 Figure 5. The Output Ripple Waveform of a Boost Converter The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 5. The RMS ripple current rating of the output capacitor can be determined using the following equation: IRMS(COUT) ≥IO(MAX) • DMAX 1− DMAX Multiple capacitors are often paralleled to meet ESR requirements. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the required RMS current rating. Additional ceramic capacitors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current waveform is continuous. The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 1µF to 100µF. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: IRMS(CIN) = 0.3 • ∆IL IO(MAX) 0.01• VOUT • ƒ 3957af 15 LT3957A APPLICATIONS INFORMATION FLYBACK CONVERTER APPLICATIONS The LT3957A can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. Due to the 40V rating of the internal power switch, LT3957A should be used in low input voltage flyback converters. Figure 6 shows a simplified flyback converter. Figure 7 shows the waveforms of the flyback converter in discontinuous mode operation. During each switching period TS, three subintervals occur: DTS, D2TS, D3TS. During DTS, M is on, and D is reverse-biased. During D2TS, M is off, and LS is conducting current. Both LP and LS currents are zero during D3TS. The flyback converter has a very low parts count for multiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. However, it has low efficiency due to the high peak currents, high peak voltages and consequent power loss. The flyback converter is commonly used for an output power of less than 50W. VSW ISW ISW(MAX) The flyback converter can be designed to operate either in continuous or discontinuous mode. Compared to continuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compensation, and the disadvantage of higher peak-to-average current and lower efficiency. SUGGESTED RCD SNUBBER VIN + CIN – VSN + CSN LP ID(MAX) DTS LS ID COUT DSN + + VOUT – 3957A F07 The flyback converter conversion ratio in the discontinuous mode operation is: SW VOUT NS D = • VIN NP D2 According to Figure 6, the peak SW voltage is: LT3957A 3957A F06 Figure 6. A Simplified Flyback Converter Flyback Converter: Switch Duty Cycle and Turns Ratio The flyback converter conversion ratio in the continuous mode operation is: t D3TS Figure 7. Waveforms of the Flyback Converter in Discontinuous Mode Operation ISW GND D2TS TS D NP:NS RSN ID VOUT NS D = • VIN NP 1− D VSW(PEAK) = VIN(MAX) + VSN where VSN is the snubber capacitor voltage. A smaller VSN results in a larger snubber loss. A reasonable VSN is 1.5 to 2 times of the reflected output voltage: VSN = k • VOUT • NP NS k = 1.5 ~ 2 where NS/NP is the second to primary turns ratio. D is duty cycle. 3957af 16 LT3957A APPLICATIONS INFORMATION According to the Absolute Maximum Ratings table, the SW voltage Absolute Maximum value is 40V. Therefore, the maximum primary to secondary turns ratio (for both the continuous and the discontinuous operation) should be. maximum output current capability by a sufficient margin (10% or higher is recommended): NP 40V − VIN(MAX) ≤ k • VOUT NS According to the preceding equations, the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. The selections of the duty cycle and the turns ratio are somewhat iterative processes, due to the number of variables involved. The user can choose either a duty cycle or a turns ratio as the start point. The following trade-offs should be considered when selecting the switch duty cycle or turns ratio, to optimize the converter performance. A higher duty cycle affects the flyback converter in the following aspects: • Lower MOSFET RMS current ISW(RMS), but higher MOSFET VSW peak voltage • Lower diode peak reverse voltage, but higher diode RMS current ID(RMS) IO(MAX) < VIN(MIN) VOUT • DMAX • ( 5A − 0.5 • ∆ISW ) The transformer ripple current ∆ISW has a direct effect on the design/choice of the transformer and the converter’s output current capability. Choosing smaller values of ∆ISW increases the output current capability, but requires large primary and secondary inductances and reduce the current loop gain (the converter will approach voltage mode). Accepting larger values of ∆ISW allows the use of low primary and secondary inductances, but results in higher input current ripple, greater core losses, and reduces the output current capability. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the primary winding, the primary winding inductance can be calculated using the following equation: L= VIN(MIN) ∆ISW • ƒ • DMAX • Higher transformer turns ratio (NP/NS) It is recommended to choose a duty cycle between 20% and 80%. The primary winding peak current is the switch current limit (typical 5.9A). The primary and secondary maximum RMS currents are: Flyback Converter: Maximum Output Current Capability and Transformer Design The maximum output current capability and transformer design for continuous conduction mode (CCM) is chosen as presented here. The maximum duty cycle (DMAX) occurs when the converter has the minimum VIN: VOUT DMAX = N • P N S N VOUT • P + VIN(MIN) NS Due to the current limit of its internal power switch, the LT3957A should be used in a flyback converter whose maximum output current (IO(MAX)) is less than the ILP(RMS) ≈ ILS(RMS) ≈ POUT(MAX) DMAX • VIN(MIN) • η I OUT(MAX) 1− DMAX where η is the converter efficiency. Based on the preceding equations, the user should design/ choose the transformer having sufficient saturation and RMS current ratings. Flyback Converter: Snubber Design Transformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the MOSFET turn-off. This is increasingly prominent at higher 3957af 17 LT3957A APPLICATIONS INFORMATION load currents, where more stored energy must be dissipated. In some cases a snubber circuit will be required to avoid overvoltage breakdown at the MOSFET’s drain node. There are different snubber circuits (such as RC snubber, RCD snubber, Zener clamp, etc.), and Application Note 19 is a good reference on snubber design. An RC snubber circuit can be connected between SW and GND to damp the ringing on SW pins. The snubber resistor values should be close to the impedance of the parasitic resonance. The snubber capacitor value should be larger than the circuit parasitic capacitance, but be small enough to keep the snubber resistor power dissipation low. If the RC snubber is insufficient to prevent SW pins overvoltage, the RCD snubber can be used to limit the peak voltage on the SW pins, which is shown in Figure 6. The snubber resistor value (RSN) can be calculated by the following equation: RSN = 2 • V 2 SN − VSN • VOUT • NP NS I2 SW(PEAK) • L LK • ƒ LLK is the leakage inductance of the primary winding, which is usually specified in the transformer characteristics. LLK can be obtained by measuring the primary inductance with the secondary windings shorted. The snubber capacitor value (CSN) can be determined using the following equation: VSN CCN = ∆VSN • RSN • ƒ where ∆VSN is the voltage ripple across CSN. A reasonable ∆VSN is 5% to 10% of VSN. The reverse voltage rating of DSN should be higher than the sum of VSN and VIN(MAX). A Zener clamp can also be connected between SW and GND to ensure SW voltage does not exceed 40V. Flyback Converter: Output Diode Selection The output diode in a flyback converter is subject to large RMS current and peak reverse voltage stresses. A fast switching diode with a low forward drop and a low reverse leakage is desired. Schottky diodes are recommended if the output voltage is below 100V. Approximate the required peak repetitive reverse voltage rating VRRM using: VRRM > NS •V +V NP IN(MAX) OUT The power dissipated by the diode is: PD = IO(MAX) • VD and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA to be used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. Flyback Converter: Output Capacitor Selection The output capacitor of the flyback converter has a similar operation condition as that of the boost converter. Refer to the Boost Converter: Output Capacitor Selection section for the calculation of COUT and ESRCOUT. The RMS ripple current rating of the output capacitors in continuous operation can be determined using the following equation: IRMS(COUT),CONTINUOUS ≈ IO(MAX) • DMAX 1− DMAX Flyback Converter: Input Capacitor Selection The input capacitor in a flyback converter is subject to a large RMS current due to the discontinuous primary current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current. The RMS ripple current rating of the input capacitors in continuous operation can be determined using the following equation: POUT(MAX) 1− DMAX I ≈ • RMS(CIN),CONTINUOUS VIN(MIN) • η DMAX 3957af 18 LT3957A APPLICATIONS INFORMATION SEPIC CONVERTER APPLICATIONS The LT3957A can be configured as a SEPIC (single-ended primary inductance converter), as shown in Figure 1. This topology allows for the input to be higher, equal, or lower than the desired output voltage. The conversion ratio as a function of duty cycle is: For the SEPIC topology, the current through L1 is the converter input current. Based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of L1 and L2 are: VOUT + VD D = VIN 1− D in continuous conduction mode (CCM). In a SEPIC converter, no DC path exists between the input and output. This is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. Compared to the flyback converter, the SEPIC converter has the advantage that both the power MOSFET and the output diode voltages are clamped by the capacitors (CIN, CDC and COUT), therefore, there is less voltage ringing across the power MOSFET and the output diodes. The SEPIC converter requires much smaller input capacitors than those of the flyback converter. This is due to the fact that, in the SEPIC converter, the current through inductor L1 (which is series with the input) is continuous. SEPIC Converter: Switch Duty Cycle and Frequency For a SEPIC converter operating in CCM, the duty cycle of the main switch can be calculated based on the output voltage (VOUT), the input voltage (VIN) and the diode forward voltage (VD). The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: also be wound on the same core, since identical voltages are applied to L1 and L2 throughout the switching cycle. DMAX = VOUT + VD VIN(MIN) + VOUT + VD SEPIC Converter: The Maximum Output Current Capability and Inductor Selection As shown in Figure 1, the SEPIC converter contains two inductors: L1 and L2. L1 and L2 can be independent, but can I L1(MAX) = IIN(MAX) = I O(MAX) • DMAX 1− DMAX I L2(MAX) = I O(MAX) Due to the current limit of its internal power switch, the LT3957A should be used in a SEPIC converter whose maximum output current (IO(MAX)) is less than the output current capability by a sufficient margin (10% or higher is recommended): IO(MAX) < (1− DMAX ) • ( 5A − 0.5 • ∆ISW ) The inductor ripple currents ∆IL1 and ∆IL2 are identical: ∆IL1 = ∆IL2 = 0.5 • ∆ISW The inductor ripple current ∆ISW has a direct effect on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of ∆ISW requires large inductances and reduces the current loop gain (the converter will approach voltage mode). Accepting larger values of ∆ISW allows the use of low inductances, but results in higher input current ripple and greater core losses and reduces output current capability. Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value (L1 and L2 are independent) of the SEPIC converter can be determined using the following equation: L1 = L2 = VIN(MIN) 0.5 • ∆ISW • ƒ • DMAX For most SEPIC applications, the equal inductor values will fall in the range of 1µH to 100µH. 3957af 19 LT3957A APPLICATIONS INFORMATION By making L1 = L2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2L, due to mutual inductance: L= VIN(MIN) ∆ISW • ƒ • DMAX This maintains the same ripple current and energy storage in the inductors. The peak inductor currents are: IL1(PEAK) = IL1(MAX) + 0.5 • ∆IL1 IL2(PEAK) = IL2(MAX) + 0.5 • ∆IL2 The maximum RMS inductor currents are approximately equal to the maximum average inductor currents. Based on the preceding equations, the user should choose the inductors having sufficient saturation and RMS current ratings. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. The average forward current in normal operation is equal to the output current. It is recommended that the peak repetitive reverse voltage rating VRRM is higher than VOUT + VIN(MAX) by a safety margin (a 10V safety margin is usually sufficient). The power dissipated by the diode is: PD = IO(MAX) • VD where VD is diode’s forward voltage drop, and the diode junction temperature is: TJ = TA + PD • RθJA The RθJA used in this equation normally includes the RθJC for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. TJ must not exceed the diode maximum junction temperature rating. SEPIC Converter: Output and Input Capacitor Selection The selections of the output and input capacitors of the SEPIC converter are similar to those of the boost converter. Please refer to the Boost Converter: Output Capacitor Selection and Boost Converter: Input Capacitor Selection sections. SEPIC Converter: Selecting the DC Coupling Capacitor The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 1) should be larger than the maximum input voltage: VCDC > VIN(MAX) CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: VOUT + VD VIN(MIN) IRMS(CDC) >IO(MAX) • A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. INVERTING CONVERTER APPLICATIONS The LT3957A can be configured as a dual-inductor inverting topology, as shown in Figure 8. The VOUT to VIN ratio is: VOUT − VD D =− VIN 1− D in continuous conduction mode (CCM). CDC L1 VIN + + CIN SW LT3957A GND L2 – – COUT D1 VOUT + + 3757A F08 Figure 8. A Simplified Inverting Converter 3957af 20 LT3957A APPLICATIONS INFORMATION Inverting Converter: Switch Duty Cycle and Frequency Inverting Converter: Selecting the DC Coupling Capacitor For an inverting converter operating in CCM, the duty cycle of the main switch can be calculated based on the negative output voltage (VOUT) and the input voltage (VIN). The DC voltage rating of the DC coupling capacitor (CDC, as shown in Figure 10) should be larger than the maximum input voltage minus the output voltage (negative voltage): The maximum duty cycle (DMAX) occurs when the converter has the minimum input voltage: VCDC > VIN(MAX) – VOUT VOUT − VD DMAX = VOUT − VD − VIN(MIN) Inverting Converter: Output Diode and Input Capacitor Selections CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IIN, while approximately –IO flows during the on-time. The RMS rating of the coupling capacitor is determined by the following equation: IRMS(CDC) >IO(MAX) • DMAX 1− DMAX The selections of the inductor, output diode and input capacitor of an inverting converter are similar to those of the SEPIC converter. Please refer to the corresponding SEPIC converter sections. A low ESR and ESL, X5R or X7R ceramic capacitor works well for CDC. Inverting Converter: Output Capacitor Selection Board Layout The inverting converter requires much smaller output capacitors than those of the boost, flyback and SEPIC converters for similar output ripples. This is due to the fact that, in the inverting converter, the inductor L2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. The output ripple voltage is produced by the ripple current of L2 flowing through the ESR and bulk capacitance of the output capacitor: The high power and high speed operation of the LT3957A demands careful attention to board layout and component placement. Careful attention must be paid to the internal power dissipation of the LT3957A at high input voltages, high switching frequencies, and high internal power switch currents to ensure that a junction temperature of 125°C is not exceeded. This is especially important when operating at high ambient temperatures. Exposed pads on the bottom of the package are SGND and SW terminals of the IC, and must be soldered to a SGND ground plane and a SW plane respectively. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into the copper planes with as much area as possible. 1 ∆VOUT(P – P) = ∆IL2 • ESRCOUT + 8 • ƒ • COUT After specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. The ESR can be minimized by using high quality X5R or X7R dielectric ceramic capacitors. In many applications, ceramic capacitors are sufficient to limit the output voltage ripple. The RMS ripple current rating of the output capacitor needs to be greater than: IRMS(COUT) > 0.3 • ∆IL2 To prevent radiation and high frequency resonance problems, proper layout of the components connected to the IC is essential, especially the power paths with higher di/ dt. The following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: • In boost configuration, the high di/dt loop contains the output capacitor, the internal power MOSFET and the Schottky diode. 3957af 21 LT3957A APPLICATIONS INFORMATION • In flyback configuration, the high di/dt primary loop contains the input capacitor, the primary winding, the internal power MOSFET. The high di/dt secondary loop contains the output capacitor, the secondary winding and the output diode. • In SEPIC configuration, the high di/dt loop contains the internal power MOSFET, output capacitor, Schottky diode and the coupling capacitor. • In inverting configuration, the high di/dt loop contains internal power MOSFET, Schottky diode and the coupling capacitor. Check the stress on the internal power MOSFET by measuring the SW-to-GND voltage directly across the IC terminals. Make sure the inductive ringing does not exceed the maximum rating of the internal power MOSFET (40V). The small-signal components should be placed away from high frequency switching nodes. For optimum load regulation and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LT3957A in order to keep the high impedance FBX node short. Figure 9 shows the suggested layout of the 4.5V to16V input, 24V output boost converter in the Typical Application section. R1 VIA TO VOUT R2 CSS RT RC CC 36 35 34 33 32 31 30 1 28 2 27 3 R3 37 4 25 24 6 CVCC LT3957A R4 23 38 8 21 9 20 10 12 13 14 15 16 17 L1 COUT COUT D1 CIN GND VOUT VIN VIA TO VOUT 3958A F09 VIAS TO SGND GROUND PLANE VIAS TO SW PLANE Figure 9. Suggested Layout of the 4.5V to 16V Input. 24V Output Boost Converter in the Typical Application Section 3957af 22 LT3957A APPLICATIONS INFORMATION Recommended Component Manufacturers Some of the recommended component manufacturers are listed in Table 2. Table 2. Recommended Component Manufacturers VENDOR COMPONENTS WEB ADDRESS Capacitors avx.com Inductors, Transformers bhelectronics.com Coilcraft Inductors coilcraft.com Cooper Bussmann AVX BH Electronics Inductors bussmann.com Diodes, Inc Diodes diodes.com General Semiconductor Diodes generalsemiconductor. com International Rectifier Diodes irf.com Kemet Tantalum Capacitors kemet.com Toroid Cores mag-inc.com Microsemi Diodes microsemi.com Murata-Erie Inductors, Capacitors murata.co.jp Capacitors nichicon.com Magnetics Inc Nichicon On Semiconductor Diodes onsemi.com Panasonic Capacitors panasonic.com Pulse Inductors pulseeng.com Sanyo Capacitors sanyo.co.jp Sumida Inductors sumida.com Taiyo Yuden Capacitors t-yuden.com Capacitors, Inductors component.tdk.com Thermalloy Heat Sinks aavidthermalloy.com Tokin Capacitors nec-tokinamerica.com Toko Inductors tokoam.com United Chemi-Con Capacitors chemi-com.com Vishay Inductors vishay.com Würth Elektronik Inductors we-online.com Capacitors vishay.com Small-Signal Discretes zetex.com TDK Vishay/Sprague Zetex 3957af 23 LT3957A TYPICAL APPLICATIONS 4.5V to 16V Input, 24V Output Boost Converter VIN 4.5V TO 16V L1 10µH CIN 10µF 25V X5R R3 200k VIN D1 GND EN/UVLO R4 95.3k COUT 10µF 50V X5R ×2 SW VOUT 24V 600mA LT3957A SGND SENSE1 SYNC SENSE2 R2 226k FBX RT RT 41.2k 300kHz SS VC CSS 0.33µF INTVCC RC 6.8k CC 22nF CVCC 4.7µF 10V X5R R1 15.8k 3957A TA02a CIN: MURATA GRM31ER61H106KA12 COUT: TAIYO YUDEN UMK325BJ106MM D1: VISHAY SILICONIX 10BQ040 L1: VISHAY SILICONIX IHLP-5050CE-1 Efficiency vs Output Current 100 VIN = 12V EFFICIENCY (%) 95 90 85 80 75 70 0 100 600 400 500 200 300 OUTPUT CURRENT (mA) 3957A TA02b 3957af 24 LT3957A TYPICAL APPLICATIONS 5V to 16V Input, 12V Output SEPIC Converter L1A D1 VOUT 12V COUT 1A 22µF 16V X5R ×2 • VIN 5V TO 16V CDC 4.7µF, 25V X5R CIN 4.7µF 25V X5R VIN 200k SW GND EN/UVLO 82.5k • L1B LT3957A SGND SENSE1 SYNC SENSE2 105k FBX RT 41.2k 300kHz INTVCC VC SS 0.47µF 10k 10nF 15.8k CVCC 4.7µF 10V X5R 3957A TA03a CIN, CDC: MURATA GRM21BR61E475KA12L COUT: MURATA GRM32ER61C226KE20 D1: VISHAY SILICONIX 30BQ040 L1A, L1B: COILTRONICS DRQ127-100 Efficiency vs Output Current 100 Load Step Waveforms VIN = 12V VIN = 12V 95 EFFICIENCY (%) 90 VOUT 1V/DIV (AC) 85 80 75 1A IOUT 0.5A/DIV 70 65 0A 60 2ms/DIV 55 50 0 800 200 400 600 OUTPUT CURRENT (mA) 3957 TA03c 1000 3957A TA03b Frequency Foldback Waveforms When Output Short-Circuit Start-Up Waveforms VIN = 12V VIN = 12V VOUT 10V/DIV VOUT 5V/DIV VSW 20V/DIV IL1A + IL1B 5A/DIV IL1A + IL1B 2A/DIV 5ms/DIV 3957A TA03d 50µs/DIV 3957A TA03e 3957af 25 LT3957A TYPICAL APPLICATIONS 5V to 16V Input, –12V Output Inverting Converter CDC 4.7µF, 50V X7R • L1B CIN 4.7µF 25V X5R VIN 200k D1 SW GND EN/UVLO 82.5k VOUT –12V COUT 1A 22µF 16V X5R ×2 • L1A VIN 5V TO 16V LT3957A SGND SENSE1 SYNC SENSE2 105k FBX RT 41.2k 300kHz INTVCC VC SS 0.47µF 7.5k CVCC 4.7µF 10V X5R 10k 10nF 395A7 TA04a CIN: MURATA GRM21BR61E475KA12L CDC: TAIYO YUDEN UMK316BJ475KL COUT: MURATA GRM32ER61C226KE20 D1: VISHAY SILICONIX 30BQ040 L1A, L1B: COILTRONICS DRQ127-100 Efficiency vs Output Current 100 Load Step Waveforms VIN = 12V VIN = 12V 95 VOUT 1V/DIV (AC) EFFICIENCY (%) 90 85 80 0.6A 75 70 IOUT 0.2A/DIV 65 0A 60 2ms/DIV 55 50 0 800 200 400 600 OUTPUT CURRENT (mA) 3957A TA04c 1000 3957A TA04b Frequency Foldback Waveforms When Output Short-Circuit Start-Up Waveforms VIN = 12V VOUT 5V/DIV VOUT 10V/DIV VIN = 12V VSW 20V/DIV IL1A + IL1B 2A/DIV IL1A + IL1B 5A/DIV 5ms/DIV 3957A TA04d 50µs/DIV 3957A TA04e 3957af 26 LT3957A PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHE Package Variation: UHE36(28)MA 36(28)-Lead Plastic QFN (5mm × 6mm) (Reference LTC DWG # 05-08-1836 Rev D) 28 27 25 24 23 21 20 0.70 ±0.05 30 1.88 ± 0.05 31 5.50 ± 0.05 4.10 ± 0.05 1.50 REF 3.00 ± 0.05 32 33 16 3.00 ± 0.05 0.12 ± 0.05 34 17 1.53 ± 0.05 15 14 PACKAGE OUTLINE 13 0.48 ± 0.05 12 35 36 1 2 3 4 6 0.50 BSC 8 9 0.25 ±0.05 10 2.00 REF 5.10 ± 0.05 6.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 0.75 ± 0.05 R = 0.10 TYP PIN 1 TOP MARK (NOTE 6) 30 31 32 1.50 REF 33 34 35 28 27 2.00 REF 25 24 6.00 ± 0.10 1 1.88 ± 0.10 3.00 ± 0.10 0.12 ± 0.10 20 2 3 4 6 23 21 36 PIN 1 NOTCH R = 0.30 OR 0.35 × 45° CHAMFER 1.53 ± 0.10 0.48 ± 0.10 3.00 ± 0.10 8 R = 0.125 TYP 9 10 0.40 ± 0.10 0.200 REF 0.00 – 0.05 17 16 15 0.25 ± 0.05 0.50 BSC 14 13 12 (UHE36(28)MA) QFN 0112 REV D BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3957af 27 LT3957A TYPICAL APPLICATION 4V to 6V Input, 180V Output Flyback Converter DANGER! HIGH VOLTAGE! T1 1:10 VIN 4V TO 6V D1 VOUT 180V 15mA • CIN 100µF 6.3V ×2 • COUT 68nF ×2 D2 22Ω 75k VIN 220pF SW GND EN/UVLO FBX 37.4k LT3957A 1.80M SENSE1 22Ω SGND 15.8k SENSE2 SYNC 10nF VC INTVCC RT SS 140k 100kHz 0.1µF 100pF 10k 4.7µF 10V X5R 10nF 3957A TA05 T1: TDK DCT15EFD-U44S003 CIN: GRM31CR60J107ME39L COUT: GRM43QR72J683KW01L D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES D2: DIODES MMSZ5258B RELATED PARTS PART NUMBER LT3957 LT3757 DESCRIPTION Boost, Flyback, SEPIC and Inverting Converter with 5A/40V Switch High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter with 3.5A/80V Switch Boost, Flyback, SEPIC and Inverting Controller LT3758 Boost, Flyback, SEPIC and Inverting Controller LT3759 Boost, SEPIC and Inverting Controller LT3958 COMMENTS 3V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN-36 Package 5V ≤ VIN < 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 5mm × 6mm QFN-36 Package 2.9V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package 5.5V ≤ VIN ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package 1.6V ≤ VIN ≤ 42V, Current Mode Control, 100kHz to 1MHz Programmable Operation Frequency, MSOP-12E Package 3957af 28 Linear Technology Corporation LT 0312 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012