LTC1326/LTC1326-2.5 Micropower Precision Triple Supply Monitors U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Simultaneously Monitors Three Supplies LTC1326: 5V, 3.3V and ADJ LTC1326-2.5: 2.5V, 3.3V and ADJ Guaranteed Threshold Accuracy: ±0.75% Low Supply Current: 20µA Internal Reset Time Delay: 200ms Manual Push-Button Reset Input Active Low and Active High Reset Outputs Active Low “Soft” Reset Output Power Supply Glitch Immunity Guaranteed RESET for VCC3 ≥ 1V or VCC5 ≥ 1V or VCC25 ≥ 1V 8-Pin SO and MSOP Packages ■ ■ The RST output is guaranteed to be in the correct state for VCC3, VCC5 or VCC25 down to 1V. The LTC1326/LTC1326-2.5 can be configured to monitor one, two or three inputs, depending on system requirements. Desktop Computers Notebook Computers Intelligent Instruments Portable Battery-Powered Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ Tight 0.75% threshold accuracy and glitch immunity ensure reliable reset operation without false triggering. The 20µA typical supply current makes the LTC1326/ LTC1326-2.5 ideal for power-conscious systems. A manual push-button reset input provides the ability to generate a very narrow “soft” reset pulse (100µs typ) or a 200ms reset pulse equivalent to a power-on reset. Both SRST and RST outputs are open-drain and can be OR-tied with other reset sources. U APPLICATIO S ■ The LTC®1326/LTC1326-2.5 are triple supply monitors intended for systems with multiple supply voltages. They provide micropower operation, small size and high accuracy supply monitoring. TYPICAL APPLICATIO RST Output Voltage vs Supply Voltage (LTC1326-2.5) 3.5 SYSTEM LOGIC 0.1µF VCC25 VCC3 VCCA LTC1326-2.5 VCC25 = VCCA = VCC3 4.7k PULL-UP FROM RST TO VCC3 TA = 25°C 3.0 RST OUTPUT VOLTAGE (V) 2.5V 3.3V VCORE DC/DC CONVERTER 2.5 2.0 1.5 1.0 0.5 RST PBR PUSH-BUTTON RESET GND 0 SRST 0 0.5 1.0 1.5 2.0 VCC3 (V) 2.5 3.0 3.5 1326/2.5 TA02 1326/2.5 TA01 1 LTC1326/LTC1326-2.5 W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Terminal Voltage VCC3, VCC5, VCC25, VCCA ......................... – 0.5V to 7V RST, SRST ............................................ – 0.5V to 7V RST ...................................... – 0.5V to (VCC3 + 0.3V) PBR .......................................................... – 7V to 7V Operating Temperature Range LTC1326C/LTC1326C-2.5 ....................... 0°C to 70°C LTC1326I/LTC1326I-2.5 ..................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW VCC3 VCC5 VCCA GND 8 7 6 5 1 2 3 4 PBR SRST RST RST MS8 PACKAGE 8-LEAD PLASTIC MSOP LTC1326CMS8 VCCA 3 6 RST GND 4 5 RST LTC1326CMS8-2.5 MS8 PART MARKING TJMAX = 125°C, θJA = 250°C/W LTEK LTC1326CS8 LTC1326IS8 S8 PART NUMBER TJMAX = 125°C, θJA = 150°C/W PBR SRST RST RST MS8 PACKAGE 8-LEAD PLASTIC MSOP 7 SRST LTBA ORDER PART NUMBER 8 7 6 5 1 2 3 4 8 PBR S8 PACKAGE 8-LEAD PLASTIC SO TOP VIEW VCC3 VCC25 VCCA GND VCC3 1 VCC5 2 MS8 PART NUMBER TJMAX = 125°C, θJA = 250°C/W ORDER PART NUMBER TOP VIEW 1326 1326I ORDER PART NUMBER TOP VIEW VCC3 1 8 PBR VCC25 2 7 SRST VCCA 3 6 RST GND 4 5 RST LTC1326CS8-2.5 LTC1326IS8-2.5 S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO 132625 326I25 TJMAX = 125°C, θJA = 150°C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC3 = 3.3V, VCC5 = 5V (for LTC1326),VCC25 = 2.5V (for LTC1326-2.5), VCCA = VCC3, TA = 25°C unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VRT3 Reset Threshold VCC3 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C ● ● 3.094 3.052 3.118 3.118 3.143 3.143 V V VRT5 Reset Threshold VCC5 (LTC1326) 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C ● ● 4.687 4.625 4.725 4.725 4.762 4.762 V V VRT25 Reset Threshold VCC25 (LTC1326-2.5) 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C ● ● 2.344 2.312 2.363 2.363 2.381 2.381 V V VRTA Reset Threshold VCCA 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C ● ● 0.992 0.980 1.000 1.000 1.007 1.007 V V VCC VCC3 Operating Voltage RST in Correct Logic State ● 1 7 V IVCC3 VCC3 Supply Current PBR = VCC3 ● 40 µA 2 20 LTC1326/LTC1326-2.5 ELECTRICAL CHARACTERISTICS VCC3 = 3.3V, VCC5 = 5V (for LTC1326),VCC25 = 2.5V (for LTC1326-2.5), VCCA = VCC3, TA = 25°C unless otherwise noted. SYMBOL PARAMETER CONDITIONS TYP MAX IVCC5 VCC5 Input Current (LTC1326) VCC5 = 5V ● 4 7 µA IVCC25 VCC25 Input Current (LTC1326-2.5) VCC25 = 2.5V ● 2.8 7 µA IVCCA VCCA Input Current VCCA = 1V 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C ● ● –5 –15 0 0 5 15 nA nA RST Low with 10kΩ Pull-Up to VCC3 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C ● ● 140 140 200 200 280 300 ms ms ● 50 100 200 µs tRST Reset Pulse Width MIN tSRST Soft Reset Pulse Width SRST Low with 10kΩ Pull-Up to VCC3 tUV VCC Undervoltage Detect to RST VCC25, VCC3 or VCCA Less Than Reset Threshold VRT by More Than 1% IPBR PBR Pull-Up Current PBR = 0V 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C µs 13 ● ● 3 3 7 7 UNITS 10 15 µA µA 0.8 V VIL PBR, RST Input Low Voltage ● VIH PBR, RST Input High Voltage ● 2 V tPW PBR Min Pulse Width ● 40 ns tDB PBR Debounce Deassertion of PBR Input to SRST Output (PBR Pulse Width = 1µs) tPB PBR Assertion Time for Transition from Soft to Hard Reset Mode PBR Held Less Than VIL 0°C ≤ TA ≤ 70°C –40°C ≤ TA ≤ 85°C ● ● ISINK = 5mA VOL RST Output Voltage Low 1.4 1.4 20 35 ms 2.0 2.0 2.8 3.0 s s ● 0.15 0.4 V ISINK = 100µA, 0°C ≤ TA ≤ 70°C VCC3 = 1V, VCC5 = 0V VCC3 = 0V, VCC5 = 1V VCC3 = 1V, VCC5 = 1V ● ● ● 0.05 0.05 0.05 0.4 0.4 0.4 V V V ISINK = 100µA, –40°C ≤ TA ≤ 85°C VCC3 = 1.1V, VCC5 = 0V VCC3 = 0V, VCC5 = 1.1V VCC3 = 1.1V, VCC5 = 1.1V ● ● ● 0.05 0.05 0.05 0.4 0.4 0.4 V V V ISINK = 100µA, 0°C ≤ TA ≤ 70°C VCC3 = 1V, VCC25 = 0V VCC3 = 0V, VCC25 = 1V VCC3 = 1V, VCC25 = 1V ● ● ● 0.05 0.05 0.05 0.4 0.4 0.4 V V V ISINK = 100µA, –40°C ≤ TA ≤ 85°C VCC3 = 1.1V, VCC25 = 0V VCC3 = 0V, VCC25 = 1.1V VCC3 = 1.1V, VCC25 = 1.1V ● ● ● 0.05 0.05 0.05 0.4 0.4 0.4 V V V ISINK = 2.5mA ● 0.15 0.4 V RST Output Voltage Low ISINK = 2.5mA ● 0.15 0.4 V RST Output Voltage High (Note 3) ISOURCE = 1µA ● VCC3 – 1 V SRST Output Voltage High (Note 3) ISOURCE = 1µA ● VCC3 – 1 V ● VCC3 – 1 SRST Output Voltage Low VOH ● RST Output Voltage High ISOURCE = 600µA tPHL Prop Delay RST to RST High Input to Low Output CRST = 20pF 25 ns V tPLH Prop Delay RST to RST Low Input to High Output CRST = 20pF 45 ns 3 LTC1326/LTC1326-2.5 ELECTRICAL CHARACTERISTICS LTC1326 Only VCC3 = 3.3V, VCC5 = 5V, VCCA = VCC3, TA = 25°C unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOVR VCC5 Reset Override Voltage Override VCC5 Ability to Assert RST (Note 4) The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. MIN TYP MAX UNITS VCC3 ±0.025 V Note 3: The output pins SRST and RST have weak internal pull-ups to VCC3 of 6µA typ. However, external pull-up resistors may be used when faster rise times are required. Note 4: The VCC5 reset override voltage is valid for an operating range less than approximately 4.15V. Above this point the override is turned off and the VCC5 pin functions normally. U W TYPICAL PERFOR A CE CHARACTERISTICS IVCC5 vs Temperature (LTC1326) IVCC25 vs Temperature (LTC1326-2.5) 5.0 3.00 24 4.8 2.95 23 4.6 2.90 22 4.4 2.85 21 4.2 20 19 IVCC25 (µA) 25 IVCC5 (µA) 4.0 3.8 2.75 2.70 3.6 2.65 17 3.4 2.60 16 3.2 2.55 15 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 3.0 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 80 100 45 TRANSIENT DURATION (µs) 1 0 –1 –2 –3 0.8 0.85 0.9 0.95 1.0 1.05 1.1 1.15 1.2 INPUT VOLTAGE (V) 1326/2.5 G04 40 80 100 1326/2.5 G03 VCC25 Transient Immunity (LTC1326-2.5) 50 TA = 25°C 2 4 2.50 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 100 VCC5 Transient Immunity (LTC1326) VCCA Input Current vs Input Voltage 3 80 1326/2.5 G02 1326/2.5 G01 INPUT CURRENT (nA) 2.80 18 45 RESET OCCURS ABOVE CURVE TA = 25°C 35 30 25 20 15 10 40 TRANSIENT DURATION (µs) IVCC3 (µA) IVCC3 vs Temperature 35 RESET OCCURS ABOVE CURVE TA = 25°C 30 25 20 15 10 5 5 0 0.01 0.1 1 0.001 VCC5 RESET COMPARATOR OVERDRIVE (V) 0 0.01 0.1 1 0.001 VCC25 RESET COMPARATOR OVERDRIVE (V) 1326/2.5 G05 1326/2.5 G06 LTC1326/LTC1326-2.5 U W TYPICAL PERFOR A CE CHARACTERISTICS 4.750 40 RESET OCCURS ABOVE CURVE TA = 25°C 35 TRANSIENT DURATION (µs) 35 RESET OCCURS ABOVE CURVE TA = 25°C 30 25 20 15 10 30 25 20 15 10 5 5 0 0.01 0.1 1 0.001 VCCA RESET COMPARATOR OVERDRIVE (V) 0 0.01 0.1 1 0.001 VCC3 RESET COMPARATOR OVERDRIVE (V) 1326/2.5 G07 4.730 4.725 4.720 4.715 4.710 4.705 2.365 2.360 2.355 VCCA Threshold Voltage vs Temperature 3.130 3.125 3.120 3.115 3.110 3.105 0 20 40 60 80 1326/2.5 G10 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 100 TEMPERATURE (°C) SOFT RESET PULSE WIDTH, tSRST (µs) 215 210 205 200 195 80 100 1326/2.5 G13 PBR ASSERTION TIME TO RESET, tPB (SEC) 112.5 220 110.0 107.5 105.0 102.5 100.0 97.5 95.0 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 100 PBR Assertion Time to Reset vs Temperature “Soft” Reset Pulse Width vs Temperature 225 80 1326/2.5 G12 1326/2.5 G11 Reset Pulse Width vs Temperature 100 1.005 3.100 – 60 – 40 – 20 100 80 1326/2.5 G09 VCCA THRESHOLD VOLTAGE, VRTA (V) VCC3 THRESHOLD VOLTAGE, VRT3 (V) VCC25 THRESHOLD VOLTAGE, VRT25 (V) 2.370 190 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 4.735 4.700 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 3.135 80 4.740 VCC3 Threshold Voltage vs Temperature 2.375 2.350 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 4.745 1326/2.5 G08 VCC25 Threshold Voltage vs Temperature (LTC1326-2.5) RESET PULSE WIDTH, tRST (ms) VCC5 THRESHOLD VOLTAGE, VRT5 (V) 40 TRANSIENT DURATION (µs) VCC5 Threshold Voltage vs Temperature (LTC1326) VCC3 Transient Immunity VCCA Transient Immunity 80 100 1326/2.5 G14 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 – 60 – 40 – 20 0 20 40 60 TEMPERATURE (°C) 80 100 1326/2.5 G15 5 LTC1326/LTC1326-2.5 U U U PIN FUNCTIONS VCC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor. VCC5 (Pin 2) (LTC1326): 5V Sense Input. Used as gate drive for the RST output FET when the voltage on VCC3 is less than the voltage on VCC5. If unused, it can be tied to VCC3 (see Dual and Single Supply Monitor Operation in the Applications Information section). VCC25 (Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as gate drive for RST output FET when the voltage on VCC3 is less than the voltage on VCC25. If unused it can be tied to VCC3. VCCA (Pin 3): 1V Sense, High Impedance Input. Can be used as a logic input with a 1V threshold. If unused it can be tied to either VCC3 or VCC25. GND (Pin 4): Ground. RST (Pin 5): Reset Logic Output. Active high CMOS logic output, drives high to VCC3, buffered complement of RST. An external pull-down on the RST pin will drive this pin high. 6 RST (Pin 6): Reset Logic Output. Active low, open-drain logic output with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. Asserted when one or more of the supplies are below trip thresholds and held for 200ms after all supplies become valid. Also asserted after PBR is held low for more than 2 seconds and for an additional 200ms after PBR is released. SRST (Pin 7): Soft Reset. Active low, open-drain logic output with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. Asserted for 100µs after PBR is held low for less than 2 seconds and released. PBR (Pin 8): Push-Button Reset. Active low logic input with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. When asserted for less than 2 seconds, outputs a soft reset 100µs pulse on the SRST pin. When PBR is asserted for greater than 2 seconds, the RST output is forced low and remains low until 200ms after PBR is released. LTC1326/LTC1326-2.5 W BLOCK DIAGRA S LTC1326 VCC3 VCC3 6µA 7µA 7 SRST 6 RST 5 RST SOFT RESET PBR TIMER PBR 8 – RESET 4.15V TO POWER DETECT + – VCC5 2 + 25mV – VCC3 – 25mV VCC3 INTERNAL + + VCC3 1 VCC3 VCC3 6µA – 200ms RESET GENERATOR + POWER DETECT/ GATE DRIVE – VCCA 3 VCC5 + GND 4 VCC3 REF 1326 BD LTC1326-2.5 VCC3 VCC3 6µA 7µA PBR TIMER PBR 8 SRST 6 RST 5 RST RESET TO POWER DETECT VCC25 2 7 SOFT RESET VCC3 VCC3 6µA – VCC3 INTERNAL 200ms RESET GENERATOR + POWER DETECT/ GATE DRIVE VCC3 1 VCC25 – VCC3 + – VCCA 3 + GND 4 REF 1326-2.5 BD 7 LTC1326/LTC1326-2.5 WU W TI I G DIAGRA S VCC Monitor Timing VCCX Push-Button Reset Function Timing PBR VRTX t < tPB tRST tPB tRST tDB RST RST tSRST 1326/2.5 TD01 SRST 1326/2.5 TD02 U W U U APPLICATIO S I FOR ATIO Operation The LTC1326/LTC1326-2.5 are micropower, high accuracy triple supply monitoring circuits. The parts have two basic functions: generation of a reset when power supplies are out of range, and generation of reset or a “soft” reset when the PBR pin is pulled low. The three internal precision voltage comparators have response times that are typically 13µs. This slow response time helps prevent mistriggering due to transients on each of the VCC inputs. The part’s ability to suppress transients can be improved by bypassing each of the VCC inputs with a 0.1µF capacitor to ground. Supply Monitoring Push-Button Reset All three VCC inputs must be above predetermined thresholds for 200ms before the reset output is released. The parts will assert reset during power-up, power-down and brownout conditions on any one or more of the VCC inputs. The parts provide a push-button reset input pin. The PBR input has an internal pull-up current source to VCC3. If the PBR pin is not used it can be left floating. On power-up, either the VCC5 or VCC3 pin on the LTC1326, or the VCC25 or VCC3 pin on the LTC1326-2.5, can power the drive circuits for the RST pin. This ensures that RST will be low when VCC5, VCC25 or VCC3 reaches 1V. As long as any one of the VCC inputs is below its predetermined threshold, RST will stay a logic low. Once all of the VCC inputs rise above their thresholds, an internal timer is started and RST is released after 200ms. The RST pin outputs the inverted state of what is seen on RST pin. RST is reasserted whenever any one of the VCC inputs drops below its predetermined threshold and remains asserted until 200ms after all of the VCC inputs are above their thresholds. On power-down, once any of the VCC inputs drop below its threshold, RST is held at a logic low. A logic low of 0.4V is guaranteed until VCC3 and VCC5 on the LTC1326 or VCC3 and VCC25 on the LTC1326-2.5 drop below 1V. 8 When the PBR is pulled low for less than tPB (≈ 2 sec), a narrow (100µs typ) soft reset pulse is generated on the SRST output pin after the button is released. The pushbutton circuitry contains an internal debounce counter which delays the output of the soft reset pulse by typically 20ms. This pin can be OR-tied to the RST pin and issue what is called a “soft” reset. The SRST thereby resets the microprocessor without interrupting the DRAM refresh cycle. In this manner DRAM information remains undisturbed. Alternatively, SRST may be monitored by the processor to initiate a software-controlled reset. When the PBR pin is held low for longer than tPB (≈ 2 sec), a standard reset is generated on the RST and RST pins. Once the 2 second period has elapsed, a reset signal is produced by the push-button logic, thereby clearing the reset counter. Once the button is released, the reset counter begins counting the reset period (200ms nominal). Consequently, the reset outputs remain asserted for approximately 200ms after the button is released. LTC1326/LTC1326-2.5 U W U U APPLICATIO S I FOR ATIO During a supply induced reset condition, the ability of the PBR pin to force a soft reset condition on the SRST pin is disabled. In other words SRST will remain high. If the PBR pin is held low, both during and after a supply induced reset (low RST), the RST pin will remain low until 200ms after the PBR goes high. Power Detect/Gate Drive The LTC1326/LTC1326-2.5 for the most part are powered internally from the VCC3 pin. The exception is at the gate drive of the output FET on the RST pin. On the input to this FET is power detection circuitry used to detect and drive the gate from either the 3.3V input pin (VCC3) or the 5V input pin (VCC5) on the LTC1326 or the 2.5V input pin (VCC25) on the LTC1326-2.5. The gate drive is derived from the pin with the highest potential. This ensures the part pulls the RST pin low as soon as either input pin is ≥ 1V. Early versions of the LTC1326 did not have the power detect/gate drive circuitry. These early versions were powered off of VCC3 alone. Consult factory for date codes concerning this circuitry change. All date codes of the LTC1326-2.5 have the power detect/gate drive circuits. When monitoring either 3.3V or 5V with VCC3 strapped to VCC5, (see Figure 1) the LTC1326 determines which is the appropriate range. The LTC1326 handles this situation as shown in Figure 2. Above 1V and below VRT3, RST is held low. From VRT3 to approximately 4.15V the LTC1326 assumes 3.3V supply monitoring and RST is deasserted. Above approximately 4.15V the LTC1326 operates as a 5V monitor. In most systems the 5V supply will pass through the 3.1V to 4.15V region in <200ms during power-up, and the RST output will behave as desired. Table 1 summarizes the state of RST and RST at various operating voltages with VCC3 = VCC5. Table 1. Override Truth Table (VCC3 = VCC5) INPUTS (VCC3 = VCC5 = VCC) 0V ≤ VCC ≤ 1V The VCC3, VCC5 and VCCA inputs may be individually disabled by the following override techniques which allow the LTC1326 or LTC1326-2.5 to be used as a dual or single supply monitor. The VCC5 trip point is reenabled when the voltage on VCC5 is equal to the voltage on VCC3 ±25mV and the two inputs are greater than approximately 4.15V. In this manner the LTC1326 can function as a 5V monitor with the 3.3V monitor disabled. — 0 1 1 0 4.15V ≤ VCC ≤ VRT5 0 1 VRT5 ≤ VCC 1 0 3.3V OR 5V LTC1326 1 R1 ADJUSTABLE SUPPLY 3 R2 4 VCC3 PBR VCC5 SRST VCCA RST GND RST 8 7 6 4.7k SYSTEM RESET 5 1326/2.5 F01 Figure 1 5 VCC3 = VCC5 = VCCA = 0V TO 5V 4.7k PULL-UP FROM RST TO VCC3 RST OUTPUT VOLTAGE (V) The VCC5 input trip point is disabled if its voltage is equal to the voltage on VCC3 ±25mV and the voltage on VCC5 is less than 4.15V. In this manner the part will behave as a 3.3V monitor and the VCC5 reset will be disabled. — VRT3 ≤ VCC ≤ 4.15V LTC1326 Override Functions The VCCA pin, if unused, can be tied to either VCC3 or VCC5. This is an obvious solution since the trip points for VCC3 and VCC5 will always be greater than the trip point for VCCA. RST 1V ≤ VCC ≤ VRT3 2 Dual and Single Supply Monitor Operation RST 4 3 2 1 0 0 1 3 4 2 SUPPLY VOLTAGE (V) 5 1326/2.5 F02 Figure 2. RST Voltage vs Supply Voltage 9 LTC1326/LTC1326-2.5 U U W U APPLICATIO S I FOR ATIO Figure 3 contains a simple circuit for 5V systems that can’t risk the RST output going high in the 3.1V to 4.15V range (possibly due to very slow rise time on the 5V supply). Diode D1 powers the LTC1326 while dropping ≈0.6V from the VCC5 pin to the VCC3 pin. This prevents the part’s internal override circuit from being activated. Without the override circuit active, the RST pin stays low until VCC5 reaches VRT5 ≅ 4.725V. (See Figure 4.) 1 2 5V 3 0.1µF 4 VCC3 PBR VCC5 SRST VCCA RST GND RST The VCCA pin, if unused, can be tied to either VCC3 or VCC25. This is an obvious solution since the trip points for VCC3 and VCC25 will always be greater than the trip point for VCCA. Likewise, the VCC25, if unused, can be tied to VCC3. VCC3 must always be used. Tying VCC3 to VCC25 and operating off of a 2.5V supply will result in the continuous assertion of RST. Extending ESD Tolerance on the PBR Input Pin LTC1326 D1* LTC1326-2.5 Override Functions 8 7 4.7k 6 SYSTEM RESET 5 *MMBD914 OR EQUIVALENT 1326/2.5 F03 Figure 3. LTC1326 Monitoring a Single 5V Supply. D1 Used to Avoid RST High Near 3.3V to 4V (See Figure 2). The PBR pin is susceptible to ESD since it may be brought out to a front panel in normal applications. The ESD tolerance of this pin can be increased by adding a resistor in series with the PBR pin. A 10k resistor can increase the ESD tolerance of the PBR pin to approximately 10kV. The PBR’s internal pull-up current of 7µA typical means there is only 70mV (150mV max) dropped across the resistor. See Figure 5. LTC1326-2.5 3.3V RST OUTPUT VOLTAGE (V) 5 VCC5 = VCCA = 0V TO 5V 4.7k PULL-UP FROM RST TO VCC5 TA = 25°C 4 ADJUSTABLE SUPPLY OR DC/DC FEEDBACK DIVIDER 2.5V 2 3 R2 4 VCC3 PBR VCC25 SRST VCCA RST GND RST 8 PUSH-BUTTON RESET 7 6 SYSTEM RESET 5 3 *OPTIONAL RESISTOR EXTENDS ESD TOLERANCE OF PBR INPUT TO APPROXIMATELY 10kV 1326/2.5 F05 2 Figure 5. Triple Supply Monitor (3.3V, 2.5V and Adjustable) with Extended ESD Tolerance 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC5 (V) 1326/2.5 F04 Figure 4. RST Output Voltage Characteristics of the Circuit in Figure 3 10 R1 1 10k* LTC1326/LTC1326-2.5 U TYPICAL APPLICATIONS N Triple Supply Monitor (3.3V, 5V and Adjustable) LTC1326 1 3.3V ADJUSTABLE SUPPLY OR DC/DC FEEDBACK DIVIDER 2 5V R1 3 4 R2 VCC3 PBR VCC5 SRST VCCA RST GND 8 7 6 SYSTEM RESET 5 RST 1326/2.5 TA03 Dual Supply Monitor (3.3V and 5V, Defeat VCCA Input) LTC1326 1 3.3V 2 5V 3 4 VCC3 PBR VCC5 SRST VCCA RST GND RST 8 7 6 SYSTEM RESET 5 1326/2.5 TA05 Dual Supply Monitor (3.3V or 5V Plus Adj) 3.3V OR 5V LTC1326 1 2 ADJUSTABLE SUPPLY R1 3 4 R2 VCC3 PBR VCC5 SRST VCCA RST GND RST 8 4.7k 7 6 SYSTEM RESET 5 1326/2.5 F01 REFER TO LTC1326 OVERRIDE FUNCTIONS IN THE APPLICATIONS INFORMATION SECTION. Dual Supply Monitor (3.3V Plus Adj) 3.3V LTC1326-2.5 1 2 ADJUSTABLE SUPPLY R1 3 R2 4 VCC3 PBR VCC25 SRST VCCA RST GND RST 8 7 6 4.7k SYSTEM RESET 5 1326/2.5 TA07 11 LTC1326/LTC1326-2.5 U TYPICAL APPLICATIONS N SRST Tied to RST and OR-Tying Other Sources to RST to Generate Reset and Reset LTC1326/ LTC1326-2.5 PBR PUSHBUTTON 8 3.3V 4.7k 6µA RESET SRST 7 6µA RST 6 OTHER OPEN DRAIN RESET SOURCES OR-TIED TO RESET VCC3 RST 5 RESET 1326/2.5 TA08 Using VCCA Tied to DC/DC Feedback Divider 2.9V 35.7k 1% 3.3V 2.8k 5V 1% LTC1435 6 VOSENSE LTC1326 1 2 3 4 22.1k 1% ADJUSTABLE RESET TRIP THRESHOLD 2.74V VCC3 PBR VCC5 SRST VCCA RST GND RST 8 7 6 5 SYSTEM RESET 1326/2.5 TA09 Using the Short Pulse Width, Push-Button Soft Reset Feature to Initiate Hard Reset LTC1326-2.5 3.3V 2.5V 1 2 3 4 PBR VCC3 VCC25 SRST VCCA RST GND RST 40ns ≤ tP ≤ 10µs 8 7 6 RESET 5 PBR 20ms RST 200ms 12 1326/2.5 TA11 LTC1326/LTC1326-2.5 U TYPICAL APPLICATIONS N Monitoring a Negative Supply 3.3V C1 0.1µF LTC1326 1 2 5V R2 150k 1% R1 150k 1% Q1 2N3906 C2 0.1µF 3 4 VCC3 PBR VCC5 SRST VCCA RST GND RST 8 7 6 SYSTEM RESET 5 Q2 2N3906 VCCA R3 100k 1% Q3 2N3904 R4 392k 1% –5V R4 ≈ (100k)(0.98)(VTRIP + 0.55)(–1) SUPPLY VTRIP R4 – 5V – 4.6V 392k – 3.3V – 3V 237k – 12V – 10.8V 1M 1326/2.5 TA12 Reset Valid for VCC3 Down to 0V 3.3V 3.5 LTC1326-2.5 ADJUSTABLE SUPPLY R1 2.5V 2 3 R2 4 VCC3 PBR VCC25 SRST VCCA RST GND RST 8 7 6 5 VCC3 = VCC25 = VCCA TA = 25°C 3.0 100k SYSTEM RESET 1326/2.5 TA13 RST OUTPUT VOLTAGE (V) 1 2.5 RST OUTPUT WITH 100k PULL-UP TO VCC3 2.0 1.5 1.0 RST OUTPUT WITHOUT 100k PULL-UP. 10M LOAD TO GND 0.5 0 0 0.5 1.0 1.5 2.0 VCC3 (V) 2.5 3.0 3.5 1326/2.5 TA13a 13 LTC1326/LTC1326-2.5 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 8 7 6 5 0.118 ± 0.004** (3.00 ± 0.102) 0.192 ± 0.004 (4.88 ± 0.10) 1 0.040 ± 0.006 (1.02 ± 0.15) 0.007 (0.18) 2 3 4 0.034 ± 0.004 (0.86 ± 0.102) 0° – 6° TYP 0.021 ± 0.006 (0.53 ± 0.015) SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) TYP 0.006 ± 0.004 (0.15 ± 0.102) * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 14 MSOP (MS8) 1197 LTC1326/LTC1326-2.5 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 0996 15 LTC1326/LTC1326-2.5 U TYPICAL APPLICATIO Triple Supply Monitor with 3.3V and 5V System Resets 3.3V 5V LTC1326 1 2 ADJUSTABLE SUPPLY OR DC/DC FEEDBACK DIVIDER R1 3 R2 4 VCC3 PBR VCC5 SRST VCCA RST GND RST 8 7 6 5 10k 10k TO 3.3V SYSTEM RESET TO 5V SYSTEM RESET Q1 2N7002 1326/2.5 TA14 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC690 5V Supply Monitor, Watchdog Timer and Battery Backup 4.65V Threshold LTC694-3.3 3.3V Supply Monitor, Watchdog Timer and Battery Backup 2.9V Threshold LTC699 5V Supply Monitor and Watchdog Timer 4.65V Threshold LTC1232 5V Supply Monitor, Watchdog Timer and Push-Button Reset 4.37V/4.62V Threshold LTC1536 Precision Triple Supply Monitor for PCI Applications Meets PCI tFAIL Timing Specifications 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com 132625f LT/TP 1198 4K • PRINTED IN THE USA LINEAR TECHNOLOGY CORPORATION 1998