LTC3855 Dual, Multiphase Synchronous DC/DC Controller with Differential Remote Sense Features Description Dual, 180° Phased Controllers Reduce Required Input Capacitance and Power Supply Induced Noise n High Efficiency: Up to 95% n R SENSE or DCR Current Sensing n Programmable DCR Temperature Compensation n ±0.75% 0.6V Output Voltage Accuracy n Phase-Lockable Fixed Frequency 250kHz to 770kHz n True Remote Sensing Differential Amplifier n Dual N-Channel MOSFET Synchronous Drive n Wide V Range: 4.5V to 38V IN n V OUT Range: 0.6V to 12.5V without Differential Amplifier n V OUT Range: 0.6V to 3.3V with Differential Amplifier n Clock Input and Output for Up to 12-Phase Operation n Adjustable Soft-Start or V OUT Tracking n Foldback Output Current Limiting n Output Overvoltage Protection n 40-Pin (6mm × 6mm) QFN and 38-Lead FE Packages The LTC®3855 is a dual PolyPhase® current mode synchronous step-down switching regulator controller that drives all N-channel power MOSFET stages. It includes a high speed differential remote sense amplifier. The maximum current sense voltage is programmable for either 30mV, 50mV or 75mV, allowing the use of either the inductor DCR or a discrete sense resistor as the sensing element. n The LTC3855 features a precision 0.6V reference and can produce output voltages up to 12.5V. A wide 4.5V to 38V input supply range encompasses most intermediate bus voltages and battery chemistries. Power loss and supply noise are minimized by operating the two controller output stages out of phase. Burst Mode® operation, continuous or pulse-skipping modes are supported. The LTC3855 can be configured for up to 12-phase operation, has DCR temperature compensation, two power good signals and two current limit set pins. The LTC3855 is available in low profile 40-pin 6mm × 6mm QFN and 38-lead exposed pad FE packages. Applications n n n n Computer Systems Telecom Systems Industrial and Medical Instruments DC Power Distribution Systems L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and PolyPhase are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. Typical Application High Efficiency Dual 1.8V/1.2V Step-Down Converter 4.7µF + VIN 0.1µF 0.56µH TG2 BOOST1 SW1 SENSE1– VFB1 ITH1 DIFFOUT VFB2 ITH2 40.2k + 470pF 330µF ×2 20k 15k 0.1µF LTC3855 IL 5A/DIV 20k VOUT2 1.2V 15A 470pF TK/SS1 DIFFP SGND DIFFN TK/SS2 0.1µF Load Step (Forced Continuous Mode) ILOAD 5A/DIV 300mA TO 5A 0.4µH BG2 PGND2 FREQ SENSE2+ SENSE2– SENSE1+ 0.1µF BOOST2 SW2 BG1 PGND1 VOUT1 1.8V 15A 1µF INTVCC TG1 VIN 4.5V TO 20V 22µF 100k + 7.5k 20k 330µF ×2 VOUT 100mV/DIV AC-COUPLED VIN = 12V VOUT = 1.8V 50µs/DIV 3855 TA01a 3855 TA01 3855f LTC3855 Absolute Maximum Ratings (Note 1) Input Supply Voltage (VIN).......................... –0.3V to 40V Top Side Driver Voltages BOOST1, BOOST2................................... –0.3V to 46V Switch Voltage (SW1, SW2).......................... –5V to 40V INTVCC , RUN1, RUN2, PGOOD(s), EXTVCC, (BOOST1-SW1), (BOOST2-SW2).............. –0.3V to 6V SENSE1+, SENSE2+, SENSE1–, SENSE2– Voltages.................................. –0.3V to 13V MODE/PLLIN, ILIM1, ILIM2, TK/SS1, TK/SS2, FREQ, DIFFOUT, PHASMD Voltages.............. –0.3V to INTVCC DIFFP, DIFFN........................................... –0.3V to INTVCC ITEMP1, ITEMP2 Voltages..................... –0.3V to INTVCC ITH1 , ITH2 , VFB1 , VFB2 Voltages............... –0.3V to INTVCC INTVCC Peak Output Current (Note 8)...................100mA Operating Junction Temperature Range (Notes 2, 3) LTC3855..............................................–40°C to 125°C Storage Temperature Range....................–65°C to 125°C Lead Temperature (Soldering, 10 sec) (FE Package)...................................................... 300°C Pin Configuration TOP VIEW 6 33 TG1 ITH1 7 VFB1 VFB2 1 30 TG1 32 BOOST1 ITH1 2 29 BOOST1 8 31 PGND1 VFB1 3 28 PGND1 9 30 BG1 SGND 4 29 VIN VFB2 5 28 INTVCC ITH2 6 27 EXTVCC TK/SS2 7 24 EXTVCC SENSE2+ 8 23 BG2 SENSE2– 9 22 SW2 ILIM1 18 21 PGOOD2 ILIM2 19 20 PGOOD1 FE PACKAGE 38-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 25°C/W EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO PCB TG2 RUN2 17 11 12 13 14 15 16 17 18 19 20 SW2 23 TG2 22 PGND2 21 BOOST2 NC 24 BOOST2 DIFFOUT 16 25 INTVCC PGOOD2 DIFFN 15 26 VIN DIFFP 10 PGOOD1 25 PGND2 ILIM2 DIFFP 14 ILIM1 26 BG2 RUN2 13 27 BG1 41 SGND DIFFOUT 12 39 SGND DIFFN TK/SS2 11 SENSE2– 40 39 38 37 36 35 34 33 32 31 TK/SS1 ITH2 10 SENSE2+ SW1 34 SW1 TK/SS1 CLKOUT 35 CLKOUT 5 PHASMD 4 SENSE1– MODE/PLLIN 36 PHASMD FREQ 3 SENSE1+ ITEMP2 RUN1 TOP VIEW ITEMP1 37 MODE/PLLIN RUN1 38 FREQ 2 SENSE1+ 1 ITEMP1 SENSE1– ITEMP2 UJ PACKAGE 40-LEAD (6mm s 6mm) PLASTIC QFN TJMAX = 125°C, θJA = 33°C/W EXPOSED PAD (PIN 41) IS SGND, MUST BE SOLDERED TO PCB 3855f LTC3855 Order information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3855EFE#PBF LTC3855EFE#TRPBF LTC3855FE 38-Lead Plastic TSSOP –40°C to 85°C LTC3855IFE#PBF LTC3855IFE#TRPBF LTC3855FE 38-Lead Plastic TSSOP –40°C to 125°C 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LTC3855EUJ#PBF LTC3855EUJ#TRPBF LTC3855UJ LTC3855IUJ#PBF LTC3855IUJ#TRPBF LTC3855UJ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range (E-Grade), otherwise specifications are at TA = 25°C. VIN = 15V, VRUN1,2 = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops VIN Input Voltage Range VOUT Output Voltage Range VFB1,2 Regulated Feedback Voltage ITH1,2 Voltage = 1.2V (Note 4) ITH1,2 Voltage = 1.2V (Note 4), TA = 125°C IFB1,2 Feedback Current (Note 4) –15 –50 nA VREFLNREG Reference Voltage Line Regulation VIN = 4.5V to 38V (Note 4) 0.002 0.02 %/V VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V l Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V l 0.01 –0.01 0.1 –0.1 % % gm1,2 Transconductance Amplifier gm ITH1,2 = 1.2V; Sink/Source 5µA; (Note 4) IQ Input DC Supply Current Normal Mode Shutdown (Note 5) VIN = 15V VRUN1,2 = 0V l l 4.5 38 V 0.6 12.5 V 0.6045 0.606 V V 0.5955 0.594 0.600 0.600 2 3.5 30 DFMAX Maximum Duty Factor In Dropout, fOSC = 500kHz UVLO Undervoltage Lockout VINTVCC Ramping Down l UVLOHYS UVLO Hysteresis 94 95 3.0 3.2 mmho 50 % 3.4 0.6 VOVL1,2 Feedback Overvoltage Lockout Measured at VFB1,2 l ISENSE1,2 Sense Pins Bias Current (Each Channel); VSENSE1,2 = 3.3V l 0.64 mA µA V V 0.66 0.68 V ±1 ±2 µA ITEMP1,2 DCR Tempco Compensation Current VITEMP1,2 = 0.2V l 9 10 11 µA ITK/SS1,2 Soft-Start Charge Current VTK/SS1,2 = 0V l 1 1.2 1.4 µA VRUN1,2 RUN Pin ON Threshold VRUN1, VRUN2 Rising l 1.1 1.22 1.35 V VRUN1,2HYS RUN Pin ON Hysteresis VSENSE(MAX) Maximum Current Sense Threshold VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = 0V VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = Float VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = INTVCC l l l 25 45 68 30 50 75 TG1, 2 tr TG1, 2 tf TG Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 25 25 ns ns BG1, 2 tr BG1, 2 tf BG Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 25 25 ns ns 80 mV 35 55 82 mV mV mV 3855f LTC3855 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range (E-Grade), otherwise specifications are at TA = 25°C. VIN = 15V, VRUN1,2 = 5V unless otherwise noted. SYMBOL PARAMETER TG/BG t1D Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Each Driver Synchronous Switch-On Delay Time CONDITIONS MIN 30 ns BG/TG t2D Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver Top Switch-On Delay Time 30 ns tON(MIN) Minimum On-Time 90 ns (Note 7) TYP MAX UNITS INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 38V VLDO INT INTVCC Load Regulation ICC = 0mA to 20mA VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V VLDOHYS EXTVCC Hysteresis 4.8 l 4.5 5 5.2 V 0.5 2 % 4.7 50 V 100 200 mV mV Oscillator and Phase-Locked Loop fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz fLOW Lowest Frequency VFREQ = 0V 210 250 290 kHz fHIGH Highest Frequency VFREQ ≥ 2.4V 700 770 850 kHz RMODE/PLLIN MODE/PLLIN Input Resistance IFREQ Frequency Setting Current CLKOUT Phase (Relative to Controller 1) CLKHIGH Clock High Output Voltage CLKLOW Clock Low Output Voltage 250 9 10 kΩ 11 60 90 120 PHASMD = GND PHASMD = Float PHASMD = INTVCC 4 µA Deg Deg Deg 5 V 0 0.2 V 0.1 0.3 V ±2 µA PGOOD Output VPGL PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPG PGOOD Trip Level, Either Controller VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10 10 % % Differential Amplifier ADA Gain RIN Input Resistance Measured at DIFFP Input l VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA PSRROA Power Supply Rejection Ratio 5V < VIN < 38V ICL Maximum Output Current 0.998 1 1.002 80 kΩ 2 2 V/V mV 100 dB 3 mA VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300µA GBW Gain Bandwidth Product (Note 8) VINTVCC – 1.4 VINTVCC – 1.1 3 MHz V Slew Rate Differential Amplifier Slew Rate (Note 8) 2 V/µs 3855f LTC3855 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range (E-Grade), otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS On Chip Driver TG RUP TG Pull-Up RDS(ON) TG High 2.6 Ω TG RDOWN TG Pull-Down RDS(ON) TG Low 1.5 Ω BG RUP BG Pull-Up RDS(ON) BG High 2.4 Ω BG RDOWN BG Pull-Down RDS(ON) BG Low 1.1 Ω Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3855E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3855I is guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3855UJ: TJ = TA + (PD • 33°C/W) LTC3855FE: TJ = TA + (PD • 25°C/W) Note 4: The LTC3855 is tested in a feedback loop that servos VITH1,2 to a specified voltage and measures the resultant VFB1,2. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 8: Guaranteed by design. Typical Performance Characteristics 100 100 90 90 Burst Mode OPERATION 80 60 DCM VIN = 12V VOUT = 1.8V 50 40 CCM 30 20 90 5 1.8V EFFICIENCY Burst Mode OPERATION 60 50 DCM 40 VIN = 12V VOUT = 1.2V CCM 30 1.2V 85 4 1.8V POWER LOSS 80 3 1.2V 20 10 0 0.01 70 Full Load Efficiency and Power Loss vs Input Voltage POWER LOSS (W) 70 EFFICIENCY (%) 80 EFFICIENCY (%) Efficiency vs Output Current and Mode EFFICIENCY (%) Efficiency vs Output Current and Mode CIRCUIT OF FIGURE 19 0.1 1 10 LOAD CURRENT (A) 100 3855 G23 10 0 0.01 CIRCUIT OF FIGURE 19 0.1 1 10 LOAD CURRENT (A) 100 3855 G24 75 CIRCUIT OF FIGURE 19 5 10 15 INPUT VOLTAGE (V) 2 20 3855 G24 3855f LTC3855 Typical Performance Characteristics Load Step (Burst Mode Operation) Load Step (Forced Continuous Mode) ILOAD 5A/DIV 300mA TO 5A ILOAD 5A/DIV 300mA TO 5A IL 5A/DIV IL 5A/DIV VOUT 100mV/DIV AC-COUPLED VOUT 100mV/DIV AC-COUPLED VIN = 12V VOUT = 1.8V 50µs/DIV 3855 G01 VIN = 12V VOUT = 1.8V Load Step (Pulse-Skipping Mode) 3855 G02 50µs/DIV Inductor Current at Light Load ILOAD 5A/DIV 300mA TO 5A FORCED CONTINUOUS MODE 5A/DIV IL 5A/DIV Burst Mode OPERATION 5A/DIV VOUT 100mV/DIV AC-COUPLED VIN = 12V VOUT = 1.8V 50µs/DIV 3855 G03 PULSE-SKIPPING MODE 5A/DIV VIN = 12V VOUT = 1.8V ILOAD = 400mA Prebiased Output at 2V 3855 G04 1µs/DIV Coincident Tracking VOUT 2V/DIV RUN 2V/DIV VOUT1 VFB 500mV/DIV TK/SS 500mV/DIV VOUT1 VOUT2 1V/DIV VIN = 12V VOUT = 3.3V 2ms/DIV 3855 G05 VOUT2 5ms/DIV VOUT1 = 1.8V, 1.5Ω LOAD VOUT2 = 1.2V, 1Ω LOAD 3855 G06 3855f LTC3855 Typical Performance Characteristics Tracking Up and Down with External Ramp 4.5 TK/SS1 TK/SS2 2V/DIV Quiescent Current vs Temperature without EXTVCC 5.5 4.0 VOUT2 VOUT1 VOUT2 500mA/DIV 3855 G07 10ms/DIV VIN = 12V VOUT1 = 1.8V, 1.5Ω LOAD VOUT2 = 1.2V, 1Ω LOAD 5.0 3.5 INTVCC VOLTAGE (V) QUIESCENT CURRENT (mA) VOUT1 INTVCC Line Regulation 3.0 2.5 2.0 1.5 1.0 4.5 4.0 3.5 3.0 2.5 0.5 0 –50 –25 0 50 25 75 TEMPERATURE (°C) 100 2.0 125 0 10 30 20 INPUT VOLTAGE (V) 40 3855 G08 Maximum Current Sense Threshold vs Common Mode Voltage Current Sense Threshold vs ITH Voltage 20 ILIM = GND 0 –20 –40 0 0.5 1 1.5 VITH (V) 80 70 60 50 ILIM = FLOAT 40 30 ILIM = GND 20 10 0 2 ILIM = INTVCC CURRENT SENSE THRESHOLD (mV) CURRENT SENSE THRESHOLD (mV) ILIM = FLOAT 2 0 4 6 8 10 12 70 ILIM = INTVCC 60 50 ILIM = FLOAT 40 30 ILIM = GND 20 10 0 0 20 40 60 DUTY CYCLE (%) VSENSE COMMON MODE VOLTAGE (V) 3855 G10 3855 G11 Maximum Current Sense Voltage vs Feedback Voltage (Current Foldback) MAXIMUM CURRENT SENSE THRESHOLD (mV) VSENSE (mV) 60 40 Maximum Current Sense Threshold vs Duty Cycle 80 ILIM = INTVCC 80 100 3855 G12 TK/SS Pull-Up Current vs Temperature 1.6 90 ILIM = INTVCC 80 70 60 TK/SS CURRENT (µA) 80 3855 G09 ILIM = FLOAT 50 40 ILIM = GND 30 1.4 1.2 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 FEEDBACK VOLTAGE (V) 3855 G13 1.0 –50 –25 0 50 25 75 TEMPERATURE (°C) 100 125 3855 G14 3855f LTC3855 Typical Performance Characteristics Regulated Feedback Voltage vs Temperature Oscillator Frequency vs Temperature 1.26 612 900 1.24 610 800 608 700 ON 1.20 1.18 1.16 1.14 OFF 1.12 1.10 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 606 FREQUENCY (kHz) 1.22 REGULATED FEEDBACK VOLTAGE (mV) RUN PIN THRESHOLD (V) Shutdown (RUN) Threshold vs Temperature 604 602 600 598 100 50 25 75 0 TEMPERATURE (°C) 100 SHUTDOWN INPUT CURRENT (µA) 500 490 2.9 2.7 2.5 –40 –20 40 20 60 0 TEMPERATURE (°C) 80 100 480 100 125 60 510 FREQUENCY (kHz) UVLO THRESHOLD (V) 3.7 3.1 50 25 75 0 TEMPERATURE (°C) Shutdown Current vs Input Voltage 520 FALLING –25 3855 G17 Oscillator Frequency vs Input Voltage 3.5 VFREQ = GND 0 –50 125 RISING 3.3 300 594 –25 VFREQ = 1.2V 400 3855 G16 Undervoltage Lockout Threshold (INTVCC) vs Temperature 3.9 500 200 3855 G15 4.1 600 596 592 –50 125 VFREQ = INTVCC 5 10 25 15 20 30 INPUT VOLTAGE (V) 35 3855 G18 40 50 40 30 20 10 0 5 10 15 20 30 25 INPUT VOLTAGE (V) 3855 G19 Shutdown Current vs Temperature 35 40 3855 G20 Quiescent Current vs Input Voltage without EXTVCC 4.5 60 4.3 4.1 SUPPLY CURRENT (mA) SHUTDOWN CURRENT (µA) 50 40 30 20 3.9 3.7 3.5 3.3 3.1 2.9 10 2.7 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3855 G21 2.5 5 10 15 20 30 25 INPUT VOLTAGE (V) 35 40 3855 G22 3855f LTC3855 Pin Functions (FE38/UJ40) ITEMP1, ITEMP2 (Pin 2, Pin 1/Pin 37, Pin 36): Inputs of the temperature sensing comparators. Connect each of these pins to external NTC resistors placed near inductors. Floating these pins disables the DCR temperature compensation function. RUN1, RUN2 (Pin 3, Pin 17/Pin 38, Pin 13): Run Control Inputs. A voltage above 1.2V on either pin turns on the IC. However, forcing either of these pins below 1.2V causes the IC to shut down the circuitry required for that particular channel. There are 1µA pull-up currents for these pins. Once the Run pin rises above 1.2V, an additional 4.5µA pull-up current is added to the pin. SENSE1+, SENSE2+ (Pin 4, Pin 12/Pin 39, Pin 8): Current Sense Comparator Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing networks or current sensing resistors. SENSE1–, SENSE2– (Pin 5, Pin 13/Pin 40, Pin 9): Current Sense Comparator Inputs. The (–) inputs to the current comparators are connected to the outputs. TK/SS1, TK/SS2 (Pin 6, Pin 11/Pin 1, Pin 7): Output Voltage Tracking and Soft-Start Inputs. When one particular channel is configured to be the master of two channels, a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave of two channels, the VFB voltage of the master channel is reproduced by a resistor divider and applied to this pin. Internal soft-start currents of 1.2µA are charging these pins. ITH1, ITH2 (Pin 7, Pin 10/Pin 2, Pin 6): Current Control Thresholds and Error Amplifier Compensation Points. Each associated channels’ current comparator tripping threshold increases with its ITH control voltage. VFB1, VFB2 (Pin 8, Pin 9/Pin 3, Pin 5): Error Amplifier Feedback Inputs. These pins receive the remotely sensed feedback voltages for each channel from external resistive dividers across the outputs. DIFFP (Pin 14/Pin 10): Positive Input of Remote Sensing Differential Amplifier. Connect this to the remote load voltage of one of the two channels directly. DIFFN (Pin 15/Pin 11): Negative Input of Remote Sensing Differential Amplifier. Connect this to the negative terminal of the output capacitors. DIFFOUT (Pin 16/Pin 12): Output of Remote Sensing Differential Amplifier. Connect this to VFB1 or VFB2 through a resistive divider. ILIM1, ILIM2 (Pin 18, Pin 19/Pin 14, Pin 15): Current Comparator Sense Voltage Range Inputs. This pin can be tied to SGND, tied to INTVCC or left floating to set the maximum current sense threshold for each comparator. PGOOD1, PGOOD2 (Pin 20, Pin 21/Pin 16, Pin 17): Power Good Indicator Output for Each Channel. Open drain logic out that is pulled to ground when either channel output exceeds ±10% regulation window, after the internal 20µs power bad mask timer expires. EXTVCC (Pin 27/Pin 24): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 4.7V. Do not exceed 6V on this pin. INTVCC (Pin 28/Pin 25): Internal 5V Regulator Output. The control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. VIN (Pin 29/Pin 26): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1µF to 1µF). BG1, BG2 (Pin 30, Pin 26/Pin 27, Pin 23): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-Channel MOSFETs between PGND and INTVCC. PGND1, PGND2 (Pin 31, Pin 25/Pin 28, Pin 22): Power Ground Pin. Connect this pin closely to the sources of the bottom N-channel MOSFETs, the (–) terminal of CVCC and the (–) terminal of CIN. 3855f LTC3855 Pin Functions (FE38/UJ40) BOOST1, BOOST2 (Pin 32, Pin 24/Pin 29, Pin 21): Boosted Floating Driver Supplies. The (+) terminal of the bootstrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. TG1, TG2 (Pin 33, Pin 23/Pin 30, Pin 20): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch nodes voltages. SW1, SW2 (Pin 34, Pin 22/Pin 31, Pin 19): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. PHASMD (Pin 36/Pin 33): This pin can be tied to SGND, tied to INTVCC or left floating. This pin determines the relative phases between the internal controllers as well as the phasing of the CLKOUT signal. See Table 1 in the Operation section. CLKOUT (Pin 35/Pin 32): Clock output with phase changeable by PHASMD to enable usage of multiple LTC3855 in multiphase systems. MODE/PLLIN (Pin 37/Pin 34): This is a dual purpose pin. When external frequency synchronization is not used, this pin selects the operating mode. The pin can be tied to SGND, tied to INTVCC or left floating. SGND enables forced continuous mode. INTVCC enables pulse-skipping mode. Floating enables Burst Mode operation. For external sync, apply a clock signal to this pin. Both channels will go into forced continuous mode and the internal PLL will synchronize the internal oscillator to the clock. The PLL compensation network is integrated into the IC. FREQ (Pin 38/Pin 35): There is a precision 10µA current flowing out of this pin. A resistor to ground sets a voltage which in turn programs the frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. SGND (Exposed Pad Pin 39/ Pin 4, Exposed Pad Pin 41): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. Exposed pad must be soldered to PCB, providing a local ground for the control components of the IC, and be tied to the PGND pin under the IC. 3855f 10 LTC3855 Functional Block Diagram FREQ MODE/PLLIN PHASMD ITEMP EXTVCC VIN VIN 4.7V F 0.6V MODE/SYNC DETECT PLL-SYNC + – TEMPSNS + 5V REG + – CIN INTVCC INTVCC F BOOST CLKOUT OSC BURSTEN S R 3k + ON – ICMP + – IREV CB TG FCNT Q M1 SW SWITCH LOGIC AND ANTISHOOT THROUGH L1 SENSE+ VOUT DB SENSE– + RUN BG OV M2 CVCC SLOPE COMPENSATION ILIM COUT PGND PGOOD INTVCC + 1 51k ITHB UV – 0.54V VFB + – – + SS + – RUN 40k + DIFFAMP 40k R1 – + R2 40k – OV 40k DIFFN 0.66V SGND 1.2µA EA – + + 0.6V REF SLOPE RECOVERY ACTIVE CLAMP SLEEP VIN DIFFP UVLO 0.5V 1.2V 1µ A 0.55V ITH RC CC1 RUN TK/SS CSS 3855 FBD DIFFOUT 3855f 11 LTC3855 Operation Main Control Loop The LTC3855 is a constant-frequency, current mode stepdown controller with two channels operating 180 degrees out-of-phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator IREV, or the beginning of the next cycle. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 4.7V, an internal 5V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as one of the LTC3855 switching regulator outputs. Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period plus 100ns every third cycle to allow CB to recharge. However, it is recommended that a load be present or the IC operates at low frequency during the drop-out transition to ensure CB is recharged. Shutdown and Start-Up (RUN1, RUN2 and TK/SS1, TK/SS2 Pins) The two channels of the LTC3855 can be independently shut down using the RUN1 and RUN2 pins. Pulling either of these pins below 1.2V shuts down the main control loop for that controller. Pulling both pins low disables both controllers and most internal circuits, including the INTVCC regulator. Releasing either RUN pin allows an internal 1µA current to pull up the pin and enable that controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the Absolute Maximum Rating of 6V on this pin. The start-up of each controller’s output voltage VOUT is controlled by the voltage on the TK/SS1 and TK/SS2 pins. When the voltage on the TK/SS pin is less than the 0.6V internal reference, the LTC3855 regulates the VFB voltage to the TK/SS pin voltage instead of the 0.6V reference. This allows the TK/SS pin to be used to program the soft-start period by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.2µA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.6V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively the TK/SS pin can be used to cause the start-up of VOUT to “track” that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the corresponding RUN pin is pulled low to disable a controller, or when INTVCC drops below its undervoltage lockout threshold of 3.2V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, both controllers are disabled and the external MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction) The LTC3855 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to a DC 3855f 12 LTC3855 Operation voltage below 0.6V (e.g., SGND). To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTVCC. To select Burst Mode operation, float the MODE/PLLIN pin. When a controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTVCC, the LTC3855 operates in PWM pulse-skipping mode at light loads. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Multichip Operations (PHASMD and CLKOUT Pins) The PHASMD pin determines the relative phases between the internal controllers as well as the CLKOUT signal as shown in Table 1. The phases tabulated are relative to zero phase being defined as the rising edge of the clock of phase 1. Table 1. PHASMD GND FLOAT INTVcc Phase1 0° 0° 0° Phase2 180° 180° 240° CLKOUT 60° 90° 120° The CLKOUT signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). Single Output Multiphase Operation The LTC3855 can be used for single output multiphase converters by making these connections • Tie all of the ITH pins together • Tie all of the VFB pins together • Tie all of the TK/SS pins together • Tie all of the RUN pins together • Tie all of the ITEMP pins together • Tie all of the ILIM pins together, or tie the ILIM pins to the same potential For three or more phases, tie the inputs of the unused differential amplifier(s) to ground. Examples of single output multiphase converters are shown in Figures 20 to 23. 3855f 13 LTC3855 Operation Sensing the Output Voltage with a Differential Amplifier The LTC3855 includes a low offset, unity gain, high bandwidth differential amplifier for applications that require true remote sensing. Sensing the load across the load capacitors directly greatly benefits regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. The LTC3855 differential amplifier has a typical output slew rate of 2V/μs. The amplifier is configured for unity gain, meaning that the difference between DIFFP and DIFFN is translated to DIFFOUT, relative to SGND. Care should be taken to route the DIFFP and DIFFN PCB traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. In addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. Ideally, the DIFFP and DIFFN traces should be shielded by a low impedance ground plane to maintain signal integrity. Inductor DCR Sensing Temperature Compensation and the ITEMP Pins Inductor DCR current sensing provides a lossless method of sensing the instantaneous current. Therefore, it can provide higher efficiency for applications of high output currents. However the DCR of a copper inductor typically has a positive temperature coefficient. As the temperature of the inductor rises, its DCR value increases. The current limit of the controller is therefore reduced. LTC3855 offers a method to counter this inaccuracy by allowing the user to place an NTC temperature sensing resistor near the inductor. ITEMP pin, when left floating, is at a voltage around 5V and DCR temperature compensation is disabled. ITEMP pin has a constant 10µA precision current flowing out the pin. By connecting an NTC resistor from ITEMP pin to SGND, the maximum current sense threshold can be varied over temperature according the following equation: VSENSEMAX( ADJ) = VSENSE(MAX ) • 1.8 – VITEMP 1.3 Where: VSENSEMAX(ADJ) is the maximum adjusted current sense threshold. VSENSE(MAX) is the maximum current sense threshold specified in the electrical characteristics table. It is typically 75mV, 50mV, or 30mV depending on the setting ILIM pins. VITEMP is the voltage of ITEMP pin. The valid voltage range for DCR temperature compensation on the ITEMP pin is between 0.5V to 0.2V, with 0.5V or above being no DCR temperature correction and 0.2V the maximum correction. However, if the duty cycle of the controller is less than 25%, the ITEMP range is extended from 0.5V to 0V. An NTC resistor has a negative temperature coefficient, that means that its value decreases as temperature rises. The VITEMP voltage, therefore, decreases as temperature increases and in turn the VSENSEMAX(ADJ) will increase to compensate the DCR temperature coefficient. The NTC resistor, however, is non-linear and user can linearize its value by building a resistor network with regular resistors. Consult the NTC manufacture datasheets for detailed information. Another use for the ITEMP pins, in addition to NTC compensated DCR sensing, is adjusting VSENSE(MAX) to values between the nominal values of 30mV, 50mV and 75mV for a more precise current limit. This is done by applying a voltage less than 0.5V to the ITEMP pin. VSENSE(MAX) will be varied per the above equation and the same duty cycle limitations will apply. The current limit can be adjusted using this method either with a sense resistor or DCR sensing. For more information see the NTC Compensated DCR Sensing paragraph in the Applications Information section. Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching 3855f 14 LTC3855 Operation frequency of the LTC3855’s controllers can be selected using the FREQ pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller’s operating frequency from 250kHz to 770kHz. There is a precision 10µA current flowing out of the FREQ pin, so the user can program the controller’s switching frequency with a single resistor to SGND. A curve is provided later in the application section showing the relationship between the voltage on the FREQ pin and switching frequency. A phase-locked loop (PLL) is integrated on the LTC3855 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when it is synchronized. The PLL loop filter network is integrated inside the LTC3855. The phase-locked loop is capable of locking any frequency within the range of 250kHz to 770kHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock. Power Good (PGOOD Pins) When VFB pin voltage is not within ±10% of the 0.6V reference voltage, the PGOOD pin is pulled low. The PGOOD pin is also pulled low when the RUN pin is below 1.2V or when the LTC3855 is in the soft-start or tracking phase. The PGOOD pin will flag power good immediately when the VFB pin is within the ±10% of the reference window. However, there is an internal 20µs power bad mask when VFB goes out the ±10% window. Each channel has its own PGOOD and only responds to its own channel signals. The PGOOD pins are allowed to be pulled up by external resistors to sources of up to 6V. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Applications Information The Typical Application on the first page is a basic LTC3855 application circuit. LTC3855 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. Next, the power MOSFETs are selected. Finally, input and output capacitors are selected. for the maximum current sense threshold will be 30mV, 50mV or 75mV, respectively. The maximum current sense threshold will be adjusted to values between these settings by applying a voltage less than 0.5V to the ITEMP pin. See the Operation section for more details. Current Limit Programming The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of the current comparators is 0V to 12.5V. Both SENSE pins are high impedance inputs with small base currents of The ILIM pin is a tri-level logic input which sets the maximum current limit of the controller. When ILIM is either grounded, floated or tied to INTVCC, the typical value Which setting should be used? For the best current limit accuracy, use the 75mV setting. The 30mV setting will allow for the use of very low DCR inductors or sense resistors, but at the expense of current limit accuracy. The 50mV setting is a good balance between the two. For single output dual phase applications, use the 50mV or 75mV setting for optimal current sharing. SENSE+ and SENSE– Pins 3855f 15 LTC3855 Applications Information less than 1µA. When the SENSE pins ramp up from 0V to 1.4V, the small base currents flow out of the SENSE pins. When the SENSE pins ramp down from 12.5V to 1.1V, the small base currents flow into the SENSE pins. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. Because of possible PCB noise in the current sensing loop, the AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE also needs to be checked in the design to get a good signal-tonoise ratio. In general, for a reasonably good PCB layout, a 10mV ∆VSENSE voltage is recommended as a conservative number to start with, either for RSENSE or DCR sensing applications, for duty cycles less than 40%. Filter components mutual to the sense lines should be placed close to the LTC3855, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If DCR sensing is used (Figure 2b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1 should be placed close to the IC pins. For previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mV for the LTC1628 / LTC3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. For today’s highest current density solutions, however, the value of the sense resistor can be less than 1mΩ and the peak sense voltage can be as low as 20mV. In addition, inductor ripple currents greater than 50% with operation up to 1MHz are becoming more common. Under these conditions the voltage drop across the sense resistor’s parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 2a. In previous generations of controllers, a small RC filter placed near the IC was commonly used to reduce the effects of capacitive and inductive noise coupled inthe sense traces on the PCB. A typical filter consists of two series 10Ω resistors connected to a parallel 1000pF capacitor, resulting in a time constant of 20ns. TO SENSE FILTER, NEXT TO THE CONTROLLER COUT RSENSE 3855 F01 Figure 1. Sense Lines Placement with Sense Resistor Low Value Resistors Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. RSENSE is chosen based on the required output current. The current comparator has a maximum threshold VSENSE(MAX) determined by the ILIM setting. The input common mode range of the current comparator is 0V to 12.5V. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-topeak ripple current, ∆IL. To calculate the sense resistor value, use the equation: RSENSE = VSENSE(MAX) ∆I I(MAX) + L 2 This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 3 illustrates the voltage waveform across a 2mΩ sense resistor with a 2010 footprint for the 1.2V/15A converter operating at 100% load. The waveform is the superposition of a purely resistive component and a purely inductive component. It was measured using two scope probes and waveform math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: ESL = VESL(STEP) tON • tOFF ∆IL tON + tOFF If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), 3855f 16 LTC3855 Applications Information VIN INTVCC BOOST TG LTC3855 BG PGND SENSE– SGND VIN INTVCC SENSE RESISTOR PLUS PARASITIC INDUCTANCE BOOST RS SW SENSE+ VIN RF ESL BG PGND R1** SENSE+ RP C1* SGND RF VOUT DCR LTC3855 RS RNTC CF L SW ITEMP CF • 2RF ≤ ESL/RS POLE-ZERO CANCELLATION INDUCTOR TG OPTIONAL TEMP COMP NETWORK VOUT VIN R2 SENSE– 3855 F02a L R2 R = DCR **PLACE R1 NEXT TO *PLACE C1 NEAR SENSE+, R1||R2 × C1 = DCR SENSE(EQ) R1 + R2 INDUCTOR SENSE– PINS FILTER COMPONENTS PLACED NEAR SENSE PINS (2a) Using a Resistor to Sense Current 3855 F02b (2b) Using the Inductor DCR to Sense Current Figure 2. Two Different Methods of Sensing Current the resulting waveform looks resistive again, as shown in Figure 4. For applications using low maximum sense voltages, check the sense resistor manufacturer’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use the equation above to determine the ESL. However, do not over-filter. Keep the RC time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on VRSENSE. The above generally applies to high density/high current applications where I(MAX) >10A and low values of inductors are used. For applications where I(MAX) <10A, set RF to 10 Ohms and CF to 1000pF. This will provide a good starting point. The filter components need to be placed close to the IC. The positive and negative sense traces need to be routed as a differential pair and Kelvin connected to the sense resistor. Inductor DCR Sensing VESL(STEP) VSENSE 20mV/DIV 500ns/DIV 3855 F03 Figure 3. Voltage Waveform Measured Directly Across the Sense Resistor. VSENSE 20mV/DIV 500ns/DIV 3855 F04 Figure 4. Voltage Waveform Measured After the Sense Resistor Filter. CF = 1000pF, RF = 100Ω. For applications requiring the highest possible efficiency at high load currents, the LTC3855 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to DCR sensing. If the external R1|| R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not 3855f 17 LTC3855 Applications Information always the same and varies with temperature; consult the manufacturers’ datasheets for detailed information. Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: RSENSE(EQUIV) = VSENSE(MAX) ∆I I(MAX) + L 2 To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the Maximum Current Sense Threshold (VSENSE(MAX)) in the Electrical Characteristics table (25mV, 45mV, or 68mV, depending on the state of the ILIM pin). Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C or use LTC3855 DCR temperature compensation function. A conservative value for TL(MAX) is 100°C. To scale the maximum inductor DCR to the desired sense resistor value, use the divider ratio: RD = RSENSE(EQUIV) DCR(MAX) at TL(MAX) C1 is usually selected to be in the range of 0.047µF to 0.47µF. This forces R1|| R2 to around 2kΩ, reducing error that might have been caused by the SENSE pins’ ±1µA current. TL(MAX) is the maximum inductor temperature. The equivalent resistance R1|| R2 is scaled to the room temperature inductance and maximum DCR: R1||R2 = L (DCR at 20°C) • C1 The sense resistor values are: R1= R1|| R2 R1 • RD ; R2 = RD 1− RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS R1= (V IN(MAX) − VOUT R1 )•V OUT Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. To maintain a good signal to noise ratio for the current sense signal, use a minimum ∆VSENSE of 10mV for duty cycles less than 40%. For a DCR sensing application, the actual ripple voltage will be determined by the equation: ∆VSENSE = VIN − VOUT VOUT R1• C1 VIN • fOSC NTC Compensated DCR Sensing For DCR sensing applications where a more accurate current limit is required, a network consisting of an NTC thermistor placed from the ITEMP pin to ground will provide correction of the current limit over temperature. Figure 2b shows this network. Resistors RS and RP will linearize the impedance the ITEMP pin sees. To implement NTC compensated DCR sensing, design the DCR sense filter network per the same procedure mentioned in the previous selection, except calculate the divider components using the room temperature value of the DCR. For a single output rail operating from one phase: 1.Set the ITEMP pin resistance to 50k at 25°C. With 10µA flowing out of the ITEMP pin, the voltage on the ITEMP pin will be 0.5V at room temperature. Current limit correction will occur for inductor temperatures greater than 25°C. 2.Calculate the ITEMP pin resistance and the maximum inductor temperature which is typically 100°C. Use the following equations: 3855f 18 LTC3855 Applications Information RITEMP100C = VITEMP100C 10µA VITEMP100C = 0.5V − 1.3 • IMAX • DCR(MAX) • R2 (1100°C − 25°C) • 0.4 • R1+ R2 100 VSENSE(MAX ) Calculate the values for RP and RS. A simple method is to graph the following RS versus RP equations with RS on the y-axis and RP on the x-axis. After determining the components for the temperature compensation network, check the results by plotting IMAX versus inductor temperature using the following equations: IMAX = VSENSEMAX( ADJ) − ∆VSENSE 2 0.4 DCR(MAX) at 25°C • 1+ TL(MAX ) − 25°C • 100 ( ) where RS = RITEMP25C – RNTC25C || RP VSENSEMAX( ADJ) = VSENSE(MAX ) • RS = RITEMP100C – RNTC100C || RP Next, find the value of RP that satisfies both equations which will be the point where the curves intersect. Once RP is known, solve for RS. VITEMP = 10µA • (RS + RP || RNTC) The resistance of the NTC thermistor can be obtained from the vendor’s data sheet either in the form of graphs, tabulated data, or formulas. The approximate value for the NTC thermistor for a given temperature can be calculated from the following equation: 1 R = RO • exp B • 1 − T + 273 TO + 273 1.8 V − VITEMP −A 1.3 Use typical values for VSENSE(MAX). Subtracting constant A will provide a minimum value for VSENSE(MAX). These values are summarized in Table 2. Table 2. ILIM GND FLOAT INTVCC VSENSE(MAX) TYP 30mV 50mV 75mV A 5mV 5mV 7mV where The resulting current limit should be greater than or equal to IMAX for inductor temperatures between 25°C and 100°C. R = Resistance at temperature T, which is in degrees C Typical values for the NTC compensation network are: RO = Resistance at temperature TO, typically 25°C • NTC RO = 100k, B-constant = 3000 to 4000 B = B-constant of the thermistor • RS ≈ 20k Figure 5 shows a typical resistance curve for a 100k thermistor and the ITEMP pin network over temperature. • RP ≈ 50k Starting values for the NTC compensation network are: • NTC RO = 100k • RS = 20k • RP = 50k But, the final values should be calculated using the above equations and checked at 25°C and 100°C. Generating the IMAX versus inductor temperature curve plot first using the above values as a starting point and then adjusting the RS and RP values as necessary is another approach. Figure 6 shows a typical curve of IMAX versus inductor temperature. For PolyPhase applications, tie the ITEMP pins together and calculate for an ITEMP pin current of 10µA • #phases. The same thermistor network can be used to correct for temperatures less than 25°C. But make sure VITEMP is 3855f 19 LTC3855 Applications Information 10000 25 THERMISTOR RESISTANCE RO = 100k, TO = 25°C B = 4334 for 25°C/100°C 20 CORRECTED IMAX IMAX (A) RESISTANCE (kΩ) 1000 100 RITMP RS = 20kΩ RP = 43.2kΩ 100k NTC 10 1 –40 –20 0 20 40 60 80 100 120 INDUCTOR TEMPERATURE (°C) 15 NOMINAL IMAX UNCORRECTED IMAX RS = 20kΩ RP = 43.2kΩ 5 NTC THERMISTOR: RO = 100k TO = 25°C B = 4334 0 20 40 60 80 100 120 –40 –20 0 INDUCTOR TEMPERATURE (°C) 10 3855 F05 3855 F06 Figure 5. Resistance Versus Temperature for ITEMP Pin Network and the 100k NTC Figure 6. Worst Case IMAX Versus Inductor Temperature Curve with and without NTC Temperature Compensation greater than 0.2V for duty cycles of 25% or more, otherwise temperature correction may not occur at elevated ambients. For the most accurate temperature detection, place the thermistors next to the inductors as shown in Figure 7. Take care to keep the ITEMP pins away from the switch nodes. maximum inductor peak current to remain unaffected throughout all duty cycles. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constantfrequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3855 uses a scheme that counteracts this compensating ramp, which allows the CONNECT TO ITEMP1 NETWORK VOUT1 VOUT2 L1 L2 SW1 SW2 CONNECT TO ITEMP2 NETWORK Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency fOSC directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VIN – VOUT VIN fOSC • L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. VOUT RNTC2 RNTC1 GND GND 3855 F07a (7a) Dual Output Dual Phase DCR Sensing Application L1 SW1 RNTC L2 SW2 3855 F07b (7b) Single Output Dual Phase DCR Sensing Application Figure 7. Thermistor Locations. Place Thermistor Next to Inductor(s) for Accurate Sensing of the Inductor Temperature, but Keep the ITEMP Pins Away from the Switch Nodes and Gate Drive Traces 3855f 20 LTC3855 Applications Information A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX) for a duty cycle less than 40%. Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC •IRIPPLE VIN For duty cycles greater than 40%, the 10mV current sense ripple voltage requirement is relaxed because the slope compensation signal aids the signal-to-noise ratio and because a lower limit is placed on the inductor value to avoid subharmonic oscillations. To ensure stability for duty cycles up to the maximum of 95%, use the following equation to find the minimum inductance. LMIN > VOUT • 1.4 fSW • ILOAD(MAX ) where LMIN is in units of µH fSW is in units of MHz Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3855: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance RDS(ON) , Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle = VIN – VOUT VIN 3855f 21 LTC3855 Applications Information The MOSFET power dissipations at maximum output current are given by: VOUT 2 IMAX ) (1+ d) RDS(ON) + ( VIN 2 I ( VIN ) MAX (RDR )(CMILLER ) • 2 1 1 • fOSC + VINTVCC – VTH(MIN) VTH(MIN) PMAIN = PSYNC = VIN – VOUT 2 IMAX ) (1+ d) RDS(ON) ( VIN where d is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. VTH(MIN) is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + d) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but d = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diodes conduct during the dead time between the conduction of the two power MOSFETs. These prevent the body diodes of the bottom MOSFETs from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. A Schottky diode in parallel with the bottom FET may also provide a modest improvement in Burst Mode efficiency. Soft-Start and Tracking The LTC3855 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown state if its RUN pin voltage is below 1.2V. Its TK/SS pin is actively pulled to ground in this shutdown state. Once the RUN pin voltage is above 1.2V, the channel powers up. A soft-start current of 1.2µA then starts to charge its soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.6V on the TK/SS pin. The total soft-start time can be calculated as: t SOFTSTART = 0.6 • CSS 1.2µA Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.54V. The output ripple is minimized during the 40mV forced continuous mode window ensuring a clean PGOOD signal. When the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft-start capacitor charging current is always flowing, 3855f 22 LTC3855 Applications Information producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC3855 is forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.54V regardless of the setting on the MODE/PLLIN pin. However, the LTC3855 should always be set in force continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, its channel will operate in discontinuous mode. Output Voltage Tracking The LTC3855 allows the user to program how its output ramps up and down by means of the TK/SS pins. Through these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown in Figure 8. In the following discussions, VOUT1 refers to the LTC3855’s output 1 as a master channel and VOUT2 refers to the LTC3855’s output 2 as a slave channel. In practice, though, either phase can be used as the master. To implement the coincident tracking in Figure 8a, connect an additional resistive divider to VOUT1 and connect its midpoint to the TK/SS pin of the slave channel. The ratio of this divider should be the same as that of the slave channel’s feedback divider shown in Figure 9a. In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking in Figure 9b, the ratio of the VOUT2 divider should be exactly the same as the master channel’s feedback divider shown in Figure 9b. By selecting different resistors, the LTC3855 can achieve different modes of tracking including the two in Figure 8. So which mode should be programmed? While either mode in Figure 8 satisfies most practical applications, some tradeoffs exist. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. When the master channel’s output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 TIME VOUT2 TIME 3855 F08a (8a) Coincident Tracking 3855 F08b (8b) Ratiometric Tracking Figure 8. Two Different Modes of Output Voltage Tracking VOUT1 TO TK/SS2 PIN VOUT2 R3 R4 R1 R2 TO VFB1 PIN TO VFB2 PIN R3 R4 VOUT1 TO TK/SS2 PIN VOUT2 R1 R2 TO VFB1 PIN TO VFB2 PIN R3 R4 3855 F09 (9a) Coincident Tracking Setup (9b) Ratiometric Tracking Setup Figure 9. Setup for Coincident and Ratiometric Tracking 3855f 23 LTC3855 Applications Information INTVCC Regulators and EXTVCC The LTC3855 features a true PMOS LDO that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC3855’s internal circuitry. The linear regulator regulates the voltage at the INTVCC pin to 5V when VIN is greater than 5.5V. EXTVCC connects to INTVCC through a P-channel MOSFET and can supply the needed power when its voltage is higher than 4.7V. Each of these can supply a peak current of 100mA and must be bypassed to ground with a minimum of 4.7µF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3855 to be exceeded. The INTVCC current, which is dominated by the gate charge current, may be supplied by either the 5V linear regulator or EXTVCC. When the voltage on the EXTVCC pin is less than 4.7V, the linear regulator is enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC3855 INTVCC current is limited to less than 44mA from a 38V supply in the UJ package and not using the EXTVCC supply: TJ = 70°C + (44mA)(38V)(33°C/W) = 125°C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.7V, the INTVCC linear regulator is turned off and the EXTVCC is connected to the INTVCC. The EXTVCC remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using the EXTVCC allows the MOSFET driver and control power to be derived from one of the LTC3855’s switching regulator outputs during normal operation and from the INTVCC when the output is out of regulation (e.g., start-up, short-circuit). If more current is required through the EXTVCC than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC < VIN. Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Tying the EXTVCC pin to a 5V supply reduces the junction temperature in the previous example from 125°C to: TJ = 70°C + (44mA)(5V)(33°C/W) = 77°C However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If a 5V external supply is available, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. For applications where the main input power is below 5V, tie the VIN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown in Figure 10 to minimize the voltage drop caused by the gate charge current. This will override the INTVCC linear regulator and will prevent INTVCC from dropping too low 3855f 24 LTC3855 Applications Information due to the dropout voltage. Make sure the INTVCC voltage is at or exceeds the RDS(ON) test voltage for the MOSFET which is typically 4.5V for logic level devices. LTC3855 VIN RVIN INTVCC CINTVCC 4.7µF 1Ω 5V + CIN 3855 F07 Figure 10. Setup for a 5V Input Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Undervoltage Lockout The LTC3855 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.2V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 600mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pins have a precision turn-on reference of 1.2V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.2V. One can program the hysteresis of the run comparator by adjusting the values of the resistive divider. For accurate VIN undervoltage detection, VIN needs to be higher than 4.5V. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-ofphase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ 1/2 IMAX ( VOUT ) ( VIN – VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3855, ceramic capacitors 3855f 25 LTC3855 Applications Information can also be used for CIN. Always consult the manufacturer if there is any question. output, as shown in Figure 11. The regulated output voltage is determined by: The benefit of the LTC3855 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. R VOUT = 0.6V • 1+ B RA A small (0.1µF to 1µF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3855, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by: 1 ∆VOUT ≈IRIPPLE ESR + 8fCOUT where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. Setting Output Voltage The LTC3855 output voltages are each set by an external feedback resistive divider carefully placed across the To improve the frequency response, a feed-forward capacitor, CFF , may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. VOUT RB 1/2 LTC3855 CFF VFB RA 3855 F11 Figure 11. Setting Output Voltage Fault Conditions: Current Limit and Current Foldback The LTC3855 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start or tracking up. Under short-circuit conditions with very low duty cycles, the LTC3855 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The shortcircuit ripple current is determined by the minimum ontime tON(MIN) of the LTC3855 (≈ 90ns), the input voltage and inductor value: ∆IL(SC) = tON(MIN) • VIN L The resulting short-circuit current is: ISC = 1/3 VSENSE(MAX) RSENSE 1 – ∆IL(SC) 2 3855f 26 LTC3855 Applications Information Phase-Locked Loop and Frequency Synchronization 900 The LTC3855 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The turn-on of controller 2’s top MOSFET is thus 180 degrees outof-phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. 800 The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. There is a precision 10µA of current flowing out of FREQ pin. This allows the user to use a single resistor to SGND to set the switching frequency when no external clock is applied to the MODE/PLLIN pin. The internal switch between FREQ pin and the integrated PLL filter network is ON, allowing the filter network to be pre-charged to the same voltage potential as the FREQ pin. The relationship between the voltage on the FREQ pin and the operating frequency is shown in Figure 12 and specified in the Electrical Characteristic table. If an external clock is detected on the MODE/PLLIN pin, the internal switch mentioned above will turn off and isolate the influence of FREQ pin. Note that the LTC3855 can only be synchronized to an external clock whose frequency is within range of the LTC3855’s internal VCO. This is guaranteed to be between 250kHz and 770kHz. A simplified block diagram is shown in Figure 13. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC , then current is sourced continuously from the phase detector output, pulling up the filter network. When the external clock frequency is less than fOSC , current is sunk continuously, pulling down the filter network. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. FREQUENCY (kHz) 700 600 500 400 300 200 100 0 0 0.5 1 1.5 FREQ PIN VOLTAGE (V) 2 2.5 3855 F12 Figure 12. Relationship Between Oscillator Frequency and Voltage at the FREQ Pin 2.4V 5V RSET 10µA FREQ EXTERNAL OSCILLATOR MODE/ PLLIN DIGITAL SYNC PHASE/ FREQUENCY DETECTOR VCO 3855 F13 Figure 13. Phase-Locked Loop Block Diagram Typically, the external clock (on MODE/PLLIN pin) input high threshold is 1.6V, while the input low threshold is 1V. It is not recommended to apply the external clock when IC is in shutdown. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3855 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that tON(MIN) < VOUT VIN (f) 3855f 27 LTC3855 Applications Information If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3855 is approximately 90ns, with reasonably good PCB layout, minimum 30% inductor current ripple and at least 10mV – 15mV ripple on the current sense signal. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on-time gradually increases to 130ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3855 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1.The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VIN current typically results in a small (<0.1%) loss. 2.INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through EXTVCC from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3.I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor. In continuous mode, the average output current flows through L and RSENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A for a 5V output, or a 3% to 12% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4.Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses during the design phase. The internal battery and fuse resistance 3855f 28 LTC3855 Applications Information losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20µF to 40µF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. The LTC3855 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. Modest improvements in Burst Mode efficiency may be realized by using a smaller inductor value, a lower switching frequency or for DCR sensing applications, making the DCR filter’s time constant smaller than the L/DCR time constant for the inductor. A small Schottky diode with a current rating equal to about 20% of the maximum load current or less may yield minor improvements, too. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT . ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD . Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. 3855f 29 LTC3855 Applications Information PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 14. Figure 15 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: 1.Are the top N-channel MOSFETs M1 and M3 located within 1 cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2.Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as possible. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3.Do the LTC3855 VFB pins’ resistive dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4.Are the SENSE+ and SENSE– leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5.Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 6.Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposite channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3855 and occupy minimum PC trace area. If DCR sensing is used, place the top resistor (Figure 2b, R1) close to the switching node. 7.Are DIFFP and DIFFN leads routed together and correctly Kelvin sensing the output voltage? 8.Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. PC Board Layout Debugging Start with one controller at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. 3855f 30 LTC3855 Applications Information CLKOUT ITH1 LTC3855 RPU2 PGOOD PGOOD VPULL-UP DIFFP DIFFN L1 DIFFOUT SENSE1+ SENSE1– CB1 BG1 MODE/PLLIN COUT1 PGND VIN INTVCC SENSE2+ BG2 M3 BOOST2 GND COUT2 1µF CERAMIC + SENSE2– CIN CINTVCC + EXTVCC TK/SS2 RIN CVIN D1 + VIN SGND ITH2 M2 1µF CERAMIC RUN1 VFB2 M1 BOOST1 ILIM RUN2 VOUT1 SW1 FREQ fIN RSENSE TG1 + VFB1 TK/SS1 M4 D2 CB2 SW2 RSENSE TG2 VOUT2 L2 3855 F14 Figure 14. Recommended Printed Circuit Layout Diagram SW1 L1 D1 RSENSE1 VOUT1 COUT1 RL1 VIN RIN CIN SW2 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. D2 L2 RSENSE2 VOUT2 COUT2 RL2 3855 F15 Figure 15. Branch Current Waveforms 3855f 31 LTC3855 Applications Information This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. input voltage: Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. Design Example As a design example for a two channel high current regulator, assume VIN = 12V(nominal), VIN = 20V(maximum), VOUT1 = 1.8V, VOUT2 = 1.2V, IMAX1,2 = 15A, and f = 400kHz (see Figure 16). The regulated output voltages are determined by: VOUT R = 0.6V • 1+ B R A Using 20k 1% resistors from both VFB nodes to ground, the top feedback resistors are (to the nearest 1% standard value) 40.2k and 20k. The frequency is set by biasing the FREQ pin to 1V (see Figure 12). The inductance values are based on a 35% maximum ripple current assumption (5.25A for each channel). The highest value of ripple current occurs at the maximum L= VOUT VOUT 1− f • ∆IL (MAX ) VIN(MAX ) Channel 1 will require 0.78µH, and channel 2 will require 0.54µH. The Vishay IHLP4040DZ-01, 0.56µH inductor is chosen for both rails. At the nominal input voltage (12V), the ripple current will be: ∆IL(NOM) = VOUT VOUT 1− f •L VIN(NOM) Channel 1 will have 6.8A (46%) ripple, and channel 2 will have 4.8A (32%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or 18.4A for channel 1 and 17.4A for channel 2. The minimum on-time occurs on channel 2 at the maximum VIN, and should not be less than 90ns: tON(MIN) = VOUT VIN(MAX) f = 1.2V = 150ns 20V(400kHz) With ILIM floating, the equivalent RSENSE resistor value can be calculated by using the minimum value for the maximum current sense threshold (45mV). RSENSE(EQUIV) = VSENSE(MIN) ∆IL(NOM) ILOAD(MAX) + 2 The equivalent required RSENSE value is 2.4mΩ for channel 1 and 2.6mΩ for channel 2. The DCR of the 0.56µH inductor is 1.7mΩ typical and 1.8mΩ maximum for a 25°C ambient. At 100°C, the estimated maximum DCR value is 2.3mΩ. The maximum DCR value is just slightly under the equivalent RSENSE values. Therefore, R2 is not required to divide down the signal. For each channel, 0.1µF is selected for C1. R1= (DCRMAX L 0.56µH = = 3.11k at 25°C) • C1 1.8mΩ • 0.1µF Choose R1 = 3.09k 3855f 32 LTC3855 Applications Information 4.7µF M1 D3 0.1µF L1 0.56µH M2 BG1 LTC3855 MODE/PLLIN ILIM1 SENSE1– RUN2 40.2k 1% + RUN1 1nF COUT1 330µF s2 20k 1% 12.1k 1% TK/SS1 L2 0.56µH BOOST2 SW2 M4 BG2 CLKOUT PGND 3.09k 1% 0.1µF 20k, 1% DIFFOUT VFB2 ITH2 VFB1 ITH1 150pF M3 0.1µF SENSE2– ITEMP2 DIFFP DIFFN ITEMP1 VOUT1 1.8V 15A 82µF 25V FREQ ILIM2 SENSE2+ SENSE1+ 0.1µF VIN 4.5V TO 20V D4 VIN PGOOD EXTVCC INTVCC TG1 TG2 BOOST1 SW1 3.09k 1% 10µF 25V s2 1µF 2.2Ω + SGND 0.1µF 1nF TK/SS2 0.1µF 150pF 4.99k 1% 100k 1% VOUT2 1.2V 15A + 20k 1% COUT2 330µF s2 3855 F16 L1, L2: VISHAY IHLP4040DZ-01, 0.56µH M1, M3: RENESAS RJK0305DPB M2, M4: RENESAS RJK0330DPB Figure 16. High Efficiency Dual 400kHz 1.8V/1.2V Step-Down Converter The power loss in R1 at the maximum input voltage is: PLOSS R1= R1 The sum of the sense resistor and DCR is 2.5mΩ (max) for the RSENSE application whereas the inductor DCR for the DCR sense application is 1.8mΩ (max). As a result of the lower conduction losses from the switch node to VOUT, the DCR sensing application has higher efficiency. The power dissipation on the topside MOSFET can be easily estimated. Choosing a Renesas RJK0305DPB 1.8V RSENSE 1.8V DCR SENSE 5 4 EFFICIENCY 85 3 80 2 POWER LOSS (W) The resulting power loss for R1 is 11mW for channel 1 and 7mW for channel 2. VIN = 12V MODE = CCM 90 EFFICIENCY (%) 95 (VIN(MAX) − VOUT ) • VOUT POWER LOSS 75 70 1 1.2V RSENSE 1.2V DCR SENSE 0 2 4 6 8 10 12 LOAD CURRENT (A) DCR SENSE APP: SEE FIGURE 16 RSENSE APP: SEE FIGURE 19 14 16 0 3855 F17 Figure 17. DCR Sense Efficiency vs RSENSE Efficiency 3855f 33 LTC3855 Applications Information MOSFET results in: RDS(ON) = 13mΩ (max), VMILLER = 2.6V, CMILLER ≅ 150pF. At maximum input voltage with TJ (estimated) = 75°C: 1.8V 2 PMAIN = 15A ) [1+ (0.005)(75°C – 25°C)] • ( 20V (0.013Ω) + (20V )2 15A (2Ω)(150pF ) • 2 PSYNC = 1W For a 2mΩ sense resistor, a short-circuit to ground will result in a folded back current of: (1/ 3) 50mV – 1 90ns(20V) = 6.7A CIN is chosen for an RMS current rating of at least 7.5A at temperature assuming only channel 1 or 2 is on. COUT is chosen with an equivalent ESR of 4.5mΩ for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (∆IL) = 0.0045Ω • 6.8A = 31mVP–P Further reductions in output voltage ripple can be made by placing a 100µF ceramic across COUT. 2 0.56µH 0.002Ω 20V – 1.8V 2 15A ) • ( 20V 1+ ( 0.005) • ( 75°C – 25°C) • 0.0039Ω PSYNC = 1 1 5V – 2.6V + 2.6V ( 400kHz ) = 329mW + 288mW = 617mW ISC = A Renesas RJK0330DPB, RDS(ON) = 3.9mΩ, is chosen for the bottom FET. The resulting power loss is: Typical Applications 20k 20k 0.1µF ITH1 BOOST1 VFB1 PGND1 SGND 100pF 20k VFB2 L1 0.68µH CMDSH-3 2.2Ω PGOOD2 L1, L2: VISHAY IHLP5050CE-01, 0.68µH COUT1, COUT3: MURATA GRM32ER60J107ME20 COUT2, COUT4: KEMET T520V337M004ATE009 RNTC1, RNTC2: MURATA NCP18WF104J03RB COUT1 100µF 6.3V + COUT2 330µF 4V s2 VOUT1 2.5V 15A 4.7µF 0.1µF SW2 0.1µF CMDSH-3 100k 100k M4 RJK0330DPB L2 0.68µH 3.01k COUT3 100µF 6.3V 24.9k + COUT4 330µF 4V s2 VOUT2 1.8V 15A 3855 F18 Figure 18. 2.5V, 15A and 1.8V, 15A Supply with NTC Temperature Compensated DCR Sensing, fSW = 350kHz 34 VIN 4.5V TO 20V 82µF 25V s2 M2 RJK0330DPB M3 RJK0305DPB PGOOD1 3.01k + BOOST2 NC PGOOD2 PGOOD1 ILIM2 PGND2 ILIM1 SENSE2– RUN2 40.2k EXTVCC BG2 DIFFP 0.1µF 24.9k INTVCC SENSE2+ DIFFOUT 0.1µF 0.1µF VIN LTC3855 ITH2 DIFFN 1nF M1 RJK0305DPB BG1 TK/SS2 15k SW1 CLKOUT TG1 TG2 20k 100pF PHSASMD TK/SS1 1nF FREQ 63.4k ITEMP2 10µF s2 MODE/PLLIN 20k 86.6k RUN1 0.1µF 49.9k ITEMP1 RNTC1 100k SENSE1+ 49.9k SENSE1– RNTC2 100k 3855f LTC3855 Typical Applications 100Ω 100Ω 1nF 100k ITH1 BOOST1 VFB1 PGND1 SGND 150pF 20k VFB2 PGOOD1 PGOOD2 + M2 RJK0330DPB COUT2 330µF 2.5V s2 VOUT1 1.8V 15A 4.7µF 0.1µF SW2 BOOST2 NC PGOOD2 20k PGOOD1 100Ω ILIM2 PGND2 ILIM1 SENSE2– DIFFN 100Ω EXTVCC BG2 DIFFP 0.1µF COUT1 100µF 6.3V INTVCC SENSE2+ RUN2 1nF 2.2Ω VIN 4.5V TO 20V 82µF 25V s2 0.002Ω L1 0.4µH CMDSH-3 VIN LTC3855 ITH2 DIFFOUT 1.5nF 0.1µF BG1 TK/SS2 5.49k M1 RJK0305DPB SW1 CLKOUT FREQ ITEMP2 RUN1 PHSASMD TG1 100k TG2 20k 150pF MODE/PLLIN TK/SS1 ITEMP1 1nF SENSE1+ 18k SENSE1– 0.1µF + 10µF s2 40.2k 0.1µF CMDSH-3 M3 RJK0305DPB L2 0.4µH M4 RJK0330DPB 0.002Ω COUT3 100µF 6.3V + COUT4 330µF 2.5V s2 VOUT2 1.2V 15A 100k L1, L2: VITEC 59PR9875 COUT1, COUT3: MURATA GRM31CR60J107ME39L COUT2, COUT4: SANYO 2R5TPE330M9 3855 F19 Figure 19. 1.8V, 15A and 1.2V, 15A Supply, fSW = 400kHz 3855f 35 LTC3855 Typical Applications 100Ω BOOST1 VFB1 PGND1 100Ω PGOOD 100k TG2 SW2 RUN 100Ω 2.2Ω M2 RJK0330DPB s2 4.7µF COUT1 100µF 6.3V s4 0.1µF + COUT2 330µF 2.5V s4 VOUT 1.2V 40A BOOST2 NC PGOOD2 DIFFN DIFFP PGOOD1 PGND2 ILIM2 BG2 SENSE2– ILIM1 SENSE2+ RUN2 1nF EXTVCC DIFFOUT 5.9k 0.001Ω 1% INTVCC TK/SS2 100pF VIN 4.5V TO 14V 270µF 16V L1 0.44µH CMDSH-3 VIN LTC3855 ITH2 20k 0.1µF BG1 VFB2 2200pF M1 RJK0305DPB SW1 CLKOUT TG1 ITH1 SGND 20k + 10µF s4 PHSASMD ITEMP2 RUN1 250kHz ITEMP1 SENSE1+ TK/SS1 0.1µF SENSE1– RUN FREQ 1nF MODE/PLLIN 100Ω 0.1µF CMDSH-3 M3 RJK0305DPB L2 0.44µH 0.001Ω 1% M4 RJK0330DPB s2 L1, L2: PULSE PA0513.441NLT COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9 3855 F20 Figure 20. High Efficiency Dual Phase 1.2V, 40A Supply, fSW = 250kHz 3855f 36 LTC3855 Typical Applications 0.1µF + TG1 ITH1 BOOST1 VFB1 PGND1 SGND 2.2Ω M2 RJK0330DPB s2 4.7µF 1µF COUT1 100µF 6.3V s4 TG2 SW2 0.1µF COUT2 330µF 2.5V s4 VOUT 1.2V 40A CMDSH-3 M3 RJK0305DPB PGOOD + BOOST2 NC PGOOD2 DIFFN DIFFP PGOOD1 PGND2 ILIM2 BG2 SENSE2– ILIM1 SENSE2+ RUN2 0.1µF EXTVCC DIFFOUT 10k 3.92k INTVCC TK/SS2 330pF 20k VIN 4.5V TO 14V 270µF 16V L1 0.47µH CMDSH-3 VIN LTC3855 ITH2 3300pF 0.1µF BG1 VFB2 20k M1 RJK0305DPB SW1 CLKOUT PHSASMD FREQ MODE/PLLIN ITEMP2 ITEMP1 RUN1 SENSE1+ TK/SS1 0.1µF SENSE1– 10µF s4 100k M4 RJK0330DPB s2 L2 0.47µH 3.92k L1, L2: VISHAY IHLP5050FD-01, 0.47µH COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9 3855 F21 Figure 21. High Efficiency Dual Phase 1.2V, 40A Supply with DCR Sensing, fSW = 250kHz 3855f 37 LTC3855 Typical Applications 100Ω 100Ω 1nF 400kHz TG1 ITH1 BOOST1 VFB1 PGND1 SGND 100Ω 100Ω PGOOD 2.2Ω M2 RJK0330DPB s2 4.7µF 1µF COUT1 100µF 6.3V s2 + COUT2 330µF 2.5V s4 VOUT 0.9V 50A 100k TG2 SW2 BOOST2 NC PGOOD2 DIFFN DIFFP PGOOD1 PGND2 ILIM2 BG2 SENSE2– ILIM1 SENSE2+ RUN2 1nF EXTVCC DIFFOUT 5.1k 0.001Ω 1% INTVCC TK/SS2 220pF 20k VIN 4.5V TO 14V 270µF 16V L1 0.23µH CMDSH-3 VIN LTC3855 ITH2 2700pF 0.1µF BG1 VFB2 10k M1 RJK0305DPB s2 SW1 CLKOUT PHSASMD FREQ MODE/PLLIN ITEMP2 RUN1 ITEMP1 SENSE1+ SENSE1– TK/SS1 0.1µF + 10µF s4 100k 0.1µF CMDSH-3 M3 RJK0305DPB s2 L2 0.23µH 0.001Ω 1% M4 RJK0330DPB s2 L1, L2: VITEC 59PR9873 COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9 3855 F22 Figure 22. Small Size, Dual Phase 0.9V, 50A Supply, fSW = 400kHz 3855f 38 LTC3855 Typical Applications 100Ω 13.3k VFB1 PGND1 SGND BG1 VFB2 VIN LTC3855 SENSE2– CMDSH-3 2.2Ω 4.7µF 1µF SW2 0.1µF M3 RJK0305DPB L2 0.3µH CMDSH-3 PGOOD1V 100k BOOST1 VFB1 PGND1 EXTVCC SENSE2+ SENSE2– 4.7µF 1µF 10µF TG2 SW2 BOOST2 NC PGOOD2 PGOOD1 ILIM2 PGND2 ILIM1 DIFFN DIFFP RUN2 0.1µF M6 RJK0330DPB BG2 DIFFOUT 10k 2.2Ω INTVCC TK/SS2 100pF L3 0.3µH CMDSH-3 VIN LTC3855 ITH2 0.1µF VOUT1 1V 50A 0.002Ω 1% 0.1µF BG1 VFB2 3300pF COUT2 470µF 2.5V s4 M5 RJK0305DPB SW1 CLKOUT PHSASMD MODE/PLLIN FREQ ITEMP2 ITEMP1 RUN1 SENSE1+ SENSE1– TG1 ITH1 SGND 20k + 100k RUN1 90.9k COUT1 100µF 6.3V s3 100Ω 1nF TK/SS1 0.002Ω 1% M4 RJK0330DPB 100Ω 100Ω M2 RJK0330DPB BOOST2 NC PGOOD2 PGOOD1 ILIM2 ILIM1 RUN2 DIFFN L1 0.3µH RUN1 100Ω 0.002Ω 1% PGND2 DIFFOUT DIFFP VIN 4.5V TO 14V BG2 TG2 1nF 2k 0.1µF 270µF 16V INTVCC EXTVCC SENSE2+ 330pF M1 RJK0305DPB SW1 CLKOUT PHSASMD FREQ RUN1 BOOST1 TK/SS2 4700pF 20k TG1 ITH1 ITH2 + 10µF s3 100k ITEMP1 SENSE1+ TK/SS1 0.1µF SENSE1– RUN1 MODE/PLLIN 1nF ITEMP2 100Ω 0.1µF CMDSH-3 M7 S4816BDY L4 2.2µH RUN2 PGOOD3.3V 100k COUT3 100µF 6.3V 2.49k VOUT2 3.3V 5A 4.99k 3855 F23 L1, L2, L3: VITEC 59PR9874 L4: WURTH 744311220 COUT1, COUT3: TDK C3225X5R0J107M COUT2: KEMET T530D477M2R5ATE006 Figure 23. Triple Phase 1V, 50A Supply with Auxillary 3.3V, 5A Rail, fSW = 400kHz 3855f 39 LTC3855 Typical Applications VIN 7V TO 24V 22µF 50V 2.2Ω 1µF Si4816BDY 4.7µF D3 M1 0.1µF L2 2.2µH TG1 BOOST1 SW1 BG1 10Ω 10Ω 15pF + 90.9k 1% COUT1 220µF MODE/PLLIN ILIM SENSE1+ M2 0.1µF 20k 1% 1000pF 100pF 10k 1% L2 3.3µH BOOST2 SW2 BG2 CLKOUT PGND FREQ SENSE2+ 10Ω 1000pF 8mΩ VOUT1 3.3V 5A TG2 LTC3855 Si4816BDY D4 VIN PGOOD INTVCC 1000pF SENSE1– SENSE2– RUN1 DIFFP RUN2 DIFFN EXTVCC DIFFOUT VFB2 VFB1 ITH2 ITH1 TK/SS1 SGND TK/SS2 0.1µF 0.1µF 8mΩ 10Ω 10pF 147k 1% 1000pF 122k 1% 15k 1% 100pF 20k 1% VOUT2 5V 5A + COUT2 150µF 3855 F24 L1: TDK RLF 7030T-2R2M5R4 L2: TDK ULF10045T-3R3N6R9 COUT1: SANYO 4TPE220MF COUT2: SANYO 6TPE150MI Figure 24. 3.3V/5A, 5V/5A Converter Using Sense Resistors 3855f 40 LTC3855 Typical Applications 0.1µF 383k ITH1 BOOST1 VFB1 PGND1 SGND 47pF 20k VFB2 INTVCC EXTVCC SENSE2+ 0.1µF + M2 BSC093N040LS COUT1 39µF 16V s2 VOUT1 12V 6A 4.7µF 0.1µF SW2 BOOST2 NC PGOOD2 PGOOD1 ILIM2 ILIM1 147k RUN2 0.1µF VIN 13V TO 38V PGND2 DIFFOUT DIFFP 100µF 50V 18k L1 13µH 2.2Ω BG2 SENSE2– 24k + CMDSH-3 VIN LTC3855 ITH2 DIFFN 5.6nF 0.1µF BG1 TK/SS2 4.99k M1 BSC093N040LS SW1 CLKOUT FREQ ITEMP2 RUN1 PHSASMD TG1 TG2 20k 47pF MODE/PLLIN TK/SS1 ITEMP1 5.6nF SENSE1+ 10k 4.7µF s6 SENSE1– 0.1µF 0.1µF CMDSH-3 M3 BSC093N040LS PGOOD1 PGOOD2 100k M4 BSC093N040LS 100k L2 3.7µH + 8.2k 24k COUT2 39µF 16V s2 VOUT2 5V 10A 3855 F25 L1: WURTH 7443551131 L2: WURTH 7443551370 COUT1, COUT2: SANYO 16SVPC39MV Figure 25. 12V, 6A and 5V, 10A Supply with DCR Sensing, fSW = 250kHz 3855f 41 LTC3855 Package Description FE Package 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1772 Rev A) Exposed Pad Variation AA 4.75 REF 38 9.60 – 9.80* (.378 – .386) 4.75 REF (.187) 20 6.60 ±0.10 4.50 REF 2.74 REF SEE NOTE 4 6.40 2.74 REF (.252) (.108) BSC 0.315 ±0.05 1.05 ±0.10 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN MILLIMETERS (INCHES) 3. DRAWING NOT TO SCALE 1 0.25 REF 19 1.20 (.047) MAX 0o – 8o 0.50 (.0196) BSC 0.17 – 0.27 (.0067 – .0106) TYP 0.05 – 0.15 (.002 – .006) FE38 (AA) TSSOP 0608 REV A 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3855f 42 LTC3855 Package Description UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.42 ±0.05 4.50 ±0.05 (4 SIDES) 4.42 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 ±0.10 2 PIN 1 NOTCH R = 0.45 OR 0.35 s 45° CHAMFER 4.42 ±0.10 (UJ40) QFN REV Ø 0406 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 3855f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 43 LTC3855 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ VIN ≤ 24V, VOUT3 Up to 13.5V LTC3731 3-Phase Synchronous Controller, Expandable to 12 phases Differential Amp, High Output Current 60A to 240A Phase-Lockable Fixed 250kHz to 600kHz Frequency, 0.6V ≤ VOUT ≤ 5.25V, 4.5V ≤ VIN ≤ 32V, LTC3850/ LTC3850-1/ LTC3850-2 Dual 2-Phase, High Efficiency Synchronous Step-Down DC/ Phase-Lockable Fixed 250kHz to 780kHz Frequency, 4V ≤ VIN ≤ 30V, DC Controller, RSENSE or DCR Current Sensing and Tracking 0.8V ≤ VOUT ≤ 5.25V LTC3854 Small Footprint Wide VIN Range Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing LTC3851A/ LTC3851A-1 No RSENSE™ Wide VIN Range Synchronous Step-Down DC/ Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ VIN ≤ 38V, DC Controller, RSENSE or DCR Current Sensing and Tracking 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16 LTC3878 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Controller, No RSENSE Required Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16 LTC3879 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Controller, No RSENSE Required Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16 LTM4600HV 10A DC/DC µModule® Complete Power Supply High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTM4601AHV 12A DC/DC µModule Complete Power Supply High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ VIN ≤ 28V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTC3610 12A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time 4V ≤ VIN ≤ 24V, VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 LTC3611 10A, 1MHz, Monolithic Synchronous Step-Down DC/DC Converter High Efficiency, Adjustable Constant On-Time 4V ≤ VIN ≤ 32V, VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 LTC3857/ LTC3857-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA LTC3868/ LTC3868-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 24V, 0.8V ≤ VOUT ≤ 14V, IQ = 170µA, LT3845 Low IQ, High Voltage Synchronous Step-Down DC/DC Controller Adjustable Fixed Operating Frequency 100kHz to 500kHz, 4V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, IQ = 30µA, TSSOP-16 Fixed 400kHz Operating Frequency 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, 2mm × 3mm QFN-12 No RSENSE is a trademark of Linear Technology Corporation. µModule is a registered trademark of Linear Technology Corporation. 3855f 44 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 1009 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2009