® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 REVISION HISTORY Revision Rev. 1.0. Rev. 2.0. Rev. 2.1. Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Rev. 2.6 Rev. 2.7 Rev. 2.8 Rev. 2.9 Description Initial Issue Revised Vcc Range(Vcc=4.5~5.5V => 2.7~5.5V) Revised ISB1 Adding PKG type : skinny P-DIP Revised VIH(min)=2.4V, VIL(max)=0.6V Revised VIH(min)=2.4V, VIL(max)=0.6V (VCC=2.7~3.6V) VIH(min)=2.4V, VIL(max)=0.8V (VCC=4.5~5.5V) Revised STSOP Package Outline Dimension Added SL grade Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Revised ISB1(MAX) Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Revised PACKAGE OUTLINE DIMENSION in page 8 & 9 Revised PACKAGE OUTLINE DIMENSION in page 10 Revised ORDERING INFORMATION in page 12 Revised PACKAGE OUTLINE DIMENSION in page 9 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Issue Date Jul.25.2004 May.4.2005 May.13.2005 Aug.29.2005 Feb.24.2006 Jul.31.2006 Mar.26.2008 Mar.30.2009 Dec.18.2009 May.7.2010 Aug.25.2010 ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 FEATURES GENERAL DESCRIPTION Fast access time : 35/55/70ns Low power consumption: Operating current : 20/15/10mA (TYP.) Standby current : 1μA (TYP.) Single 2.7~5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.5V (MIN.) Green package available Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mm x 13.4mm STSOP 28-pin 300 mil Skinny P-DIP The LY62256 is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62256 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY62256 operates from a single power supply of 2.7~5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY62256 LY62256(E) LY62256(I) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ Vcc Range Speed 2.7 ~ 5.5V 2.7 ~ 5.5V 2.7 ~ 5.5V 35/55/70ns 35/55/70ns 35/55/70ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A14 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# WE# OE# CONTROL CIRCUIT Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 1µA 20/15/10mA 1µA 20/15/10mA 1µA 20/15/10mA 32Kx8 MEMORY ARRAY SYMBOL DESCRIPTION A0 - A14 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground COLUMN I/O Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 PIN CONFIGURATION 1 28 Vcc A12 2 27 WE# A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 LY62256 A14 23 A11 22 OE# 21 A10 20 CE# A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 Vss 14 15 DQ3 OE# A11 A9 A8 A13 WE# Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LY62256 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 STSOP Skinny P-DIP/P-DIP/SOP ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L I/O OPERATION High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage Input High Voltage SYMBOL VCC *1 VIH Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage *2 VIL ILI ILO VOH VOL ICC Average Operating Power supply Current ICC1 ISB Standby Power Supply Current ISB1 TEST CONDITION VCC=2.7~3.6V VCC=4.5~5.5V VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -1mA IOL = 2mA -35 Cycle time = Min. CE# = VIL , II/O = 0mA -55 Other pins at VIL or VIH -70 Cycle time = 1µs CE#≦0.2V and II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH, other pins at VIL or VIH LL LLE/LLI *5 SL CE# ≧VCC-0.2V 25℃ *5 SLE Others at 0.2V or *5 40℃ SLI VCC - 0.2V SL SLE/SLI MIN. 2.7 2.4 - 0.5 - 0.5 -1 TYP. 3.3 - *4 MAX. 5.5 VCC+0.5 0.6 0.8 1 UNIT V V V V µA -1 - 1 µA 2.4 - 3.0 20 15 10 0.4 50 45 40 V V mA mA mA - 3 10 mA - 1 1 1 3 20 30 mA µA µA - 1 3 µA - 1.5 4 µA - 1 1 10 20 µA µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ 5. This parameter is measured at VCC = 3.0V CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 UNIT pF pF ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* LY62256-35 MIN. MAX. 35 35 35 25 10 5 15 15 10 - LY62256-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 - LY62256-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 - UNIT LY62256-35 MIN. MAX. 35 30 30 0 25 0 20 0 5 15 LY62256-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 LY62256-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 UNIT *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 High-Z ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout High-Z (4) tDW tDH Data Valid Din Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V LL/LLE/LLI SL 25℃ VCC = 1.5V SLE CE# ≧ VCC - 0.2V IDR SLI 40℃ Others at 0.2V or VCC-0.2V SL SLE/SLI See Data Retention tCDR Waveforms (below) tR MIN. 1.5 - TYP. 0.5 MAX. 5.5 20 - 0.5 2 - 1 3 - 0.5 0.5 8 15 µA µA µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≧ 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 UNIT V µA µA ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 PACKAGE OUTLINE DIMENSION 28 pin 600 mil PDIP Package Outline Dimension UNIT SYM. A1 A2 B B1 c D E E1 e eB L S Q1 Θ INCH.(BASE) 0.015(MIN) 0.155±0.005 0.020(MAX) 0.060(TYP) 0.012(MAX) 1.470(MAX) 0.6(TYP) 0.55(MAX) 0.100(TYP) 0.650±0.020 0.200(MAX) 0.06(MAX) 0.08(MAX) o 15 (MAX) MM(REF) 0.381(MIN) 3.937±0.127 0.508(MAX) 1.524(TYP) 0.304(MAX) 37.338(MAX) 15.24(TYP) 13.970(MAX) 2.540(TYP) 16.510±0.508 5.080(MAX) 1.524(MAX) 2.032(MAX) o 15 (MAX) Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 28 pin 330 mil SOP Package Outline Dimension UNIT SYM. A A1 A2 b c D E E1 e L L1 S y Θ INCH(BASE) 0.120(MAX) 0.002(MIN) 0.098±0.005 0.016(TYP) 0.010(TYP) 0.728(MAX) 0.340(MAX) 0.465±0.012 0.050(TYP) 0.038(MAX) 0.067±0.008 0.047(MAX) 0.004(MAX) o o 0 ～10 MM(REF) 3.048(MAX) 0.05(MIN) 2.489±0.127 0.406(TYP) 0.254(TYP) 18.491(MAX) 8.636(MAX) 11.811±0.305 1.270(TYP) 0.965(MAX) 1.702 ±0.203 1.194(MAX) 0.102(MAX) o o 0 ～10 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY62256 32K X 8 BIT LOW POWER CMOS SRAM Rev. 2.9 28 pin 8x13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 28 14 15 12° (2x) b E e 1 "A" y Seating Plane D 12° (2X) 14 15 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE 12° (2X) L 1 28 SYMBOLS A A1 A2 b c HD D E e L L1 Y Θ "A" DATAIL VIEW DIMENSIONS IN MILLIMETERS MIN NOM MAX 1.00 1.10 1.20 0.05 0.15 0.91 1.00 1.05 0.17 0.22 0.27 0.07 0.15 0.23 13.20 13.40 13.60 11.60 11.80 12.00 7.80 8.00 8.20 0.55 0.30 0.50 0.70 0.675 0.00 0.076 0° 3° 5° DIMENSIONS IN INCHES MIN NOM MAX 0.040 0.043 0.047 0.002 0.006 0.036 0.039 0.041 0.007 0.009 0.011 0.003 0.006 0.009 0.520 0.528 0.535 0.457 0.465 0.472 0.307 0.315 0.323 0.0216 0.012 0.020 0.028 0.027 0.000 0.003 0° 3° 5° Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 L1 ® LY62256 Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM 28 pin 300 mil PDIP Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY62256 Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12 ® LY62256 Rev. 2.9 32K X 8 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 13