Product Brief Integrated Circuit Systems, Inc. M2006-02/-12 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION PIN ASSIGNMENT (9 x 9 mm SMT) 27 26 25 24 23 22 21 20 19 FIN_SEL1 GND The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables. NC or APC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC GENERAL DESCRIPTION FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC DNC DNC 18 17 16 15 14 13 12 11 10 M2006-02 M2006-12 (Top View) GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN This phase-change triggered implementation of HS is not recommended when using an unstable reference (more than 1ns jitter pk-to-pk) or when the resulting phase detector frequency is less than 5MHz. Refer to full product data sheet for more information. Example I/O Clock Frequency Combinations Using M2006-02/-12-622.0800 and Inverse FEC Ratios FEATURES FEC PLL Ratio Mfec / Rfec • Pin-selectable PLL divider ratios support forward Base Input Rate 1 (MHz) and inverse FEC ratio translation, including: 1/1 238/255 237/255 236/255 • 255/238 (OTU1) Mapping and 238/255 De-mapping • 255/237 (OTU2) Mapping and 237/255 De-mapping • 255/236 (OTU3) Mapping and 236/255 De-mapping • Supports input reference and VCSO frequencies up • • • • • P0_SEL P1_SEL nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND 1 2 3 4 5 6 7 8 9 The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected. 28 29 30 31 32 33 34 35 36 to 700MHz, supports loop timing modes (Specify VCSO frequency at time of order) Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz) M2006-12 includes APC pin for Phase Build-out function (for absorption of the input phase change) Commercial and Industrial temperature grades Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package 622.0800 666.5143 669.3266 672.1627 Output Clock (either output) MHz 622.08 or 155.52 Note 1: Input reference clock can be the base frequency shown divided by “Mfin”, as shown in the following table. Mfin Divider and Example Input Frequencies Mfin Value FIN_SEL1:0 1 1 0 0 1 0 1 0 1 4 8 32 For Base Input Rate of 622.0800 Sample Ref. Freq. (MHz) 622.08 155.52 77.76 19.44 SIMPLIFIED BLOCK DIAGRAM Loop Filter M2006-02 / M2006-12 APC M2006-12 only DIF_REF0 0 nDIF_REF0 Rfec Div DIF_REF1 Mfec Div REF_SEL FIN_SEL1:0 (1 or 4) nFOUT0 1 nDIF_REF1 FEC_SEL3:0 FOUT0 P0 Div VCSO 4 Mfin Div (1, 4, 8, or 32) Mfec / Rfec Divider LUT FOUT1 P1 Div (1 or 4) 2 nFOUT1 Mfin Divider LUT P0_SEL P1_SEL M2006-02/-12 PB Rev 2.2 Revised 06Jul2004 M2006-02/-12 VCSO Based FEC Clock PLL / Hitless Switching Integrated Circuit Systems, Inc. ● Networking & Communications ● w w w. i c s t . c o m ● tel (508) 852-5400