STMICROELECTRONICS M24C04

M24C16, M24C08
M24C04, M24C02, M24C01
16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I²C bus EEPROM
Features
■
Supports both the 100 kHz I2C Standard-mode
and the 400 kHz I2C Fast-mode
■
Single supply voltage:
– 2.5 V to 5.5 V for M24Cxx-W
– 1.8 V to 5.5 V for M24Cxx-Rev 16
– 1.7 V to 5.5 V for M24Cxx-F
PDIP8 (BN)
■
Write Control input
■
Byte and Page Write (up to 16 bytes)
■
Random and Sequential Read modes
■
Self-timed programming cycle
■
Automatic address incrementing
■
Enhanced ESD/latch-up protection
■
More than 1 million write cycles
■
More than 40-year data retention
■
Packages:
– SO8, TSSOP8, UFDFPN8: ECOPACK2®
(RoHS-compliant and Halogen-free)
– PDIP8: ECOPACK1® (RoHS-compliant)
Table 1.
SO8 (MN)
150 mils width
TSSOP8 (DW)
169 mils width
Device summary
Reference
UFDFPN8 (MB, MC)
2 × 3 mm (MLP)
Part number
M24C16-W
M24C16
M24C16-R
M24C16-F
WLCSP (CS)(1)
Thin WLCSP (CT)(2)
M24C08-W
M24C08
M24C08-R
M24C08-F
M24C04
M24C04-W
1. Only M24C08-F and M24C16-F devices are offered in
the WLCSP package.
M24C04-R
2. Only M24C08-F devices are offered in the Thin
WLCSP package.
M24C04-F
M24C02
M24C01
April 2010
M24C02-W
M24C02-R
M24C01-W
M24C01-R
Doc ID 5067 Rev 16
1/39
www.st.com
1
Contents
M24C16, M24C08, M24C04, M24C02, M24C01
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1
2.4
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.1
3
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7
3.6.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.3
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 15
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.1
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.2
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.4
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/39
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Contents
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 5067 Rev 16
3/39
List of tables
M24C16, M24C08, M24C04, M24C02, M24C01
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/39
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions (M24Cxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC characteristics (M24Cxx-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC characteristics (M24Cxx-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics (M24Cxx-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R,
M24Cxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC characteristics at 100 kHz (I2C Standard-mode) (M24Cxx-W,
M24Cxx-R, M24Cxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M24C08: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data . . . . . . . . . . . . 26
M24C08: Thin WLCSP (0.3 mm height), 0.4 mm pitch, 5 bumps, package data . . . . . . . . 27
M24C16: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data . . . . . . . . . . . . 27
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30
PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 31
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Available M24C16 products (package, voltage range, temperature grade) . . . . . . . . . . . . 33
Available M24C08 products (package, voltage range, temperature grade) . . . . . . . . . . . . 33
Available M24C04 products (package, voltage range, temperature grade) . . . . . . . . . . . . 33
Available M24C02 products (package, voltage range, temperature grade) . . . . . . . . . . . . 34
Available M24C01 products (package, voltage range, temperature grade) . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
M24C08-F WLCSP and thin WLCSP connections
(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum RP value versus bus parasitic capacitance (C) for an I²C bus . . . . . . . . . . . . . . 9
I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
WLCSP (0.5 mm) and Thin WLCSP (0.3 mm) 0.4 mm pitch 5 bumps,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 28
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30
PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 31
Doc ID 5067 Rev 16
5/39
Description
1
M24C16, M24C08, M24C04, M24C02, M24C01
Description
These I²C-compatible electrically erasable programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08, M24C04, M24C02 and
M24C01).
Figure 1.
Logic diagram
VCC
3
E0-E2
SDA
M24Cxx
SCL
WC
VSS
AI02033
I²C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C
bus definition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Table 2.
Signal names
Signal name
6/39
Function
Direction
E0, E1, E2
Chip Enable
Input
SDA
Serial Data
Input/output
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 2.
Description
8-pin package connections (top view)
M24Cxx
16Kb /8Kb /4Kb /2Kb /1Kb
NC / NC / NC / E0 / E0 1
8 VCC
NC / NC / E1 / E1 / E1 2
7 WC
NC / E2 / E2 / E2 / E2 3
6 SCL
VSS 4
5 SDA
AI02034E
1. NC = Not connected
2. See Section 7: Package mechanical data for package dimensions, and how to identify pin-1.
Figure 3.
M24C08-F WLCSP and thin WLCSP connections
(top view, marking side, with balls on the underside)
VCC
WC
SDA
SCL
VSS
ai14908
Doc ID 5067 Rev 16
7/39
Signal description
M24C16, M24C08, M24C04, M24C02, M24C01
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor can be connected from Serial Clock
(SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-ORed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how
the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code as shown in Figure 4. When not connected (left
floating), E0, E1, E2 are read as low (0,0,0).
Figure 4.
Device select code
VCC
VCC
M24Cxx
M24Cxx
Ei
Ei
VSS
VSS
Ai11650
2.3.1
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, device select and address bytes are
acknowledged, data bytes are not acknowledged.
8/39
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
2.4
Supply voltage (VCC)
2.4.1
Operating supply voltage VCC
Signal description
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 6, Table 7 and
Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the
VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.4.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 6, Table 7 and Table 8 and the rise time must not vary faster than 1 V/µs.
2.4.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC reaches the power-on-reset threshold voltage (this threshold is lower
than the minimum VCC operating voltage defined in Table 6, Table 7 and Table 8). When
VCC passes over the POR threshold, the device is reset and enters the Standby Power
mode. The device, however, must not be accessed until VCC reaches a valid and stable VCC
voltage within the specified [VCC(min), VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power-on-reset threshold voltage, the device stops responding to any instruction
sent to it.
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
Figure 5.
Maximum RP value versus bus parasitic capacitance (C) for an I²C bus
100
Bus line pull-up resistor
(k )
2.4.4
10
4 kΩ
When tLOW = 1.3 µs (min value for
fC = 400 kHz), the Rbus × Cbus
time constant must be below the
400 ns time constant line
represented on the left.
R
bu
s ×
C
bu
s =
Here Rbus × Cbus = 120 ns
40
VCC
Rbus
0n
s
I²C bus
master
SCL
M24xxx
SDA
1
30 pF
10
100
Bus line capacitor (pF)
1000
Cbus
ai14796b
Doc ID 5067 Rev 16
9/39
Signal description
Figure 6.
M24C16, M24C08, M24C04, M24C02, M24C01
I²C bus protocol
SCL
SDA
SDA
Input
Start
condition
SCL
1
2
SDA
MSB
SDA
Change
Stop
condition
3
7
8
9
ACK
Start
condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
Stop
condition
AI00792c
Table 3.
Device select code
Device type identifier(1)
Chip Enable(2),(3)
b7
b6
b5
b4
b3
b2
b1
b0
M24C01 select code
1
0
1
0
E2
E1
E0
RW
M24C02 select code
1
0
1
0
E2
E1
E0
RW
M24C04 select code
1
0
1
0
E2
E1
A8
RW
M24C08 select code
1
0
1
0
E2
A9
A8
RW
M24C16 select code
1
0
1
0
A10
A9
A8
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.
10/39
RW
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
3
Device operation
Device operation
The device supports the I²C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communication.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
Doc ID 5067 Rev 16
11/39
Device operation
3.5
M24C16, M24C08, M24C04, M24C02, M24C01
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 3 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the
device select code is received, the device only responds if the Chip Enable Address is the
same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with
larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0
is not available for use on devices that need to use address line A8; E1 is not available for
devices that need to use address line A9, and E2 is not available for devices that need to
use address line A10 (see Figure 2 and Table 3 for details). Using the E0, E1 and E2 inputs,
up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can
be connected to one I²C bus. In each case, and in the hybrid cases, this gives a total
memory capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used).
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 4.
Operating modes
Mode
Current Address Read
RW bit
WC(1)
Bytes
1
X
1
0
X
Random Address Read
Start, Device Select, RW = 1
Start, Device Select, RW = 0, Address
1
1
X
reStart, Device Select, RW = 1
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
Start, Device Select, RW = 0
Page Write
0
VIL
≤16
Start, Device Select, RW = 0
1. X = VIH or VIL.
12/39
Initial sequence
Doc ID 5067 Rev 16
Similar to Current or Random Address
Read
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 7.
Device operation
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
Byte address
NO ACK
Data in
Stop
Dev select
Start
Byte Write
ACK
R/W
WC
ACK
Dev select
Start
Page Write
ACK
Byte address
NO ACK
Data in 1
NO ACK
Data in 2
Data in 3
R/W
WC (cont'd)
NO ACK
Data in N
Stop
Page Write
(cont'd)
NO ACK
AI02803d
3.6
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte’s Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal write
cycle.
During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and
the device does not respond to any requests.
3.6.1
Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High (during
the period from the Start condition until the end of the address byte), the device replies to
the data byte with NoAck, as shown in Figure 7, and the location is not modified. If, instead,
Doc ID 5067 Rev 16
13/39
Device operation
M24C16, M24C08, M24C04, M24C02, M24C01
the addressed location is not Write-protected, the device replies with Ack. The bus master
terminates the transfer by generating a Stop condition, as shown in Figure 8.
3.6.2
Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write
Control (WC) being driven High (during the period from the Start condition until the end of
the address byte), the device replies to the data bytes with NoAck, as shown in Figure 7,
and the locations are not modified. After each byte is transferred, the internal byte address
counter (the 4 least significant address bits only) is incremented. The transfer is terminated
by the bus master generating a Stop condition.
Figure 8.
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
Byte address
ACK
Data in
Stop
Dev Select
Start
Byte Write
ACK
R/W
WC
ACK
Dev Select
Start
Page Write
ACK
Byte address
ACK
Data in 1
ACK
Data in 2
Data in 3
R/W
WC (cont'd)
ACK
Data in N
Stop
Page Write
(cont'd)
ACK
14/39
Doc ID 5067 Rev 16
AI02804c
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9.
Device operation
Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
operation is
addressing the
memory
YES
Send Address
and Receive ACK
ReStart
NO
Stop
Start
condition
YES
Data for the
Write operation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847d
3.6.3
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 15, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 9, is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Doc ID 5067 Rev 16
15/39
Device operation
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 10. Read mode sequences
ACK
Data out
Stop
Start
Dev select
R/W
ACK
Start
Dev select *
ACK
Byte address
R/W
ACK
Sequentila
Current
Read
Dev select *
NO ACK
Data out
R/W
ACK
ACK
Data out 1
NO ACK
Data out N
Stop
Start
Dev select
R/W
ACK
Start
Dev select *
ACK
Byte address
R/W
ACK
ACK
Dev select *
Start
Sequential
Random
Read
ACK
Start
Random
Address
Read
Stop
Current
Address
Read
NO ACK
ACK
Data out 1
R/W
NO ACK
Stop
Data out N
AI01942b
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 3rd bytes) must
be identical.
3.7
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
The device has an internal address counter which is incremented each time a byte is read.
3.7.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
16/39
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
3.7.2
Device operation
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
3.7.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.7.4
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Standby mode.
Doc ID 5067 Rev 16
17/39
Initial delivery state
4
M24C16, M24C08, M24C04, M24C02, M24C01
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE program and other relevant
quality documents.
Table 5.
Absolute maximum ratings
Symbol
TA
TSTG
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
Lead temperature during soldering
TLEAD
PDIP-specific lead temperature during soldering
IOL
DC output current (SDA = 0)
VIO
Input or output range
VCC
Supply voltage
VESD
see note
Electrostatic discharge voltage (human body
model)(3)
260
(2)
-
5
mA
–0.50
6.5
V
–0.50
6.5
V
–4000
4000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. TLEAD max must not be applied for more than 10 s.
3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
18/39
Doc ID 5067 Rev 16
°C
M24C16, M24C08, M24C04, M24C02, M24C01
6
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 6.
Operating conditions (M24Cxx-W)
Symbol
VCC
TA
Table 7.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (M24Cxx-R)
Symbol
VCC
TA
Table 8.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
1.7
5.5
V
Ambient operating temperature
–20
85
°C
Operating conditions (M24Cxx-F)
Symbol
VCC
TA
Parameter
Doc ID 5067 Rev 16
19/39
DC and AC parameters
Table 9.
M24C16, M24C08, M24C04, M24C02, M24C01
DC characteristics (M24Cxx-W, device grade 6)
Symbol
Test conditions (in addition to those in
Table 6)
Parameter
ILI
Input leakage current
V = VSS or VCC, device in Standby mode
(SCL, SDA, E0, E1,and E2) IN
ILO
Output leakage current
ICC
Min.
Max. Unit
±2
µA
SDA in Hi-Z, external voltage applied on
SDA: VSS or VCC
±2
µA
VCC = 5 V, fc = 400 kHz
(rise/fall time < 50 ns)
2
mA
VCC = 2.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
1
mA
Device not selected(1), VIN = VSS or VCC,
for 2.5 V < VCC ≤ 5.5 V
1
µA
Supply current
ICC1
Standby supply current
VIL
Input low voltage (SDA,
SCL, WC)
–0.45 0.3VCC
V
VIH
Input high voltage (SDA,
SCL, WC)
0.7VCC VCC+1
V
VOL
Output low voltage
IOL = 2.1 mA when VCC = 2.5 V or
IOL = 3 mA when VCC = 5.5 V
0.4
V
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).
Table 10.
DC characteristics (M24Cxx-W, device grade 3)
Symbol
Parameter
Test condition
(in addition to those in Table 6)
ILI
Input leakage current (SCL,
SDA, E0, E1,and E2)
ILO
Output leakage current
ICC
ICC1
Min.
Max.
Unit
VIN = VSS or VCC, device in
Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 5 V, fC= 400 kHz
(rise/fall time < 50 ns)
3
mA
VCC = 2.5 V, fC = 400 kHz
(rise/fall time < 50 ns)
3
mA
Device not selected(1), VIN = VSS
or VCC, VCC = 5 V
5
µA
Device not selected(1), VIN = VSS
or VCC, VCC = 2.5 V
2
µA
Supply current
Standby supply current
VIL
Input low voltage (SDA,
SCL, WC)
–0.45
0.3VCC
V
VIH
Input high voltage (SDA,
SCL, WC)
0.7VCC
VCC+1
V
VOL
Output low voltage
0.4
V
IOL = 2.1 mA when VCC = 2.5 V or
IOL = 3 mA when VCC = 5.5 V
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).
20/39
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Table 11.
DC and AC parameters
DC characteristics (M24Cxx-R)
Symbol
Parameter
Test condition
(in addition to those in Table 7)
ILI
Input leakage current
(SCL, SDA, E0, E1,and E2)
ILO
Output leakage current
ICC
Supply current
ICC1
Standby supply current
VIL
Input low voltage (SDA,
SCL, WC)
VIH
Input high voltage (SDA,
SCL, WC)
VOL
Output low voltage
Min.
Max.
Unit
VIN = VSS or VCC, device in
Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.8 V, fc= 400 kHz
(rise/fall time < 50 ns)
0.8
mA
Device not selected(1), VIN = VSS
or VCC, VCC = 1.8 V
1
µA
2.5 V ≤ VCC
–0.45
0.3 VCC
V
1.8 V ≤VCC < 2.5 V
–0.45
0.25 VCC
V
0.7VCC
VCC+1
V
0.2
V
IOL = 0.7 mA, VCC = 1.8 V
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).
Doc ID 5067 Rev 16
21/39
DC and AC parameters
Table 12.
M24C16, M24C08, M24C04, M24C02, M24C01
DC characteristics (M24Cxx-F)
Symbol
Test condition
(in addition to those in Table 8)
Parameter
ILI
Input leakage current (SCL, SDA,
E0, E1,and E2)
ILO
Output leakage current
ICC
Supply current
ICC1
Standby supply current
VIL
Input low voltage (SDA, SCL, WC)
VIH
Input high voltage (SDA, SCL, WC)
VOL
Output low voltage
Min.
Max.
Unit
VIN = VSS or VCC, device in Standby
mode
±2
µA
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC = 1.7 V, fc= 400 kHz
(rise/fall time < 50 ns)
0.8
mA
Device not selected(1), VIN = VSS or
VCC, VCC = 1.7 V
1
µA
2.5 V ≤VCC
–0.45
0.3 VCC
V
1.7 V ≤VCC < 2.5 V
–0.45
0.25 VCC
V
0.7VCC
VCC+1
V
0.2
V
IOL = 0.7 mA, VCC = 1.7 V
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the completion of the
internal write cycle tW (tW is triggered by the correct decoding of a write command).
Table 13.
AC measurement conditions
Symbol
Cbus
Parameter
Min.
Load capacitance
Max.
100
SCL input rise/fall time, SDA input fall time
Unit
pF
50
ns
Input levels
0.2VCC to 0.8VCC
V
Input and output timing reference levels
0.3VCC to 0.7VCC
V
Figure 11. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 14.
Input parameters
Parameter(1)
Symbol
Test condition
Min.
Unit
CIN
Input capacitance (SDA)
8
pF
CIN
Input capacitance (other pins)
6
pF
70
kΩ
ZWCL
WC input impedance
VIN < 0.3 V
15
ZWCH
WC input impedance
VIN > 0.7VCC
500
Pulse width ignored (input filter on
SCL and SDA)
Single glitch
tNS
1. Characterized only.
22/39
Max.
Doc ID 5067 Rev 16
kΩ
100
ns
M24C16, M24C08, M24C04, M24C02, M24C01
Table 15.
DC and AC parameters
AC characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R,
M24Cxx-F)
Test conditions specified in either Table 6, Table 7 or Table 8 and Table 13
Max.(1)
Unit
400
kHz
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
Clock pulse width high
600
ns
tCLCH
tLOW
Clock pulse width low
1300
ns
tQL1QL2
(2)
tXH1XH2
tXL1XL2
tF
tR
tF
Parameter
Min.(1)
Symbol
SDA (out) fall time
(3)
120
ns
Input signal rise time
(4)
(4)
ns
Input signal fall time
(4)
(4)
ns
tDXCX
tSU:DAT Data in set up time
tCLDX
tHD:DAT Data in hold time
20
100
ns
0
ns
ns
tCLQX
tDH
Data out hold time
100
tCLQV(5)(6)
tAA
Clock low to next data valid (access time)
200
900
ns
tCHDL
tSU:STA Start condition setup time
600
ns
tDLCL
tHD:STA Start condition hold time
600
ns
tCHDH
tSU:STO Stop condition set up time
600
ns
1300
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
tW
tWR
Write time
5
ms
1. All values are referred to VIL(max) and VIH(min).
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.
Doc ID 5067 Rev 16
23/39
DC and AC parameters
Table 16.
M24C16, M24C08, M24C04, M24C02, M24C01
AC characteristics at 100 kHz (I2C Standard-mode)(1) (M24Cxx-W,
M24Cxx-R, M24Cxx-F)
Test conditions specified in either Table 6, Table 7 or Table 8 and Table 13
Symbol
Alt.
fC
fSCL
tCHCL
Min.
Max.
Unit
Clock frequency
-
100
kHz
tHIGH
Clock pulse width high
4
-
µs
tCLCH
tLOW
Clock pulse width low
4.7
-
µs
tXH1XH2
tR
Input signal rise time
-
1
µs
tXL1XL2
tF
Input signal fall time
-
300
ns
tF
SDA fall time
-
300
ns
tQL1QL2
(2)
Parameter
tDXCX
tSU:DAT Data in setup time
250
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
tCLQX
tCLQV
(3)
tDH
Data out hold time
200
-
ns
tAA
Clock low to next data valid (access time)
200
3450
ns
tCHDX(4)
tSU:STA Start condition setup time
4.7
-
µs
tDLCL
tHD:STA Start condition hold time
4
-
µs
tCHDH
tSU:STO Stop condition setup time
4
-
µs
4.7
-
µs
-
5
ms
tDHDL
tBUF
Time between Stop condition and next Start
condition
tW
tWR
Write time
1. Values recommended by the I2C bus Standard-mode specification for a robust design of the I2C bus
application. Note that the M24xxx devices decode correctly faster timings as specified in Table 15: AC
characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W, M24Cxx-R, M24Cxx-F).
2. Characterized only.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. For a reStart condition, or following a Write cycle.
24/39
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
DC and AC parameters
Figure 12. AC waveforms
T8,8,
T8(8(
T#(#,
T#,#(
3#,
T$,#,
T8,8,
3$!)N
T#($,
T#,$8
T8(8(
3TART
CONDITION
3$!
)NPUT
3$! T$8#(
#HANGE
T#($( T$($,
3TART
3TOP
CONDITION CONDITION
3#,
3$!)N
T7
T#($(
T#($,
3TOP
CONDITION
7RITECYCLE
3TART
CONDITION
T#(#,
3#,
T#,16
3$!/UT
T#,18
$ATAVALID
T1,1,
$ATAVALID
!)F
Doc ID 5067 Rev 16
25/39
Package mechanical data
7
M24C16, M24C08, M24C04, M24C02, M24C01
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. WLCSP (0.5 mm) and Thin WLCSP (0.3 mm) 0.4 mm pitch 5 bumps,
package outline
D
Orientation reference
e1
e2
A
B
E
e
C
F
b
G
1
A
2
3
A2
A1
SEATING PLANE
1Ca_ME
1. Drawing is not to scale.
Table 17.
M24C08: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.545
0.495
0.595
0.0215
0.0195
0.0234
A1
0.19
0.165
0.215
0.0075
0.0065
0.0085
A2
0.355
0.33
0.38
0.014
0.013
0.015
b
0.27
0.24
0.3
0.0106
0.0094
0.0118
D
1.215
1.195
1.235
0.0478
0.047
0.0486
E
1.025
1.005
1.045
0.0404
0.0396
0.0411
e
0.4
0.0157
e1
0.693
0.0273
e2
0.346
0.0136
F
0.313
0.0123
G
0.261
0.0103
N(2)
5
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.
26/39
Doc ID 5067 Rev 16
5
M24C16, M24C08, M24C04, M24C02, M24C01
Table 18.
Package mechanical data
M24C08: Thin WLCSP (0.3 mm height), 0.4 mm pitch, 5 bumps, package
data(1)
inches(2)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.3
0.270
0.330
0.0118
0.0096
0.014
A1
0.1
0.0039
A2
0.2
0.0079
b
0.16
0.0063
D
1.215
1.34
0.0478
0.0528
E
1.025
1.15
0.0404
0.0453
e
0.4
0.0157
e1
0.693
0.0273
e2
0.346
0.0136
F
0.313
0.0123
G
0.261
0.0103
N(3)
5
5
1. Preliminary data.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. N is the total number of terminals.
Table 19.
M24C16: WLCSP (0.5 mm height) 0.4 mm pitch, 5 bumps, package data(1)
inches(2)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.545
0.495
0.595
0.0215
0.0195
0.0234
A1
0.19
0.165
0.215
0.0075
0.0065
0.0085
A2
0.355
0.33
0.38
0.014
0.013
0.015
b
0.27
0.24
0.3
0.0106
0.0094
0.0118
D
1.255
1.235
1.275
0.0494
0.0486
0.0502
E
1.210
1.190
1.230
0.0476
0.0469
0.0484
e
0.4
0.0157
e1
0.693
0.0273
e2
0.346
0.0136
F
0.405
0.0159
G
0.281
0.0111
N(3)
5
5
1. Preliminary data.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. N is the total number of terminals.
Doc ID 5067 Rev 16
27/39
Package mechanical data
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1 and the ‘N’ indicates the total
number of pins.
Table 20.
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
1.75
Max
0.0689
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.1
0.0039
D
4.9
4.8
5
0.1929
0.189
0.1969
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
-
-
0.05
-
-
h
0.25
0.5
0.0098
0.0197
k
0°
8°
0°
8°
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
28/39
Min
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Package mechanical data
Figure 15. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline
REV MB
e
D
REV MC
e
b
L1
L3
b
L1
L3
Pin 1
E
E2
E2
K
K
L
L
A
D2
D2
ddd
A1
ZW_MEc
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering
process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 21.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.55
0.45
0.6
0.0217
0.0177
0.0236
A1
0.02
0
0.05
0.0008
0
0.002
b
0.25
0.2
0.3
0.0098
0.0079
0.0118
D
2
1.9
2.1
0.0787
0.0748
0.0827
D2 (rev MB)
1.6
1.5
1.7
0.063
0.0591
0.0669
1.45
1.7
0.0571
0.0669
D2 (rev MC)
E
3
2.9
3.1
0.1181
0.1142
0.122
E2 (rev MB)
0.2
0.1
0.3
0.0079
0.0039
0.0118
1.25
1.6
0.0492
0.063
E2 (rev MC)
e
0.5
-
-
0.0197
-
-
K
-
0.3
-
-
0.0118
-
L
-
0.3
0.5
-
0.0118
0.0197
L1
-
-
0.15
-
0.3
-
-
0.0118
-
-
-
0.002
-
-
L3
ddd(2)
0.05
0.0059
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
Doc ID 5067 Rev 16
29/39
Package mechanical data
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 22.
TSSOP8 – 8 lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
A
Max.
0.050
0.150
0.800
1.050
b
0.190
c
0.090
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
α
0.0394
0°
8°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
30/39
Min.
1.200
A1
A2
Typ.
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Package mechanical data
Figure 17. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
1. Drawing is not to scale.
Table 23.
PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
A
Max.
Typ.
Min.
5.33
A1
Max.
0.2098
0.38
0.015
A2
3.3
2.92
4.95
0.1299
0.115
0.1949
b
0.46
0.36
0.56
0.0181
0.0142
0.022
b2
1.52
1.14
1.78
0.0598
0.0449
0.0701
c
0.25
0.2
0.36
0.0098
0.0079
0.0142
D
9.27
9.02
10.16
0.365
0.3551
0.4
E
7.87
7.62
8.26
0.3098
0.3
0.3252
E1
6.35
6.1
7.11
0.25
0.2402
0.2799
e
2.54
-
-
0.1
-
-
eA
7.62
-
-
0.3
-
-
eB
L
10.92
3.3
2.92
3.81
0.4299
0.1299
0.115
0.15
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 5067 Rev 16
31/39
Part numbering
8
M24C16, M24C08, M24C04, M24C02, M24C01
Part numbering
Table 24.
Ordering information scheme
Example:
M24C16
–
W DW 3
T
P /S
Device type
M24 = I2C serial access EEPROM
Device Function
16 = 16 Kbit (2048 x 8)
08 = 8 Kbit (1024 x 8)
04 = 4 Kbit (512 x 8)
02 = 2 Kbit (256 x 8)
01 = 1 Kbit (128 x 8)
Operating voltage
W = VCC = 2.5 V to 5.5 V (400 kHz)
R = VCC = 1.8 V to 5.5 V (400 kHz)
F = VCC = 1.7 V to 5.5 V (400 kHz)
Package
BN = PDIP8
MN = SO8 (150 mil width)
MB or MC= UFDFPN8 (MLP8)
DW = TSSOP8 (169 mil width)
CS = WLCSP(1) (Chip scale package)
CT = Thin WLCSP(2) (Chip scale package)
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
3 = Automotive: device tested with high reliability certified flow(3) over –40 to 125 °C
5 = Consumer: device tested with standard test flow over –20 to 85 °C.
Option
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(4)
/S = F6SP36%
1. Only M24C08 and M24C16 devices are offered in the WLCSP package.
2. Only M24C08-F devices are offered in the Thin WLCSP package.
3. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
4. Used only for device grade 3.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
32/39
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Table 25.
Part numbering
Available M24C16 products (package, voltage range, temperature grade)
M24C16-W
VCC = 2.5 V to 5.5 V
M24C16-R
VCC = 1.8 V to 5.5 V
M24C16-F
VCC = 1.7 V to 5.5 V
Range 6
Range 6
-
Range 6, Range 3
Range 6
-
UFDFPN8 (MB)
-
Range 6
Range 5
UFDFPN8 (MC)
-
Range 6
-
TSSOP8 (DW)
Range 6, Range 3
Range 6
-
-
-
Range 5
Package
DIP8 (BN)
SO8N (MN)
WLCSP (CS)
Table 26.
Available M24C08 products (package, voltage range, temperature grade)
M24C08-W
VCC = 2.5 V to 5.5 V
M24C08-R
VCC = 1.8 V to 5.5 V
M24C08-F
VCC = 1.7 V to 5.5 V
Range 6
-
-
Range 6, Range 3
Range 6
-
UFDFPN8 (MB)
-
Range 6
Range 5
UFDFPN8 (MC)
-
Range 6
Range 5
TSSOP8 (DW)
Range 6
Range 6
-
WLCSP (CS)
-
-
Range 5
Thin WLCSP (CT)
-
-
Range 5
Package
DIP8 (BN)
SO8N (MN)
Table 27.
Available M24C04 products (package, voltage range, temperature grade)
M24C04-W
VCC = 2.5 V to 5.5 V
M24C04-R
VCC = 1.8 V to 5.5 V
M24C04-F
VCC = 1.7 V to 5.5 V
Range 6
-
-
Range 6, Range 3
Range 6
-
UFDFPN8 (MB)
-
Range 6
Range 5
UFDFPN8 (MC)
-
Range 6
Range 5
TSSOP8 (DW)
Range 6, Range 3
Range 6
-
Package
DIP8 (BN)
SO8N (MN)
Doc ID 5067 Rev 16
33/39
Part numbering
M24C16, M24C08, M24C04, M24C02, M24C01
Table 28.
Available M24C02 products (package, voltage range, temperature grade)
Package
DIP8 (BN)
SO8N (MN)
UFDFPN8 (MB or MC)
TSSOP8 (DW)
Table 29.
M24C02-R
VCC = 1.8 V to 5.5 V
Range 6
-
Range 6, Range 3
Range 6
-
Range 6
Range 6, Range 3
Range 6
Available M24C01 products (package, voltage range, temperature grade)
M24C01-W
VCC = 2.5 V to 5.5 V
M24C01-R
VCC = 1.8 V to 5.5 V
DIP8 (BN)
Range 6
-
SO8N (MN)
Range 6
Range 6
-
-
Range 6
Range 6
Package
UFDFPN8 (MB or MC)
TSSOP8 (DW)
34/39
M24C02-W
VCC = 2.5 V to 5.5 V
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
9
Revision history
Revision history
Table 30.
Document revision history
Date
Version
10-Dec-1999
2.4
TSSOP8 Turned-Die package removed (p 2 and order information)
Lead temperature added for TSSOP8 in table 2
18-Apr-2000
2.5
Labelling change to Fig-2D, correction of values for ‘E’ and main caption for
Tab-13
05-May-2000
2.6
Extra labelling to Fig-2D
23-Nov-2000
3.0
SBGA package information removed to an annex document
-R range changed to being the -S range, and the new -R range added
19-Feb-2001
3.1
SBGA package information put back in this document
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data
updated
Wording brought in to line with standard glossary
20-Apr-2001
3.2
Revision of DC and AC characteristics for the -S series
08-Oct-2001
3.3
Ball numbers added to the SBGA connections and package mechanical
illustrations
09-Nov-2001
3.4
Specification of Test Condition for Leakage Currents in the DC
Characteristics table improved
30-Jul-2002
3.5
Document reformatted using new template. SBGA5 package removed
TSSOP8 (3x3mm² body size) package (MSOP8) added. -L voltage range
added
04-Feb-2003
3.6
Document title spelt out more fully. “W”-marked devices with tw=5ms
added.
3.7
-R voltage range upgraded to 400kHz working, and no longer preliminary
data.
5V voltage range at temperature range 3 (-xx3) no longer preliminary data.
-S voltage range removed. -Wxx3 voltage+temp ranged added as
preliminary data.
4.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Read
Operations. VIL(min) improved to
-0.45V. tW(max) value for -R voltage range corrected.
5.0
MLP package added. Absolute Maximum Ratings for VIO(min) and
VCC(min) changed. Soldering temperature information clarified for RoHS
compliant devices. Device grade information clarified. Process
identification letter “G” information added. 2.2-5.5V range is removed, and
4.5-5.5V range is now Not for New Design
05-May-2003
07-Oct-2003
17-Mar-2004
Changes
Doc ID 5067 Rev 16
35/39
Revision history
Table 30.
Date
7-Oct-2005
17-Jan-2006
19-Sep-2006
03-Aug-2007
27-Sep-2007
36/39
M24C16, M24C08, M24C04, M24C02, M24C01
Document revision history (continued)
Version
Changes
6.0
Product List summary table added. AEC-Q100-002 compliance. Device
Grade information clarified. Updated Device internal reset section,
Figure 4, Figure 5, Table 16 and Table 24 Added ECOPACK® information.
Updated tW=5ms for the M24Cxx-W.
7.0
Pin numbers removed from silhouettes (see on page 1). Internal Device
Reset paragraph moved to below Section 2.4: Supply voltage (VCC).
Section 2.4: Supply voltage (VCC) added below Section 2: Signal
description. Test conditions for VOL updated in Table 9 and Table 10 SO8N
package specifications updated (see Table 20)
New definition of ICC1 over the whole VCC range (see Tables 9, 10 and 11).
8
Document converted to new ST template.
SO8 and UFDFPN8 package specifications updated (see Section 7:
Package mechanical data). Section 2.4: Supply voltage (VCC) clarified.
ILI value given with the device in Standby mode in Tables 9, 10 and 11.
Information given in Table 16: AC characteristics (M24Cxx-R and M24CxxF) are no longer preliminary data.
9
1.7 V to 5.5 V VCC voltage range added (M24C16-F, M24C08-F, M24C04-F
part numbers added; Table 8 and Table 12 added).
Section 2.4: Supply voltage (VCC) modified.
Note 1 updated to latest standard revision in Table 5: Absolute maximum
ratings.
Rise/fall time conditions for ICC modified in Table 9, Table 10 and Table 11.
ICC1 conditions modified in Table 11: DC characteristics (M24Cxx-R).
Note removed below Table 14: Input parameters.
tW modified for M24Cxx-R in Table 16, note added.
TSSOP8 (DS) package specifications updated (see Table 23 and
Figure 17).
Added: Table 25, Table 26, Table 27, Table 28 and Table 29 summarizing
all available products.
Table 24: Ordering information scheme: Blank option removed under
Plating technology, /W removed under Process.
10
Section 2.3: Chip Enable (E0, E1, E2) updated.
Concerned signals specified for VIL and VIH parameters, and note removed
in DC characteristics tables (Table 9, Table 10, Table 11 and Table 12).
tW modified in Table 16: AC characteristics (M24Cxx-R and M24Cxx-F).
M24C08-F and M24C04-F offered in UFDFPN8 package in the
temperature range 5 (see Table 26 and Table 27).
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Table 30.
Date
Revision history
Document revision history (continued)
Version
Changes
30-Jan-2009
11
Section 2.4: Supply voltage (VCC) clarified.
Figure 5: Maximum RP value versus bus parasitic capacitance (C) for an
I²C bus updated.
IOL added to Table 5: Absolute maximum ratings. ICC1 test conditions
clarified in DC characteristics Table 9, Table 10, Table 11 and Table 12.
Note modified below Table 14: Input parameters.
tXH1XH2 and tXL1XL2 added to Table 15: AC characteristics at 400 kHz (I2C
Fast-mode) (M24Cxx-W, M24Cxx-R, M24Cxx-F), note 4 removed.
Figure 12: AC waveforms updated.
WLCSP package added (refer to Figure 3 and Section 7: Package
mechanical data).
In Section 7: Package mechanical data:
– ECOPACK text added
– inch values calculated from millimeters and rounded to four decimal
digits
– UFDFPN package specifications updated
Small text changes.
11-Mar-2009
12
Timings for 100 kHz I2C Standard-mode added (see Table 16: AC
characteristics at 100 kHz (I2C Standard-mode) (M24Cxx-W, M24Cxx-R,
M24Cxx-F).
13
Added Thin WLCSP package.
Added Table 19: M24C16: WLCSP (0.5 mm height) 0.4 mm pitch, 5
bumps, package data.
Updated available devices in Table 25, Table 26, Table 27, Table 28, and
Table 29.
14
Package ECOPACK1 or ECOPACK2 category specified.
Section 3.1: Start condition and Section 3.6: Write operations updated.
ILO test conditions modified in Table 9: DC characteristics (M24Cxx-W,
device grade 6), Table 10: DC characteristics (M24Cxx-W, device grade 3)
and Table 11: DC characteristics (M24Cxx-R).
Table 15: AC characteristics at 400 kHz (I2C Fast-mode) (M24Cxx-W,
M24Cxx-R, M24Cxx-F) modified.
tDL1DL2 renamed as tQL1QL2 in Table 16: AC characteristics at 100 kHz (I2C
Standard-mode) (M24Cxx-W, M24Cxx-R, M24Cxx-F).
Figure 12: AC waveforms updated.
28-May-2009
02-Mar-2010
Doc ID 5067 Rev 16
37/39
Revision history
Table 30.
Date
01-Apr-2010
29-Apr-2010
38/39
M24C16, M24C08, M24C04, M24C02, M24C01
Document revision history (continued)
Version
Changes
15
Updated Figure 15: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat
package no lead 2 x 3 mm, outline and Table 21 on page 29.
Updated Table 13: AC measurement conditions.
Updated Table 25 to Table 27.
16
Deleted TSSOP8 3x3 mm package from cover page.
Deleted Figure and Table relating to TSSOP8 3x3 mm package
information.
Deleted line and note in Table 24: Ordering information scheme concerning
TSSOP8 3x3 mm package.
In Table 26: Available M24C08 products (package, voltage range,
temperature grade) updated UFDFPN8 (MC) package for M24C08-F range
to 5 and deleted line concerning TSSOP8 3x3 mm package.
In Table 27: Available M24C04 products (package, voltage range,
temperature grade) updated UFDFPN8 (MC) package for M24C08-F range
to 5.
In Table 28: Available M24C02 products (package, voltage range,
temperature grade) updated UFDRPN8 options to MB or MC.
Doc ID 5067 Rev 16
M24C16, M24C08, M24C04, M24C02, M24C01
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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