M28C64C M28C64X 64 Kbit (8Kb x8) Parallel EEPROM FAST ACCESS TIME: 150ns SINGLE 5V ± 10% SUPPLY VOLTAGE LOW POWER CONSUMPTION FAST WRITE CYCLE – 32 Bytes Page Write Operation – Byte or Page Write Cycle: 5ms ENHANCED END OF WRITE DETECTION – Ready/Busy Open Drain Output (for M28C64C product only) – Data Polling – Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY – Endurance >100,000 Erase/Write Cycles – Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT DESCRIPTION The M28C64C is an 8 Kbit x8 low power Parallel EEPROM fabricated with STMicroelectronics proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V power supply. The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshakingmode with Ready/Busy, Data Polling and Toggle Bit. The M28C64C supports 32 byte page write operation. Table 1. Signal Names A0 - A12 Address Input DQ0 - DQ7 Data Input / Output W Write Enable E Chip Enable G Output Enable RB Ready / Busy VCC Supply Voltage VSS Ground February 1999 28 1 PDIP28 (P) PLCC32 (K) 28 1 SO28 (MS) 300 mils TSOP28 (N) 8 x13.4mm Figure 1. Logic Diagram VCC 13 8 A0-A12 W DQ0-DQ7 M28C64C E RB G VSS AI00746B 1/15 M28C64C, M28C64X VCC W DU A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 RB DU VCC W DU 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M28C64C 8 21 9 20 10 19 11 18 12 17 13 16 14 15 A7 A12 RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 2B. LCC Pin Connections 1 32 A6 A5 A4 A3 A2 A1 A0 NC DQ0 9 M28C64C 25 A8 A9 A11 NC G A10 E DQ7 DQ6 17 DQ1 DQ2 VSS DU DQ3 DQ4 DQ5 Figure 2A. DIP Pin Connections AI00747C AI00748D Warning: DU = Don’t Use. Warning: NC = Not Connected, DU = Don’t Use. Figure 2C. SO Pin Connections Figure 2D. TSOP Pin Connections RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M28C64C 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W DU A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 G A11 A9 A8 DU W VCC RB A12 A7 A6 A5 A4 A3 22 28 1 21 M28C64C 7 AI00876C 15 14 8 A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 AI01016D Warning: DU = Don’t Use. Warning: DU = Don’t Use. PIN DESCRITPION Addresses (A0-A12). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations. 2/15 M28C64C, M28C64X Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit Ambient Operating Temperature – 40 to 125 °C T STG Storage Temperature Range – 65 to 150 °C VCC Supply Voltage – 0.3 to 6.5 V V IO Input/Output Voltage – 0.3 to VCC +0.6 V VI Input Voltage – 0.3 to 6.5 V 2000 V TA VESD Electrostatic Discharge Voltage (Human Body model) Note: Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Operating Modes Mode E G W DQ0 - DQ7 Read VIL VIL VIH Data Out Write VIL VIH VIL Data In Standby / Write Inhibit VIH X X Hi-Z Write Inhibit X X VIH Data Out or Hi-Z Write Inhibit X VIL X Data Out or Hi-Z Output Disable X VIH X Hi-Z Note: X = VIH or VIL Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28C64C through the I/O pins. Write Enable (W). The Write Enable input controls the writing of data to the M28C64C. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. OPERATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 6. Read The M28C64C is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedancewhen either G or E is high. Write Write operations are initiated when both W and E are low and G is high.The M28C64C supports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion. Page Write Page write allows up to 32 bytes to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A5 - A12 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data up to a maximum of 100µs after the rising edge of E or W which ever occurs first (t BLC). If a transition of E or W is not detected within 100µs, the internal programming cycle will start. 3/15 M28C64C, M28C64X Figure 3. Block Diagram RB VPP GEN A0-A4 ADDRESS LATCH X DECODE A5-A12 (Page Address) RESET E G W ATD & CONTROL LOGIC 64K ARRAY ADDRESS LATCH Y DECODE SENSE AND DATA LATCH I/O BUFFERS PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING DQ0-DQ7 AI00877C Microcontroller Control Interface The M28C64C provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only, or as the RB signal on a separate pin. Figure 4. Status Bit Assignment DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle. 4/15 Toggle bit (DQ6). The M28C64C offers another way for determining when the internal write cycle is completed. Duringthe internal Erase/Write cycle, DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the first read value is ”0”) on subsequent attempts to read any address in the memory. When the internal cycle is completed the toggling will stop and the device will be accessible for a new Read or Write operation. Page Load Timer Status bit (DQ5). In the Page Write mode data may be latched by E or W up to 100µs after the previous byte. Up to 32 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is running, High indicates time-out after which the write cycle will start and no new data may be input. Ready/Busy pin. The RB pin provides a signal at its open drain output which is low during the erase/write cycle, but which is released at the completion of the programming cycle. M28C64C, M28C64X Table 4. AC Measurement Conditions Figure 6. AC Testing Equivalent Load Circuit Input Rise and Fall Times ≤ 20ns Input Pulse Voltages 0.4V to 2.4V Input and Output Timing Ref. Voltages 0.8V to 2.0V 1.3V 1N914 Note that Output Hi-Z is defined as the point where data is no longer driven. 3.3kΩ Figure 5. AC Testing Input Output Waveforms 2.4V DEVICE UNDER TEST OUT CL = 30pF 2.0V 0.8V 0.4V CL includes JIG capacitance AI00826 AI01129 Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol Parameter Test Condition Input Capacitance CIN Output Capacitance C OUT Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. Table 6. Read Mode DC Characteristics (TA = 0 to 70°C or –40 to 85°C, VCC = 4.5V to 5.5V) Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC 10 µA ILO Output Leakage Current 0V ≤ VIN ≤ VCC 10 µA E = VIL, G = VIL , f = 5 MHz 30 mA E = VIH 2 mA E > VCC –0.3V 100 µA ICC (1) Supply Current (TTL and CMOS inputs) ICC1 (1) Supply Current (Standby) TTL ICC2 (1) Supply Current (Standby) CMOS VIL Input Low Voltage – 0.3 0.8 V VIH Input High Voltage 2 VCC +0.5 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = –400 µA 2.4 V Note: 1. All I/O’s open circuit. Table 7. Power Up Timing (1) (TA = 0 to 70°C or –40 to 85°C, VCC = 4.5V to 5.5V) Symbol Parameter Min Max Unit tPUR Time Delay to Read Operation 1 µs tPUW Time Delay to Write Operation 10 ms Note: 1. Sampled only, not 100% tested. 5/15 M28C64C, M28C64X Table 8. Read Mode AC Characteristics (TA = 0 to 70°C or –40 to 85°C, VCC = 4.5V to 5.5V) M28C64C Symbol Alt Parameter Test Condition -150 min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV -200 max min Unit -250 max min max E = VIL, G = VIL 150 200 250 ns Chip Enable Low to Output Valid G = VIL 150 200 250 ns tOE Output Enable Low to Output Valid E = VIL 75 100 110 ns tEHQZ (1) tDF Chip Enable High to Output Hi-Z G = VIL 0 50 0 60 0 65 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 0 50 0 60 0 65 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 0 ns Note: 1. Output Hi-Z is defined as the point at which data is no longer driven. Figure 7. Read Mode AC Waveforms A0-A12 VALID tAVQV tAXQX E tGLQV tEHQZ G tELQV DQ0-DQ7 tGHQZ DATA OUT Hi-Z AI00749B Note: Write Enable (W) = High 6/15 M28C64C, M28C64X Table 9. Write Mode AC Characteristics (TA = 0 to 70°C or –40 to 85°C, VCC = 4.5V to 5.5V) Symbol Alt tAVWL tAS tAVEL Parameter Test Condition Min Max Unit Address Valid to Write Enable Low E = VIL, G = VIH 0 ns tAS Address Valid to Chip Enable Low G = VIH, W = VIL 0 ns tELWL tCES Chip Enable Low to Write Enable Low G = VIH 0 ns tGHWL tOES Output Enable High to Write Enable Low E = VIL 0 ns tGHEL tOES Output Enable High to Chip Enable Low W = VIL 0 ns tWLEL tWES Write Enable Low to Chip Enable Low G = VIH 0 ns tWLAX tAH Write Enable Low to Address Transition 150 ns tELAX tAH Chip Enable Low to Address Transition 150 ns tWLDV tDV Write Enable Low to Input Valid E = VIL, G = VIH 1 µs tELDV tDV Chip Enable Low to Input Valid G = VIH, W = VIL 1 µs tWLWH tWP Write Enable Low to Write Enable High 150 ns tELEH tWP Chip Enable Low to Chip Enable High 150 ns tWHEH tCEH Write Enable High to Chip Enable High 0 ns tWHGL tOEH Write Enable High to Output Enable Low 10 ns tEHGL tOEH Chip Enable High to Output Enable Low 10 ns tEHWH tWEH Chip Enable High to Write Enable High 0 ns tWHDX tDH Write Enable High to Input Transition 0 ns tEHDX tDH Chip Enable High to Input Transition 0 ns tWHWL tWPH Write Enable High to Write Enable Low 200 ns tWHWH tBLC Byte Load Repeat Cycle Time 0.35 tWHRH tWC Write Cycle Time tWHRL tDB Write Enable High to Ready/Busy Low tEHRL tDB Chip Enable High to Ready/Busy Low tDVWH tDS Data Valid before Write Enable High 50 ns tDVEH tDS Data Valid before Chip Enable High 50 ns 50 µs 5 ms Note 1 220 ns Note 1 220 ns Note: 1. With a 3.3 kΩ external pull-up resistor. 7/15 M28C64C, M28C64X Figure 8. Write Mode AC Waveforms - Write Enable Controlled A0-A12 VALID tAVWL tWLAX E tELWL tWHEH G tGHWL tWLWH tWHGL W tWLDV tWHWL DATA IN DQ0-DQ7 tDVWH tWHDX RB tWHRL AI00750 Figure 9. Write Mode AC Waveforms - Chip Enable Controlled A0-A12 VALID tAVEL tELAX E tGHEL tELEH G tWLEL tEHGL W tELDV DQ0-DQ7 tEHWH DATA IN tDVEH tEHDX RB tEHRL AI00751 8/15 M28C64C, M28C64X Figure 10. Page Write Mode AC Waveforms - Write Enable Controlled A0-A12 Addr 0 Addr 1 Addr 2 Addr n E tPLTS G tWHWL tWHRH W tWLWH tWHWH Byte 0 DQ0-DQ7 Byte 1 Byte 2 tWHWH Byte n DQ5 Byte n tWHRL RB AI00752C Figure 11. Data Polling Waveform Sequence A0-A12 Address of the last byte of the Page Write instruction E G W DQ7 DQ7 LAST WRITE DQ7 DQ7 DQ7 INTERNAL WRITE SEQUENCE DQ7 READY AI00753C 9/15 M28C64C, M28C64X Figure 12. Toggle Bit Waveform Sequence A0-A12 E G W DQ6 (1) LAST WRITE TOGGLE INTERNAL WRITE SEQUENCE READY AI00754D Note: 1. First Toggle bit is forced to ’0’ ORDERING INFORMATION SCHEME Example: M28C64C -150 K Package Speed Version 1 Temperature Range C RB available -150 150 ns P PDIP28 1 0 to 70 °C X RB not bonded (pin NC) -200 200 ns K PLCC32 6 –40 to 85 °C -250 250 ns MS SO28 300 mils N TSOP28 8 x 13.4mm For a listof availableoptions (Speed, Package,etc... ) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 10/15 M28C64C, M28C64X PDIP28 - 28 pin Plastic DIP, 600 mils width mm Symb Typ inches Min Max A Typ Min 5.08 Max 0.200 A1 0.38 A2 3.56 4.06 0.140 0.160 B 0.38 0.51 0.015 0.020 B1 0.015 1.52 0.060 C 0.20 0.30 0.008 0.012 D 36.83 37.34 1.450 1.470 0.535 0.545 D2 33.02 1.300 E 15.24 0.600 E1 13.59 13.84 e1 2.54 0.100 eA 14.99 0.590 eB 15.24 17.78 0.600 0.700 L 3.18 3.43 0.125 0.135 S 1.78 2.08 0.070 0.082 α 0° 10° 0° 10° N 28 28 A2 A1 B1 B A L e1 α eA D2 C eB D S N E1 E 1 PDIP Drawing is not to scale. 11/15 M28C64C, M28C64X PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular mm Symb Typ inches Min Max A 2.54 A1 Typ Min Max 3.56 0.100 0.140 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 0.050 0.035 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R PLCC Drawing is not to scale. 12/15 CP M28C64C, M28C64X SO28 - 28 lead Plastic Small Outline, 300 mils body width mm Symb Typ inches Min Max A 2.46 A1 Min Max 2.64 0.097 0.104 0.13 0.29 0.005 0.011 A2 2.29 2.39 0.090 0.094 B 0.35 0.48 0.014 0.019 C 0.23 0.32 0.009 0.013 D 17.81 18.06 0.701 0.711 E 7.42 7.59 0.292 0.299 – – – – H 10.16 10.41 0.400 0.410 L 0.61 1.02 0.024 0.040 α 0° 8° 0° 8° N 28 e 1.27 CP Typ 0.050 28 0.10 A2 0.004 A C B CP e D N E H 1 A1 α L SO-b Drawing is not to scale. 13/15 M28C64C, M28C64X TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm mm Symb Typ inches Min Max Typ Min A 1.25 0.049 A1 0.20 0.008 A2 0.95 1.15 0.037 0.045 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 13.20 13.60 0.520 0.535 D1 11.70 11.90 0.461 0.469 E 7.90 8.10 0.311 0.319 – – – – L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 28 e 0.55 0.022 28 CP 0.10 0.004 A2 22 21 e 28 1 E B 7 8 D1 A CP D DIE C TSOP-c Drawing is not to scale. 14/15 Max A1 α L M28C64C, M28C64X Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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