STMICROELECTRONICS M36W432T85ZA6T

M36W432T
M36W432B
32 Mbit (2Mb x16, Boot Block) Flash Memory
and 4 Mbit (256K x16) SRAM, Multiple Memory Product
PRODUCT PREVIEW
FEATURES SUMMARY
■ SUPPLY VOLTAGE
SRAM
4 Mbit (256K x 16 bit)
– VDDF = 2.7V to 3.3V
■
– VDDS = VDDQF = 2.7V to 3.3V
– VPPF = 12V for Fast Program (optional)
■
ACCESS TIME: 70ns
■
LOW VDDS DATA RETENTION: 1.5V
■
ACCESS TIME: 70,85ns
■
■
LOW POWER CONSUMPTION
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
Figure 1. Packages
– Top Device Code, M36W432T: 88BAh
– Bottom Device Code, M36W432B: 88BBh
FLASH MEMORY
32 Mbit (2Mb x16) BOOT BLOCK
■
– 8 x 4 KWord Parameter Blocks (Top or
Bottom Location)
■
PROGRAMMING TIME
– 10µs typical
– Double Word Programming Option
■
FBGA
Stacked LFBGA66 (ZA)
8 x 8 ball array
BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
■
AUTOMATIC STAND-BY MODE
■
PROGRAM and ERASE SUSPEND
■
COMMON FLASH INTERFACE
– 64 bit Security Code
■
SECURITY
– 64 bit user programmable OTP cells
– 64 bit unique device identifier
– One parameter block permanently lockable
February 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/57
M36W432T, M36W432B
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Flash Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Flash Security Block Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SRAM Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Read Block Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 17
Flash Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Flash Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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M36W432T, M36W432B
Figure 10. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12. Flash Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Flash Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13. SRAM Read AC Waveforms, Address Controlled with UBS = LBS = VIL . . . . . . . . . . . 31
Figure 14. SRAM Read AC Waveforms, E1S, E2S or GS Controlled . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. SRAM Write AC Waveforms, WS Controlled with GS High . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. SRAM Write AC Waveforms, UBS and LBS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. SRAM Low VDDS Data Retention AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . 36
Figure 21. SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled . . . . . . . . . . . . . . . . 36
Table 21. SRAM Low VDDS Data Retention Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline. . . . 37
Table 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data . . . . . . . 37
Figure 23. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . 38
Figure 24. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)39
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 23. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26. Top Boot Block Addresses, M36W432T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 27. Bottom Boot Block Addresses, M36W432B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 28. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 30. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 31. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
APPENDIX C. FLASH MEMORY FLOWCHARTS and PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . 49
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M36W432T, M36W432B
Figure 25. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 26. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 27. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 51
Figure 28. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 30. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
APPENDIX D. FLASH MEMORY COMMAND INTERFACE and PROGRAM/ERASE CONTROLLER
STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. Write State Machine Current/Next, sheet 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 35. Write State Machine Current/Next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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M36W432T, M36W432B
SUMMARY DESCRIPTION
The M36W432 is a low voltage Multiple Memory
Product which combines two memory devices; a
32 Mbit boot block Flash memory and a 4 Mbit
SRAM. Recommended operating conditions do
not allow both the Flash and the SRAM to be active at the same time.
The memory is offered in a Stacked LFBGA66 (0.8
mm pitch) package and is supplied with all the bits
erased (set to ‘1’).
Table 1. Signal Names
A0-A17
Address Inputs
A18-A20
Address Inputs for Flash Chip only
DQ0-DQ15
Data Input/Output
VDDF
Flash Power Supply
VDDQF
Flash Power Supply for I/O Buffers
VPPF
Flash Optional Supply Voltage for Fast
Program & Erase
VSSF
Flash Ground
VDDS
SRAM Power Supply
VSSS
SRAM Ground
NC
Not Connected Internally
Figure 2. Logic Diagram
VDDQF
VDDF
VDDS
VPPF
21
16
A0-A20
DQ0-DQ15
Flash control functions
EF
Chip Enable input
GF
GF
Output Enable input
WF
WF
Write Enable input
RPF
RPF
Reset input
WPF
Write Protect input
EF
WPF
M36W432T
M36W432B
E1S
SRAM control functions
E2S
E1S, E2S
Chip Enable inputs
GS
Output Enable input
WS
Write Enable input
UBS
Upper Byte Enable input
LBS
Lower Byte Enable input
GS
WS
UBS
LBS
VSSF
VSSS
AI05200
5/57
M36W432T, M36W432B
Figure 3. LFBGA Connections (Top view through package)
#1
#2
1
2
3
4
5
6
7
8
#3
#4
NC
NC
A20
A11
A15
A14
A13
A12
VSSF
VDDQF
NC
NC
B
A16
A8
A10
A9
DQ15
WS
DQ14
DQ7
C
WF
NC
DQ13
DQ6
DQ4
DQ5
D
VSSS
RPF
DQ12
E2S
VDDS
VDDF
E
WPF
VPPF
A19
DQ10
DQ2
DQ3
F
LBS
UBS
GS
DQ9
DQ8
DQ0
DQ1
G
A18
A17
A7
A6
A3
A2
A1
E1S
NC
A5
A4
A0
EF
VSSF
GF
NC
NC
NC
A
H
NC
NC
DQ11
AI05201
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A17). Addresses
A0-A17
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (EF) and Write
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip Enable (EF) and Write Enable (WF) signals
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
6/57
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at VIL and Reset is at VIH the device
is in active mode. When Chip Enable is at VIH the
memory is deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
Flash Output Enable (GF). The Output Enable
controls the data outputs during the Bus Read operation of the Flash memory.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip
Enable, EF, or Write Enable, WF, whichever occurs first.
M36W432T, M36W432B
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at VIL, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at VIH, the Lock-Down is disabled and the block
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RPF). The Reset input provides a
hardware reset of the Flash memory. When Reset
is at VIL, the memory is in reset mode: the outputs
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at VIH, the device is
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
of Chip Enable or a change of the address is required to ensure valid data outputs.
SRAM Chip Enable (E1S, E2S). The Chip Enable inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at VIH or
E2S at VIL deselects the memory and reduces the
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at VIL. It
is not allowed to set EF at VIL, E1S at VIL and E2S
at VIH at the same time.
SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is active low.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is active low.
VDDF Supply Voltage (2.7V to 3.3V). VDDF provides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
VDDQF and VDDS Supply Voltage (2.7V to 3.3V).
VDDQF provides the power supply for the Flash
memory I/O pins and VDDS provides the power
supply for the SRAM control pins. This allows all
Outputs to be powered independently from the
Flash core power supply, VDDF. VDDQF can be tied
to VDDS
VPPF Program Supply Voltage. VPPF is both a
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Voltage VDDF and the Program Supply Voltage VPPF
can be applied in any order.
If VPPF is kept in a low voltage range (0V to 3.6V)
VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection
against program or erase, while VPPF > VPPLK enables these functions (see Table 14, DC Characteristics for the relevant values). VPPF is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect and program or erase operations continue.
If VPPF is in the range 11.4V to 12.6V it acts as a
power supply pin. In this condition VPPF must be
stable until the Program/Erase algorithm is completed (see Table 16 and 17).
VSSF and VSSS Ground. VSSF and VSSS are the
ground reference for all voltage measurements in
the Flash and SRAM chips, respectively.
Note: Each device in a system should have VDDF, VDDQF and VPPF decoupled with a 0.1µF capacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the required VPPF program and erase currents.
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M36W432T, M36W432B
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM.
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
simultaneous read operations on the Flash and
the SRAM which would result in a data bus contention. Therefore it is recommended to put the
SRAM in the high impedance state when reading
the Flash and vice versa (see Table 2 Main Operation Modes for details).
Figure 4. Functional Block Diagram
VDDF
VDDF
EF
EF
GF
GF
WF
WF
RPF
RPF
WPF
WPF
VDDQF
VDDQF
VPPF
VPPF
Flash Memory
Flash
Memory
32 Mbit
(x16)
32 Mbit (x16)
A18-A20
A18-A20
A0-A17
A0-A17
VSSF
VSSF
VDDS
VDDS
E1S
E1S
E2S
E2S
GS
GS
WS
WS
UBS
UBS
LBS
LBS
DQ0-DQ15
DQ0-DQ15
SRAM
SRAM
4 Mbit
(x16)
4 Mbit (x16)
VSSS
VSSS
AI05202
AI05202
8/57
M36W432T, M36W432B
SRAM
Flash Memory
Table 2. Main Operation Modes
Operation
Mode
EF
GF
WF
RPF
WPF
VPPF
Read
VIL
VIL
VIH
VIH
X
Don't care
SRAM must be disabled
Data
Output
Write
VIL
VIH
VIL
VIH
VIH
VDDF or
VPPFH
SRAM must be disabled
Data Input
Block
Locking
VIL
X
X
VIH
VIL
Don't care
SRAM must be disabled
X
Standby
VIH
X
X
VIH
X
Don't care
Any SRAM mode is allowed
Hi-Z
Reset
X
X
X
VIL
X
Don't care
Any SRAM mode is allowed
Hi-Z
Output
Disable
VIL
VIH
VIH
VIH
X
Don't care
Any SRAM mode is allowed
Hi-Z
E1S E2S
GS
WS
UBS, LBS (1)
DQ15-DQ0
Read
Flash must be disabled
VIL
VIH
VIL
VIH
VIL
Data out
Word Read
Write
Flash must be disabled
VIL
VIH
VIH
VIL
VIL
Data in
Word Write
VIH
X
X
X
X
Hi-Z
X
VIL
X
X
X
Hi-Z
X
X
X
X
VIH
Hi-Z
VIH
X
X
X
X
Hi-Z
X
VIL
X
X
X
Hi-Z
X
X
X
X
VIH
Hi-Z
VIL
VIH
VIH
VIH
X
Hi-Z
Standby/
Power
Down
Data
Retention
Output
Disable
Any Flash mode is allowable
Any Flash mode is allowable
Any Flash mode is allowable
Note: X = VIL or VIH, VPPFH = 12V ± 5%.
1. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
9/57
M36W432T, M36W432B
Flash Memory Component
The Flash Memory is a 32 Mbit (2 Mbit x 16) device that can be erased electrically at the block
level and programmed in-system on a Word-byWord basis. These operations can be performed
using a single low voltage (2.7 to 3.3V) supply
and the VDDQF for device I/0 operation feature the
same voltage range. An optional 12V VPPF power
supply is provided to speed up customer programming.
The device features an asymmetrical blocked architecture with an array of 71 blocks: 8 Parameter
Blocks of 4 KWord and 63 Main Blocks of 32
KWord. The M36W432T device has the Flash
Memory Parameter Blocks at the top of the memory address space while the M36W432B device locates the Parameter Blocks starting from the
bottom. The memory maps are shown in Figure 5,
Block Addresses.
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase.
When VPPF ≤ VPPLK all blocks are protected
10/57
against program or erase. All blocks are locked at
Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system design. The Protection Register is divided into two 64 bit segments, the first one contains
a unique device number written by ST, while the
second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Security Block,
parameter block 0, can be permanently protected
by the user. Figure 6, shows the Flash Security
Block Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
M36W432T, M36W432B
Figure 5. Flash Block Addresses
Bottom Boot Block Addresses
Top Boot Block Addresses
1FFFFF
1FFFFF
32 KWords
4 KWords
1F8000
1F7FFF
1FF000
32 KWords
Total of 8
4 KWord Blocks
1F0000
Total of 63
32 KWord Blocks
1F8FFF
4 KWords
1F8000
1F7FFF
32 KWords
00FFFF
1F0000
32 KWords
008000
007FFF
4 KWords
Total of 63
32 KWord Blocks
007000
Total of 8
4 KWord Blocks
00FFFF
32 KWords
008000
007FFF
000FFF
32 KWords
4 KWords
000000
000000
AI05203
Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses.
Figure 6. Flash Security Block Memory Map
88h
User Programmable OTP
85h
84h
Parameter Block # 0
Unique device number
81h
80h
Protection Register Lock
2
1
0
AI05204
SRAM Component
The SRAM is an 4 Mbit asynchronous random access memory which features a super low voltage
operation and low current consumption with an ac-
cess time of 70 ns in all conditions. The memory
operations can be performed using a single low
voltage supply, 2.7V to 3.3V, which is the same as
the Flash voltage supply.
11/57
M36W432T, M36W432B
OPERATING MODES
Flash Bus Operations
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2, Main Operation Modes, for a
summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read depends on the previous command written to the
memory (see Command Interface section). See
Figure 9, Read Mode AC Waveforms, and Table
15, Flash Read AC Characteristics, for details of
when the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at VIL with Output Enable at
VIH. Commands, Input Data and Addresses are
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
See Figures 10 and 11, Write AC Waveforms, and
Tables 16 and 17, Flash Write AC Characteristics,
for details of the timing requirements.
Output Disable. The data outputs are high impedance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by
when Chip Enable is at VIH and the device is in
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
VIH during a program or erase operation, the device enters Standby mode when finished.
Automatic Standby. Automatic Standby provides a low power consumption state during Read
mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, VIL, and the supply
current is reduced to IDD1. The data Inputs/Out-
12/57
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable
is Low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset
mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSSF during a Program or Erase, this operation is aborted and the
memory content is no longer valid.
Flash Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution
of the Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Program/Erase states. See Appendix 29, Table 34,
Write State Machine Current/Next, for a summary
of the Command Interface.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Reset or whenever VDDF is lower than VLKO. Command sequences must be followed exactly. Any
invalid combination of commands will reset the device to Read mode. Refer to Table 3, Commands,
in conjunction with the text descriptions below.
Read Memory Array Command. The
Read
command returns the memory to its Read mode.
One Bus Write cycle is required to issue the Read
Memory Array command and return the memory to
Read mode. Subsequent read operations will read
the addressed location and output the data. When
a device Reset occurs, the memory defaults to
Read mode.
Read Status Register Command. The Status
Register indicates when a program or erase operation is complete and the success or failure of the
operation itself. Issue a Read Status Register
command to read the Status Register’s contents.
Subsequent Bus Read operations read the Status
Register at any address, until another command is
issued. See Table 10, Status Register Bits, for details on the definitions of the bits.
The Read Status Register command may be issued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the content of the Status Register.
M36W432T, M36W432B
Read Electronic Signature Command. The
Read Electronic Signature command reads the
Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protection and Lock Register. See Tables 4, 5 and 6 for
the valid address.
Read CFI Query Command. The Read Query
Command is used to read data from the Common
Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of
the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations
read from the Common Flash Interface Memory
Area. See Appendix B, Common Flash Interface,
Tables 28, 29, 30, 31, 32 and 33 for details on the
information contained in the Common Flash Interface memory area.
Block Erase Command. The Block Erase command can be used to erase a block. It sets all the
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the Status Register
will output the error.
Two Bus Write cycles are required to issue the
command.
■ The first bus cycle sets up the Erase command.
■ The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
Erase aborts if Reset turns to VIL. As data integrity
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are
given in Table 7, Program, Erase Times and Program/Erase Endurance Cycles.
See Appendix C, Figure 28, Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.
Program Command. The memory array can be
programmed word-by-word. Two bus write cycles
are required to issue the Program Command.
The first bus cycle sets up the Program
command.
■ The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
During Program operations the memory will accept the Read Status Register command and the
Program/Erase Suspend command. Typical Program times are given in Table 7, Program, Erase
Times and Program/Erase Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and reprogrammed.
See Appendix C, Figure 25, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program Command. This feature
is offered to improve the programming throughput,
writing a page of two adjacent words in parallel.The two words must differ only for the address
A0. Programming should not be attempted when
VPPF is not at VPPH. The command can be executed if VPPF is below VPPH but the result is not guaranteed.
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity
cannot be guaranteed when the program operation is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 26, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program
command.
Clear Status Register Command. The
Clear
Status Register command can be used to reset
bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
bus write cycle is required to issue the Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
■
13/57
M36W432T, M36W432B
Program/Erase Suspend Command. The Program/Erase Suspend command is used to pause
a Program or Erase operation. One bus write cycle
is required to issue the Program/Erase command
and pause the Program/Erase controller.
During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then
the Program, Block Lock, Block Lock-Down or
Protection Program commands will also be accepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/
Erase Resume command is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Enable to VIH. Program/Erase is aborted if
Reset turns to VIL.
See Appendix C, Figure 27, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, and Figure 29, Erase Suspend &
Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Suspend command.
Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the command. Once the command is issued subsequent
Bus Read operations read the Status Register.
See Appendix C, Figure 27, Program or Double
Word Program Suspend & Resume Flowchart and
Pseudo Code, and Figure 29, Erase Suspend &
Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command.
Protection Register Program Command. The
Protection Register Program command is used to
Program the 64 bit user One-Time-Programmable
(OTP) segment of the Protection Register. The
segment is programmed 16 bits at a time. When
shipped all bits in the segment are set to ‘1’. The
user can only program the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
■ The first bus cycle sets up the Protection
Register Program command.
14/57
The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register. Bit 1 of the Protection Lock Register protects bit 2 of the Protection Lock Register. Programming bit 2 of the
Protection Lock Register will result in a permanent
protection of the Security Block (see Figure 6,
Flash Security Block Memory Map). Attempting to
program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register and/or the
Security Block is not reversible.
The Protection Register Program cannot be suspended.
Block Lock Command. The Block Lock command is used to lock a block and prevent Program
or Erase operations from changing the data in it.
All blocks are locked at power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latches the block
address.
The Lock Status can be monitored for each block
using the Read Block Signature command. Table.
9 shows the Lock Status after issuing a Block Lock
command.
The Block Lock bits are volatile, once set they remain set until reset or power-down/power-up.
They are cleared by a Blocks Unlock command.
Refer to the section, Block Locking, for a detailed
explanation.
Block Unlock Command. The Blocks Unlock
command is used to unlock a block, allowing the
block to be programmed or erased. Two Bus Write
cycles are required to issue the Blocks Unlock
command.
■ The first bus cycle sets up the Block Unlock
command.
■ The second Bus Write cycle latches the block
address.
The Lock Status can be monitored for each block
using the Read Block Signature command. Table.
9 shows the Lock Status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation.
■
M36W432T, M36W432B
Block Lock-Down Command. A locked block
cannot be Programmed or Erased, or have its
Lock status changed when WP is low, VIL. When
WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock command.
■ The first bus cycle sets up the Block Lock
command.
The second Bus Write cycle latches the block
address.
The Lock Status can be monitored for each block
using the Read Block Signature command.
Locked blocks revert to the protected (and not
locked) state when the device is reset on powerdown. Table. 9 shows the Lock Status after issuing
a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation.
■
Table 3. Commands
Bus Write Operations
Commands
No. of
Cycles
1st Cycle
2nd Cycle
3nd Cycle
Bus
Op.
Addr
Data
Bus
Op.
Addr
Data
Read Memory Array
1+
Write
X
FFh
Read
Read
Addr
Data
Read Status Register
1+
Write
X
70h
Read
X
Status
Register
Read Electronic Signature
1+
Write
X
90h
Read
Signature
Addr (1)
Signature
Read CFI Query
1+
Write
55h
98h
Read
CFI Addr
Query
Erase
2
Write
X
20h
Write
Block
Addr
D0h
Program
2
Write
X
40h or
10h
Write
Addr
Data Input
Double Word Program (2)
3
Write
X
30h
Write
Addr 1
Data Input
Clear Status Register
1
Write
X
50h
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Block Lock
2
Write
X
60h
Write
Block
Address
01h
Block Unlock
2
Write
X
60h
Write
Block
Address
D0h
Block Lock-Down
2
Write
X
60h
Write
Block
Address
2Fh
Protection Register
Program
2
Write
X
C0h
Write
Address Data Input
Bus
Op.
Addr
Data
Write
Addr 2
Data
Input
Note: X = Don't Care.
1. The signature addresses are listed in Tables 4, 5 and 6.
2. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.
15/57
M36W432T, M36W432B
Table 4. Read Electronic Signature
Code
Device
EF
GF
WF
A0
A1
A2-A7
A8-A11
A12-A20
DQ0-DQ7
DQ8-DQ15
VIL
VIL
VIH
VIL
VIL
0
Don't Care
Don't Care
20h
00h
M36W432T
VIL
VIL
VIH
VIH
VIL
0
Don't Care
Don't Care
xxh
88h
M36W432B
VIL
VIL
VIH
VIH
VIL
0
Don't Care
Don't Care
xxh
88h
Manufacture
Code
Device
Code
Note: RPF = VIH.
Table 5. Read Block Signature
EF
GF
WF
A0
A1
A2-A7
Locked Block
VIL
VIL
VIH
VIL
VIH
0
Unlocked Block
VIL
VIL
VIH
VIL
VIH
Locked-Down
Block
VIL
VIL
VIH
VIL
VIH
Block Status
A8-A20
A12-A20
DQ0
DQ1
DQ2-DQ15
Don't Care Block Address
1
0
00h
0
Don't Care Block Address
0
0
00h
0
Don't Care Block Address
X (1)
1
00h
Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0"; see Block Locking section.
Table 6. Read Protection Register and Lock Register
EF
GF
WF A0-A7
A8-A20
DQ0
DQ1
DQ2
Lock
VIL
VIL
VIH
80h
Don't Care
0
OTP Prot.
data
Security
prot. data
00h
00h
Unique ID 0
VIL
VIL
VIH
81h
Don't Care
ID data
ID data
ID data
ID data
ID data
Unique ID 1
VIL
VIL
VIH
82h
Don't Care
ID data
ID data
ID data
ID data
ID data
Unique ID 2
VIL
VIL
VIH
83h
Don't Care
ID data
ID data
ID data
ID data
ID data
Unique ID 3
VIL
VIL
VIH
84h
Don't Care
ID data
ID data
ID data
ID data
ID data
OTP 0
VIL
VIL
VIH
85h
Don't Care
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 1
VIL
VIL
VIH
86h
Don't Care
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 2
VIL
VIL
VIH
87h
Don't Care
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 3
VIL
VIL
VIH
88h
Don't Care
OTP data
OTP data
OTP data
OTP data
OTP data
Word
16/57
DQ3-DQ7 DQ8-DQ15
M36W432T, M36W432B
Table 7. Program, Erase Times and Program/Erase Endurance Cycles
Flash Memory
Parameter
Test Conditions
Unit
Min
Word Program
Double Word Program
Typ
Max
VPPF = VDDF
10
200
µs
VPPF = 12V ±5%
10
200
µs
VPPF = 12V ±5%
0.16
5
s
VPPF = VDDF
0.32
5
s
VPPF = 12V ±5%
0.02
4
s
VPPF = VDDF
0.04
4
s
VPPF = 12V ±5%
1
10
s
VPPF = VDDF
1
10
s
VPPF = 12V ±5%
0.8
10
s
VPPF = VDDF
0.8
10
s
Main Block Program
Parameter Block Program
Main Block Erase
Parameter Block Erase
Program/Erase Cycles (per Block)
Flash Block Locking
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.
■ Lock/Unlock - this first level allows softwareonly control of block locking.
■ Lock-Down - this second level requires
hardware interaction before locking can be
changed.
■ VPPF ≤ VPPLK - the third level offers a complete
hardware protection against program and erase
on all blocks.
The locking status of each block can be set to
Locked, Unlocked, and Lock-Down. The following
sections explain the operation of the locking system. Table 7, defines all of the possible locking
states (WP, DQ1, DQ0), and Appendix C, Figure
30, shows a flowchart for the locking operations.
Locked State. The default status of all blocks on
power-up or reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase operations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
100,000
cycles
Unlocked State. Unlocked blocks (states (0,0,0),
(1,0,0) (1,1,0)), can be programmed or erased. All
unlocked blocks return to the Locked state when
the device is reset or powered-down. The status of
an unlocked block can be changed to Locked or
Locked-Down using the appropriate software
commands. A locked block can be unlocked by issuing the Unlock command.
Lock-Down State. Blocks that are Locked-Down
(state (0,1,1))are protected from program and
erase operations (as for Locked blocks) but their
Lock status cannot be changed using software
commands alone. A Locked or Unlocked block can
be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked
state when the device is reset or powered-down.
The Lock-Down function is dependent on the WPF
input pin. When WPF=0 (VIL), the blocks in the
Lock-Down state (0,1,1) are protected from program, erase and lock status changes. When
WPF=1 (VIH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WPF
remains high. When WPF is low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,1) regardless of any changes made
while WPF was high. Device reset or power-down
resets all blocks, including those in Lock-Down, to
the Locked state.
17/57
M36W432T, M36W432B
Reading a Block’s Lock Status. The lock status
of every block can be read in the Read Electronic
Signature mode of the device. To enter this mode
write 90h to the device. Subsequent reads at Block
Address 00002h will output the lock status of that
block. The lock status is represented by DQ0 and
DQ1. DQ0 indicates the Block Lock/Unlock status
and is set by the Lock command and cleared by
the Unlock command. it is also automatically set
when entering Lock-Down. DQ1 indicates the
Lock-Down status and is set by the Lock-Down
command. It cannot be cleared by software, only
by a device reset or power-down.
Locking Operations During Erase Suspend.
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After completing any desired lock, read, or program operations,
resume the erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operations cannot be performed during a
program suspend. Refer to Appendix D, Command Interface and Program/Erase Controller
State, for detailed information on which commands are valid during erase suspend.
Table 8. Block Lock Status
Item
Block Lock Configuration
Address
Data
xx002
LOCK
Block is Unlocked
DQ0=0
Block is Locked
DQ0=1
Block is Locked-Down
DQ1=1
Table 9. Lock Status
Current
Lock Status(1)
(WPF, DQ1, DQ0)
Next Lock Status(1)
(WPF, DQ1, DQ0)
Current State
Program/Erase
Allowed
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
After
WPF transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
1,0,1(2)
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
0,0,1(2)
no
0,0,1
0,0,0
0,1,1
1,0,1
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.
3. A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
18/57
M36W432T, M36W432B
Flash Status Register
The Status Register provides information on the
current or previous Program or Erase operation.
The various bits convey information and errors on
the operation. To read the Status register the
Read Status Register command can be issued, refer to Read Status Register Command section. To
output the contents, the Status Register is latched
on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to update
the latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in
Table 10, Status Register Bits. Refer to Table 10
in conjunction with the following text descriptions.
Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device
is ready to process a new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller pauses the bit is High.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Register should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPPF
Status and Block Lock Status bits should be tested
for errors.
Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation
has been suspended or is going to be suspended.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30µs of the Program/Erase Sus-
pend command being issued therefore the memory may still complete the operation rather than
entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set to ‘1’), the Program/
Erase Controller has applied the maximum number of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive).
Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a
hardware reset. If set High it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum
number of pulses to the byte and still failed to verify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive).
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset before a new command is issued, otherwise the new
command will appear to fail.
VPPF Status (Bit 3). The VPPF Status bit can be
used to identify an invalid voltage on the VPPF pin
during Program and Erase operations. The VPPF
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can occur if VPPF becomes invalid during an operation.
When the VPPF Status bit is Low (set to ‘0’), the
voltage on the VPPF pin was sampled at a valid
voltage; when the VPPF Status bit is High (set to
‘1’), the VPPF pin has a voltage that is below the
VPPF Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot
be performed.
Once set High, the VPPF Status bit can only be reset Low by a Clear Status Register command or a
hardware reset. If set High it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
19/57
M36W432T, M36W432B
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program operation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Resume command. The Program Suspend Status
should only be considered valid when the Program/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set within 5µs of
the Program/Erase Suspend command being issued therefore the memory may still complete the
operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the
contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been attempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.
Table 10. Status Register Bits
Bit
7
6
5
4
3
2
1
0
Name
Logic Level
Definition
'1'
Ready
'0'
Busy
'1'
Suspended
'0'
In progress or Completed
'1'
Erase Error
'0'
Erase Success
'1'
Program Error
'0'
Program Success
'1'
VPPF Invalid, Abort
'0'
VPPF OK
'1'
Suspended
'0'
In Progress or Completed
'1'
Program/Erase on protected block, Abort
'0'
No operation to protected blocks
P/E.C. Status
Erase Suspend Status
Erase Status
Program Status
VPPF Status
Program Suspend Status
Block Protection Status
Reserved
Note: Logic level '1' is High, '0' is Low.
SRAM Operations
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable, WS, is at VIH, Output Enable, GS, is at VIL, Chip Enable, E1S, is at
20/57
VIL, Chip Enable, E2S, is at VIH, and Byte Enables,
UBS and LBS are at VIL.
Valid data will be available on the output pins after
a time of tAVQV after the last stable address. If the
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines
will always be valid at tAVQV (see Table 19, Figures
13 and 14).
M36W432T, M36W432B
Write. Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
WS and E1S are at VIL, and E2S is at VIH. Either
the Chip Enable inputs, E1S and E2S, or the Write
Enable input, WS, must be deasserted during address transitions for subsequent write cycles.
A Write operation is initiated when E1S is at VIL,
E2S is at VIH and WS is at VIL. The data is latched
on the falling edge of E1S, the rising edge of E2S
or the falling edge of WS, whichever occurs last.
The Write cycle is terminated on the rising edge of
E1S, the rising edge of WS or the falling edge of
E2S, whichever occurs first.
If the Output is enabled (E1S=VIL, E2S=VIH and
GS=VIL), then WS will return the outputs to high
impedance within tWLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. The Data input must be valid for tDVWH before the rising edge of Write Enable, for
tDVE1H before the rising edge of E1S or for tDVE2L
before the falling edge of E2S, whichever occurs
first, and remain valid for tWHDX, tE1HAX or tE2LAX
(see Table 20, Figure 16, 17, 18 and 19).
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which invokes an automatic standby mode (see Table 19,
Figure 15). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S at VIH
or E2S at VIL.
Data Retention. The SRAM data retention performances as VDDS goes down to VDR are described in Table 21 and Figure 20, 21. In E1S
controlled data retention mode, the minimum
standby current mode is entered when
E1S ≥ VDDS – 0.2V
and
E2S ≤ 0.2V
or
E2S ≥ VDDS – 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S ≤ 0.2V.
Output Disable. The data outputs are high impedance when the Output Enable, GS, is at VIH
with Write Enable, WS, at VIH.
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 11. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
Ambient Operating Temperature (1)
–40
85
°C
TBIAS
Temperature Under Bias
–40
125
°C
TSTG
Storage Temperature
–55
155
°C
Input or Output Voltage
–0.5
VDDQF +0.3
V
Flash Supply Voltage
–0.6
3.9
V
VPPF
Program Voltage
–0.6
13
V
VDDS
SRAM Supply Voltage
–0.5
3.9
V
TA
VIO
VDDF, VDDQF
Note: 1. Depends on range.
21/57
M36W432T, M36W432B
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 12,
Operating and AC Measurement Conditions. Designers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Parameter
SRAM
Flash Memory
70
70/85
Units
Min
Max
Min
Max
–
–
2.7
3.3
V
VDDQ F = VDDS Supply Voltage
2.7
3.3
2.7
3.3
V
Ambient Operating Temperature
– 40
85
– 40
85
°C
VDDF Supply Voltage
Load Capacitance (CL)
50
50
Input Rise and Fall Times
pF
5
Input Pulse Voltages
Input and Output Timing Ref. Voltages
5
ns
0 to VDDQF
0 to VDDQF
V
VDDQF/2
VDDQF/2
V
Figure 8. AC Measurement Load Circuit
Figure 7. AC Measurement I/O Waveform
VDDQF
VDDQ
VDDQ/2
VDDQF
VDDF
0V
25kΩ
AI05205
DEVICE
UNDER
TEST
Note: VDDQ means VDDQF = VDDS
CL
0.1µF
25kΩ
0.1µF
CL includes JIG capacitance
AI05206
Table 13. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
22/57
Test Condition
Typ
Max
Unit
VIN = 0V, f=1 MHz
12
14
pF
VOUT = 0V, f=1 MHz
20
22
pF
M36W432T, M36W432B
Table 14. DC Characteristics
Symbol
Parameter
Device
Test Condition
Min
Typ
Max
Unit
ILI
Input Leakage Current
Flash &
SRAM
0V ≤ VIN ≤ VDDQF
±2
µA
ILO
Output Leakage Current
Flash &
SRAM
0V ≤ VOUT ≤ VDDQF,
SRAM Outputs Hi-Z
±10
µA
Flash
EF = VDDQF ± 0.2V
VDDQF = VDDF max
15
50
µA
SRAM
E1S = E2S ≥ VDDS – 0.2V
or E2S ≤ 0.2V
20
50
µA
Flash
RPF = VSSF ± 0.2V
15
50
µA
VIN ≤ VDDS – 0.2V
or VIN ≤ 0.2V
IIO = 0 mA, cycle time = 1µs
1
2
mA
VIN ≤ VDDS – 0.2V
or VIN ≤ 0.2V
IIO = 0 mA, min cycle time
7
12
mA
IDDS
IDDD
IDD
VDD Standby Current
Supply Current (Reset)
Supply Current
SRAM
IDDR
Supply Current (Read)
Flash
EF = VIL, GF = VIH, f = 5 MHz
10
20
mA
IDDW
Supply Current (Program)
Flash
Program in progress
10
20
mA
IDDE
Supply Current (Erase)
Flash
Erase in progress
5
20
mA
IDDES
Supply Current
(Erase Suspend)
Flash
Erase Suspend in progress
50
µA
IDDWS
Supply Current
(Program Suspend)
Flash
Program Suspend in progress
50
µA
Program Current
(Standby)
Flash
Program Current
(Read)
Flash
IPPW
Program Current
(Program)
IPPE
VPPF ≤ VDDQF
0.2
5
µA
VPPF > VDDF
100
400
µA
VPPF ≤ VDDQF
0.2
5
µA
VPPF = VDDF
100
400
µA
Flash
VPPF = 12V ± 0.6V
Program in progress
5
10
mA
Program Current
(Erase)
Flash
VPPF = 12V ± 0.6V
Program in progress
5
10
mA
VIL
Input Low Voltage
Flash &
SRAM
VDDQF = VDDS ≥ 2.7V
– 0.3
0.8
V
VIH
Input High Voltage
Flash &
SRAM
VDDQF = VDDS ≥ 2.7V
2.2
VDDQF
+0.3
V
VOL
Output Low Voltage
Flash &
SRAM
VDDQF = VDDS = VDD min
IOL = 100µA
0.1
V
VOH
Output High Voltage
Flash &
SRAM
VDDQF = VDDS = VDD min
IOH = –100µA
VPPL
Program Voltage (Program or
Erase operations)
IPPS
IPPR
Flash
VDDQ
–0.1
2.7
V
3.3
V
23/57
M36W432T, M36W432B
Symbol
Parameter
Device
VPPH
Program Voltage
(Program or Erase operations)
Flash
VPPLK
Program Voltage
(Program and Erase lock-out)
VLKO
VDDF Supply Voltage (Program
and Erase lock-out)
Test Condition
Min
Typ
Max
Unit
12.6
V
Flash
1
V
Flash
2
V
11.4
Figure 9. Flash Read AC Waveforms
tAVAV
VALID
A0-A20
tAVQV
tAXQX
EF
tELQV
tELQX
tEHQX
tEHQZ
GF
tGLQV
tGHQX
tGLQX
tGHQZ
VALID
DQ0-DQ15
OUTPUTS
ENABLED
ADDR. VALID
CHIP ENABLE
DATA VALID
STANDBY
AI05207
Table 15. Flash Read AC Characteristics
Flash
Symbol
Alt
Parameter
Unit
70
85
tAVAV
tRC
Address Valid to Next Address Valid
Min
70
85
ns
tAVQV
tACC
Address Valid to Output Valid
Max
70
85
ns
tAXQX (1)
tOH
Address Transition to Output Transition
Min
0
0
ns
tEHQX (1)
tOH
Chip Enable High to Output Transition
Min
0
0
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
Max
20
20
ns
tELQV (2)
tCE
Chip Enable Low to Output Valid
Max
70
85
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
Min
0
0
ns
tGHQX (1)
tOH
Output Enable High to Output Transition
Min
0
0
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
Max
20
20
ns
tGLQV (2)
tOE
Output Enable Low to Output Valid
Max
20
20
ns
24/57
M36W432T, M36W432B
Flash
Symbol
tGLQX (1)
Alt
tOLZ
Parameter
Output Enable Low to Output Transition
Unit
Min
70
85
0
0
ns
Note: 1. Sampled only, not 100% tested.
2. GF may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV.
25/57
26/57
VPPF
WPF
DQ0-DQ15
WF
GF
EF
A0-A20
tWLWH
COMMAND
SET-UP COMMAND
tDVWH
tELWL
tWHDX
tWHWL
tWHEH
CMD or DATA
CONFIRM COMMAND
OR DATA INPUT
tVPHWH
tWPHWH
tAVWH
VALID
tAVAV
tWHEL
tWHGL
tWHAX
PROGRAM OR ERASE
AI05208
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
M36W432T, M36W432B
Figure 10. Flash Write AC Waveforms, Write Enable Controlled
M36W432T, M36W432B
Table 16. Flash Write AC Characteristics, Write Enable Controlled
Flash
Symbol
Alt
Parameter
Unit
70
85
tAVAV
tWC
Write Cycle Time
Min
70
85
ns
tAVWH
tAS
Address Valid to Write Enable High
Min
45
45
ns
tDVWH
tDS
Data Valid to Write Enable High
Min
45
45
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
Chip Enable Low to Output Valid
Min
70
85
ns
Output Valid to VPPF Low
Min
0
0
ns
Output Valid to Write Protect Low
Min
0
0
ns
tELQV
tQVVPL (1,2)
tQVWPL
tVPHWH (1)
tVPS
VPPF High to Write Enable High
Min
200
200
ns
tWHAX
tAH
Write Enable High to Address Transition
Min
0
0
ns
tWHDX
tDH
Write Enable High to Data Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHEL
Write Enable High to Output Enable Low
Min
25
25
ns
tWHGL
Write Enable High to Output Enable Low
Min
20
20
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
25
25
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
45
ns
Write Protect High to Write Enable High
Min
45
45
ns
tWPHWH
Note: 1. Sampled only, not 100% tested.
2. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).
27/57
28/57
VPPF
WPF
DQ0-DQ15
EF
GF
WF
A0-A20
tELEH
COMMAND
POWER-UP AND
SET-UP COMMAND
tDVEH
tWLEL
tEHDX
tEHEL
tEHWH
CMD or DATA
CONFIRM COMMAND
OR DATA INPUT
tVPHEH
tWPHEH
tAVEH
VALID
tAVAV
tEHGL
tEHAX
PROGRAM OR ERASE
AI05209
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
M36W432T, M36W432B
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled
M36W432T, M36W432B
Table 17. Flash Write AC Characteristics, Chip Enable Controlled
Flash
Symbol
Alt
Parameter
Unit
70
85
tAVAV
tWC
Write Cycle Time
Min
70
85
ns
tAVEH
tAS
Address Valid to Chip Enable High
Min
45
45
ns
tDVEH
tDS
Data Valid to Chip Enable High
Min
45
45
ns
tEHAX
tAH
Chip Enable High to Address Transition
Min
0
0
ns
tEHDX
tDH
Chip Enable High to Data Transition
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
25
25
ns
Chip Enable High to Output Enable Low
Min
25
25
ns
tEHGL
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
45
ns
Chip Enable Low to Output Valid
Min
70
85
ns
Output Valid to VPPF Low
Min
0
0
ns
Data Valid to Write Protect Low
Min
0
0
ns
tELQV
tQVVPL (1,2)
tQVWPL
tVPHEH (1)
tVPS
VPPF High to Chip Enable High
Min
200
200
ns
tWLEL
tCS
Write Enable Low to Chip Enable Low
Min
0
0
ns
Write Protect High to Chip Enable High
Min
45
45
ns
tWPHEH
Note: 1. Sampled only, not 100% tested.
2. Applicable if VPPF is seen as a logic input (VPPF < 3.6V).
29/57
M36W432T, M36W432B
Figure 12. Flash Power-Up and Reset AC Waveforms
WF, EF,GF
tPHWL
tPHEL
tPHGL
tPHWL
tPHEL
tPHGL
RPF
tVDHPH
tPLPH
VDDF, VDDQF
Power-Up
Reset
AI05210
Table 18. Flash Power-Up and Reset AC Characteristics
Flash
Symbol
tPHWL
tPHEL
tPHGL
Parameter
Reset High to Write Enable Low, Chip Enable
Low, Output Enable Low
Test Condition
Unit
70
85
During
Program and
Erase
Min
50
50
µs
others
Min
30
30
ns
tPLPH(1,2)
Reset Low to Reset High
Min
100
100
ns
tVDHPH(3)
Supply Voltages High to Reset High
Min
50
50
µs
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.
2. Sampled only, not 100% tested.
3. It is important to assert RPF in order to allow proper CPU initialization during power up or reset.
30/57
M36W432T, M36W432B
Figure 13. SRAM Read AC Waveforms, Address Controlled with UBS = LBS = VIL
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DQ0-DQ15
DATA VALID
DATA VALID
AI05211
Note: E1S = Low, E2S = High, GS = Low, WS = High.
Figure 14. SRAM Read AC Waveforms, E1S, E2S or GS Controlled
tAVAV
VALID
A0-A17
tAVQV
tAXQX
tE1LQV
tE1HQZ
E1S
tE1LQX
tE2HQV
tE2LQZ
E2S
tE2HQX
tBLQV
tBHQZ
UBS, LBS
tBLQX
tGLQV
tGHQZ
GS
tGLQX
DQ0-DQ15
DATA VALID
AI05212
31/57
M36W432T, M36W432B
Figure 15. SRAM Standby AC Waveforms
E1S
E2S
tPU
IDD
tPD
50%
AI05213
Table 19. SRAM Read AC Characteristics
SRAM
Symbol
Alt
Parameter
Unit
Min
Max
tAVAV
tRC
Read Cycle Time
tAVQV
tAA
Address Valid to Output Valid
tAXQX
tOH
Address Transition to Output Transition
tBHQZ
tBHZ
UBS, LBS Disable to Hi-Z Output
25
ns
tBLQV
tBA
UBS, LBS Access Time
70
ns
tBLQX
tBLZ
UBS, LBS Enable to Low-Z Output
tE1HQZ
tHZ1
Chip Enable 1 High to Output Hi-Z
25
ns
tE1LQV
tCO1
Chip Enable 1 Low to Output Valid
70
ns
tE1LQX
tLZ1
Chip Enable 1 Low to Output Transition
tE2HQV
tCO2
Chip Enable 2 High to Output Valid
tE2HQX
tLZ2
Chip Enable 2 High to Output Transition
tE2LQZ
tHZ2
Chip Enable 2 Low to Output Hi-Z
25
ns
tGHQZ
tOHZ
Output Enable High to Output Hi-Z
25
ns
tGLQV
tOE
Output Enable Low to Output Valid
35
ns
tGLQX
tOLZ
Output Enable Low to Output Transition
tPD (1)
Chip Enable 1 High or Chip Enable 2 Low to Power Down
tPU (1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
Note: 1. Sampled only. Not 100% tested.
32/57
70
ns
70
10
ns
10
ns
10
ns
70
10
ns
ns
5
ns
70
0
ns
ns
ns
M36W432T, M36W432B
Figure 16. SRAM Write AC Waveforms, WS Controlled with GS Low
tAVAV
VALID
A0-A17
tAVWH
tE1LWH
tAVE1L
tWHAX
E1S
tAVE2H
E2S
tE2HWH
tBLWH
UBS, LBS
tAVWL
tWLWH
WS
tWHQX
tWLQZ
tDVWH
DQ0-DQ15
tWHDX
INPUT VALID
AI05214
Figure 17. SRAM Write AC Waveforms, WS Controlled with GS High
tAVAV
VALID
A0-A17
tAVWH
tE1LWH
tAVE1L
tWHAX
E1S
tAVE2H
E2S
tE2HWH
tBLWH
UBS, LBS
tAVWL
tWLWH
WS
GS
tWHQX
tGHQZ
DQ0-DQ15
tDVWH
tWHDX
INPUT VALID
AI05215
33/57
M36W432T, M36W432B
Figure 18. SRAM Write AC Waveforms, UBS and LBS Controlled
tAVAV
VALID
A0-A17
tE1LWH
tE1HAX
E1S
tAVWH
E2S
tE2HWH
tAVWL
tBLWH
UBS, LBS
tWLWH
WS
tDVWH
tWHDX
DATA VALID
DQ0-DQ15
AI05216
Figure 19. SRAM Write AC Waveforms, E1S Controlled
tAVAV
VALID
A0-A17
tAVE1L
tE1LWH
tE1HAX
E1S
E2S
tBLWH
UBS, LBS
tAVWL
WS
tDVE1H
DQ0-DQ15
tWHDX
INPUT VALID
AI05217
34/57
M36W432T, M36W432B
Table 20. SRAM Write AC Characteristics
SRAM
Symbol
Alt
Parameter
Unit
Min
tAVAV
tWC
tAVE1L
tAS (1)
tAVE2H
Write Cycle Time
Max
70
ns
Address Valid to Chip Enable 1 Low
0
ns
tAS (1)
Address Valid to Chip Enable 2 High
0
ns
tAVWH
tAW
Address Valid to Write Enable High
60
ns
tAVWL
tAS (1)
Address Valid to Write Enable Low
0
ns
tBLWH
tBW
UBS, LBS Valid to End of Write
60
ns
tDVE1H
tDW
Input Valid to Chip Enable 1 High
30
ns
tDVE2L
tDW
Input Valid to Chip Enable 2 Low
30
ns
tDVWH
tDW
Input Valid to Write Enable High
30
ns
tE1HAX
tWR (2)
Chip Enable 1 High to Address Transition
0
ns
tE1LWH,
tE2HWH
tCW (3)
Chip Select to End of Write
60
ns
tE2LAX
tWR (2)
Chip Enable 2 Low to Address Transition
0
ns
tGHQZ
tGHZ
tWHAX
tWR (2)
tWHDX
Output Enable High to Output Hi-Z
25
ns
Write Enable High to Address Transition
0
ns
tDH
Write Enable High to Input Transition
0
ns
tWHQX
tOW
Write Enable High to Output Transition
10
ns
tWLQZ
tWHZ
Write Enable Low to Output Hi-Z
tWLWH
tWP (4)
Note: 1.
2.
3.
4.
Write Enable Pulse Width
25
50
ns
ns
tAS is measured from the address valid to the beginning of write.
tWR is measured from the end or write to the address change. tWR applied in case a write ends as E1S or WS going high.
tCW is measured from E1S going low end of write.
A Write occurs during the overlap (tWP) of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the earliest transition when E1S goes high and WS goes high. The tWP is measured from the beginning of write to the end of write.
35/57
M36W432T, M36W432B
Figure 20. SRAM Low VDDS Data Retention AC Waveforms, E1S Controlled
tCDR
tR
DATA RETENTION MODE
VDDS
2.8 V
VDR ≥ 1.5V
1.5 V
E1S ≥ VDDS – 0.2V
E1S
VSSS
AI05218
Figure 21. SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled
DATA RETENTION MODE
VDDS
2.8 V
E2S
tCDR
1.5 V
VDR ≥ 1.5V
tR
E2S ≤ 0.2V
0.4 V
VSSS
AI05219
Table 21. SRAM Low VDDS Data Retention Characteristic
Symbol
Parameter
Test Condition
IDDDR
Supply Current (Data Retention)
VDDS = 3.3V, E1S ≥ VDDS – 0.2V,
E2S ≥ VDDS – 0.2V or E2S ≤ 0.2V
VDR
Supply Voltage (Data Retention)
E1S ≥ VDDS – 0.2V, E2S ≤ 0.2V
1.5
tCDR
Chip Disable to Power Down
E1S ≥ VDDS – 0.2V, E2S ≤ 0.2V
0
ns
tRC
ns
tR
Operation Recovery Time
Note: 1. All other Inputs VIH ≤ VDD –0.2V or VIL ≤ 0.2V.
2. Sampled only. Not 100% tested.
36/57
Min
Max
Unit
15
µA
3.3
V
M36W432T, M36W432B
PACKAGE MECHANICAL
Figure 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline
D
D2
D1
SE
b
BALL "A1"
e
E E1
FE
FD
SD
ddd
e
A
A2
A1
BGA-Z12
Note: Drawing is not to scale.
Table 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data
Symbol
millimeters
Typ
Min
A
inches
Max
Typ
Min
1.400
A1
0.0551
0.250
A2
0.0098
1.100
b
0.400
0.350
Max
0.450
0.0433
0.0157
0.0138
0.0177
D
12.000
–
–
0.4724
–
–
D1
5.600
–
–
0.2205
–
–
D2
8.800
–
–
0.3465
–
–
ddd
0.100
0.0039
E
8.000
–
–
0.3150
–
–
E1
5.600
–
–
0.2205
–
–
e
0.800
–
–
0.0315
–
–
FD
1.600
–
–
0.0630
–
–
FE
1.200
–
–
0.0472
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
37/57
M36W432T, M36W432B
Figure 23. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package)
#1
#2
1
2
3
4
5
6
7
8
#3
#4
A
B
C
D
E
F
G
H
AI05220
38/57
M36W432T, M36W432B
Figure 24. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)
END
POINT
START
POINT
#1
#2
1
2
3
4
5
6
7
8
#3
#4
A
B
C
D
E
F
G
H
AI05221
39/57
M36W432T, M36W432B
PART NUMBERING
Table 23. Ordering Information Scheme
Example:
M36W432T
70 ZA
6
T
Device Type
M36 = MMP (Flash + SRAM)
Operating Voltage
W = VDDF = 2.7V to 3.3V, VDDS = VDDQF = 2.7V to 3.3V
SRAM Chip Size & Organization
4 = 4 Mbit (256K x 16 bit)
Device Function
32 = 32 Mbit (x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70ns
85 = 85ns
Package
ZA = LFBGA66: 0.8mm pitch
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Option
T = Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
Table 24. Daisy Chain Ordering Scheme
Example:
M36W432
-ZA T
Device Type
M36W432
Daisy Chain
-ZA = LFBGA66: 0.8mm pitch
Option
T = Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
40/57
M36W432T, M36W432B
REVISION HISTORY
Table 25. Document Revision History
Date
Version
Revision Details
19-Jun-2001
-01
First Issue
16-Jul-2001
-02
Flash Commands Table corrections: Protect/Lock, Unprotect/Unlock, Lock/LockDown
11-Feb-2002
-03
Package mechanical data clarified (Table 22)
41/57
M36W432T, M36W432B
APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES
Table 26. Top Boot Block Addresses,
M36W432T
#
Size
(KWord)
Address Range
0
4
1FF000-1FFFFF
1
4
1FE000-1FEFFF
2
4
1FD000-1FDFFF
3
4
1FC000-1FCFFF
4
4
1FB000-1FBFFF
5
4
1FA000-1FAFFF
6
4
1F9000-1F9FFF
7
4
1F8000-1F8FFF
8
32
1F0000-1F7FFF
9
32
1E8000-1EFFFF
10
32
1E0000-1E7FFF
11
32
1D8000-1DFFFF
12
32
1D0000-1D7FFF
13
32
1C8000-1CFFFF
14
32
1C0000-1C7FFF
15
32
1B8000-1BFFFF
16
32
1B0000-1B7FFF
17
32
1A8000-1AFFFF
18
32
1A0000-1A7FFF
19
32
198000-19FFFF
20
32
190000-197FFF
21
32
188000-18FFFF
22
32
180000-187FFF
23
32
178000-17FFFF
24
32
170000-177FFF
25
32
168000-16FFFF
26
32
160000-167FFF
27
32
158000-15FFFF
28
32
150000-157FFF
29
32
148000-14FFFF
30
32
140000-147FFF
31
32
138000-13FFFF
32
32
130000-137FFF
33
32
128000-12FFFF
42/57
34
32
120000-127FFF
35
32
118000-11FFFF
36
32
110000-117FFF
37
32
108000-10FFFF
38
32
100000-107FFF
39
32
0F8000-0FFFFF
40
32
0F0000-0F7FFF
41
32
0E8000-0EFFFF
42
32
0E0000-0E7FFF
43
32
0D8000-0DFFFF
44
32
0D0000-0D7FFF
45
32
0C8000-0CFFFF
46
32
0C0000-0C7FFF
47
32
0B8000-0BFFFF
48
32
0B0000-0B7FFF
49
32
0A8000-0AFFFF
50
32
0A0000-0A7FFF
51
32
098000-09FFFF
52
32
090000-097FFF
53
32
088000-08FFFF
54
32
080000-087FFF
55
32
078000-07FFFF
56
32
070000-077FFF
57
32
068000-06FFFF
58
32
060000-067FFF
59
32
058000-05FFFF
60
32
050000-057FFF
61
32
048000-04FFFF
62
32
040000-047FFF
63
32
038000-03FFFF
64
32
030000-037FFF
65
32
028000-02FFFF
66
32
020000-027FFF
67
32
018000-01FFFF
68
32
010000-017FFF
69
32
008000-00FFFF
70
32
000000-007FFF
M36W432T, M36W432B
Table 27. Bottom Boot Block Addresses,
M36W432B
#
Size
(KWord)
Address Range
70
32
1F8000-1FFFFF
69
32
1F0000-1F7FFF
68
32
1E8000-1EFFFF
67
32
1E0000-1E7FFF
66
32
1D8000-1DFFFF
65
32
1D0000-1D7FFF
64
32
1C8000-1CFFFF
63
32
1C0000-1C7FFF
62
32
1B8000-1BFFFF
61
32
1B0000-1B7FFF
60
32
1A8000-1AFFFF
59
32
1A0000-1A7FFF
58
32
198000-19FFFF
57
32
190000-197FFF
56
32
188000-18FFFF
55
32
180000-187FFF
54
32
178000-17FFFF
53
32
170000-177FFF
52
32
168000-16FFFF
51
32
160000-167FFF
50
32
158000-15FFFF
49
32
150000-157FFF
48
32
148000-14FFFF
47
32
140000-147FFF
46
32
138000-13FFFF
45
32
130000-137FFF
44
32
128000-12FFFF
43
32
120000-127FFF
42
32
118000-11FFFF
41
32
110000-117FFF
40
32
108000-10FFFF
39
32
100000-107FFF
38
32
0F8000-0FFFFF
37
32
0F0000-0F7FFF
36
32
0E8000-0EFFFF
35
32
0E0000-0E7FFF
34
32
0D8000-0DFFFF
33
32
0D0000-0D7FFF
32
32
0C8000-0CFFFF
31
32
0C0000-0C7FFF
30
32
0B8000-0BFFFF
29
32
0B0000-0B7FFF
28
32
0A8000-0AFFFF
27
32
0A0000-0A7FFF
26
32
098000-09FFFF
25
32
090000-097FFF
24
32
088000-08FFFF
23
32
080000-087FFF
22
32
078000-07FFFF
21
32
070000-077FFF
20
32
068000-06FFFF
19
32
060000-067FFF
18
32
058000-05FFFF
17
32
050000-057FFF
16
32
048000-04FFFF
15
32
040000-047FFF
14
32
038000-03FFFF
13
32
030000-037FFF
12
32
028000-02FFFF
11
32
020000-027FFF
10
32
018000-01FFFF
9
32
010000-017FFF
8
32
008000-00FFFF
7
4
007000-007FFF
6
4
006000-006FFF
5
4
005000-005FFF
4
4
004000-004FFF
3
4
003000-003FFF
2
4
002000-002FFF
1
4
001000-001FFF
0
4
000000-000FFF
43/57
M36W432T, M36W432B
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 28, 29,
30, 31, 32 and 33 show the addresses used to retrieve the data.
The CFI data structure also contains a security
area where a 64 bit unique security number is written (see Table 33, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security number after it has been written by ST. Issue a Read
command to return to Read mode.
Table 28. Query Structure Overview
Offset
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Note: Query data are always presented on the lowest order data outputs.
Table 29. CFI Query Identification String
Offset
Data
Description
00h
0020h
Manufacturer Code
01h
88BAh
88BBh
Device Code
02h-0Fh
reserved
10h
0051h
11h
0052h
12h
0059h
13h
0003h
14h
0000h
15h
0035h
16h
0000h
17h
0000h
18h
0000h
19h
0000h
1Ah
0000h
ST
Top
Bottom
Reserved
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 31)
Intel
compatible
P = 35h
Alternate Vendor Command Set and Control Interface ID Code second vendor specified algorithm supported (0000h means none exists)
NA
Address for Alternate Algorithm extended Query table
(0000h means none exists)
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
44/57
Value
M36W432T, M36W432B
Table 30. CFI Query System Interface Information
Offset
Data
Description
Value
1Bh
0027h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
2.7V
1Ch
0036h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
3.6V
1Dh
00B4h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 mV
11.4V
1Eh
00C6h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 mV
12.6V
1Fh
0004h
Typical timeout per single word program = 2n µs
16µs
20h
0004h
Typical timeout for Double Word Program = 2n µs
16µs
21h
000Ah
Typical timeout per individual block erase = 2n ms
1s
22h
0000h
Typical timeout for full chip erase = 2n ms
NA
23h
0005h
Maximum timeout for word program = 2n times typical
512µs
24h
0005h
Maximum timeout for Double Word Program = 2n times typical
512µs
25h
0003h
Maximum timeout per individual block erase = 2n times typical
8s
26h
0000h
Maximum timeout for chip erase = 2n times typical
NA
45/57
M36W432T, M36W432B
Table 31. Device Geometry Definition
Data
27h
0016h
Device Size = 2n in number of bytes
28h
29h
0001h
0000h
Flash Device Interface Code description
2Ah
2Bh
0002h
0000h
Maximum number of bytes in multi-byte program or page = 2n
4
2Ch
0002h
Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.
2
2Dh
2Eh
003Eh
0000h
Region 1 Information
Number of identical-size erase block = 003Eh+1
63
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase block = 0007h+1
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
31h
32h
003Eh
0000h
Region 2 Information
Number of identical-size erase block = 003Eh=1
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
M36W432B
M36W432T
Offset Word
Mode
46/57
Description
Value
4 MByte
x16
Async.
64 KByte
8
8 KByte
8
8 KByte
63
64 KByte
M36W432T, M36W432B
Table 32. Primary Algorithm-Specific Extended Query Table
Offset
P = 35h (1)
Data
(P+0)h = 35h
0050h
(P+1)h = 36h
0052h
(P+2)h = 37h
0049h
(P+3)h = 38h
0031h
Major version number, ASCII
"1"
(P+4)h = 39h
0030h
Minor version number, ASCII
"0"
(P+5)h = 3Ah
0066h
(P+6)h = 3Bh
0000h
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
(P+7)h = 3Ch
0000h
(P+8)h = 3Dh
0000h
(P+9)h = 3Eh
0001h
(P+A)h = 3Fh
0003h
(P+B)h = 40h
0000h
Description
Value
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
8
31 to 9
Chip Erase supported
Suspend Erase supported
Suspend Program supported
Legacy Lock/Unlock supported
Queued Erase supported
Instant individual block locking supported
Protection bits supported
Page mode read supported
Synchronous read supported
Reserved; undefined bits are ‘0’
(1
(1
(1
(1
(1
(1
(1
(1
(1
= Yes,
= Yes,
= Yes,
= Yes,
= Yes,
= Yes,
= Yes,
= Yes,
= Yes,
0 = No)
0 = No)
0 = No)
0 = No)
0 = No)
0 = No)
0 = No)
0 = No)
0 = No)
No
Yes
Yes
No
No
Yes
Yes
No
No
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
bit 0
Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
Yes
Block Lock Status : Defines which bits in the Block Status Register section of
the Query are implemented.
Address (P+A)h contains less significant byte
bit 0
Block Lock Status bit active
(1 = Yes, 0 = No)
bit 1
Block Lock-Down Status bit active
(1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Yes
Yes
(P+C)h = 41h
0030h
VDD Logic Supply Optimum Program/Erase voltage (highest performance)
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
3V
(P+D)h = 42h
00C0h
VPP Supply Optimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12V
(P+E)h = 43h
0001h
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
01
(P+F)h = 44h
0080h
80h
(P+10)h = 45h
0000h
(P+11)h = 46h
0003h
(P+12)h = 47h
0003h
Protection Field 1: Protection Description
This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-programmable.
bit 0 to 7
Lock/bytes JEDEC-plane physical low address
bit 8 to 15
Lock/bytes JEDEC-plane physical high address
bit 16 to 23
"n" such that 2n = factory pre-programmed bytes
bit 24 to 31
"n" such that 2n = user programmable bytes
(P+13)h = 48h
00h
8 Byte
8 Byte
Reserved
Note: 1. See Table 29, offset 15 for P pointer definition.
47/57
M36W432T, M36W432B
Table 33. Security Code Area
Offset
Data
80h
00XX
81h
XXXX
82h
XXXX
83h
XXXX
84h
XXXX
85h
XXXX
86h
XXXX
87h
XXXX
88h
XXXX
48/57
Description
Protection Register Lock
64 bits: unique device number
64 bits: User Programmable OTP
M36W432T, M36W432B
APPENDIX C. FLASH MEMORY FLOWCHARTS AND PSEUDO CODES
Figure 25. Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
/*or writeToFlash (any_address, 0x10) ; */
Write 40h or 10h
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
Read Status
Register
b7 = 1
NO
} while (status_register.b7== 0) ;
YES
b3 = 0
NO
VPPF Invalid
Error (1, 2)
NO
Program
Error (1, 2)
NO
Program to Protected
Block Error (1, 2)
if (status_register.b3==1) /*VPPF invalid error */
error_handler ( ) ;
YES
b4 = 0
if (status_register.b4==1) /*program error */
error_handler ( ) ;
YES
b1 = 0
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI05222
Note: 1. Status check of b1 (Protected Block), b3 (VPPF Invalid) and b4 (Program Error) can be made after each program operation or after
a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
49/57
M36W432T, M36W432B
Figure 26. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 1
& Data 1 (3)
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
Read Status
Register
b7 = 1
NO
} while (status_register.b7== 0) ;
YES
b3 = 0
NO
VPPF Invalid
Error (1, 2)
NO
Program
Error (1, 2)
NO
Program to Protected
Block Error (1, 2)
if (status_register.b3==1) /*VPPF invalid error */
error_handler ( ) ;
YES
b4 = 0
if (status_register.b4==1) /*program error */
error_handler ( ) ;
YES
b1 = 0
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI05223
Note: 1. Status check of b1 (Protected Block), b3 (VPPF Invalid) and b4 (Program Error) can be made after each program operation or after
a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
50/57
M36W432T, M36W432B
Figure 27. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
Read Status
Register
b7 = 1
NO
} while (status_register.b7== 0) ;
YES
b2 = 1
NO
Program Complete
YES
Write FFh
}
Read data from
another address
Write D0h
if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
}
Write FFh
}
Program Continues
Read Data
AI05224
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M36W432T, M36W432B
Figure 28. Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
Read Status
Register
b7 = 1
NO
} while (status_register.b7== 0) ;
YES
b3 = 0
NO
VPPF Invalid
Error (1)
YES
Command
Sequence Error (1)
if (status_register.b3==1) /*VPPF invalid error */
error_handler ( ) ;
YES
b4, b5 = 1
if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
error_handler ( ) ;
NO
b5 = 0
NO
Erase Error (1)
if ( (status_register.b5==1) )
/* erase error */
error_handler ( ) ;
YES
b1 = 0
NO
Erase to Protected
Block Error (1)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI05225
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
52/57
M36W432T, M36W432B
Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
{
status_register=readFlash (any_address) ;
/* EF or GF must be toggled*/
Read Status
Register
b7 = 1
NO
} while (status_register.b7== 1) ;
YES
b6 = 1
NO
Erase Complete
YES
if (status_register.b6==1) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
Write D0h
}
else
{ read_program_data ( );
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
Write FFh
}
Erase Continues
Read Data
AI05226
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M36W432T, M36W432B
Figure 30. Locking Operations Flowchart and Pseudo Code
Start
locking_operation_command (address, lock_operation) {
writeToFlash (any_address, 0x60) ; /*configuration setup*/
Write 60h
if (lock_operation==PROTECT) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNPROTECT) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK) /*to lock the block*/
writeToFlash (address, 0x2F) ;
Write
01h, D0h or 2Fh
writeToFlash (any_address, 0x90) ;
Write 90h
Read Status
Register
Locking
change
confirmed?
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
NO
YES
writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/
Write FFh
}
End
AI05227
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M36W432T, M36W432B
APPENDIX D. FLASH MEMORY COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER
STATE
Table 34. Write State Machine Current/Next, sheet 1 of 2
Current
State
SR
bit 7
Data
When
Read
Read Array
“1”
Array
Command Input (and Next State)
Read
Array
(FFh)
Program
Setup
(10/40h)
Erase
Confirm
(D0h)
Prog/Ers
Resume
(D0h)
Read
Status
(70h)
Clear
Status
(50h)
Read Array
Read Sts.
Read Array
Read Array
Erase
Setup
Read Array
Read
Status
Read Array
Electronic
Signature
Read Array
Program
Setup
Erase
Setup
Read Array
Read
Status
Read Array
“1”
CFI
Read Array
Program
Setup
Erase
Setup
Read Array
Read
Status
Read Array
Lock Setup
“1”
Status
Lock Cmd
Error
“1”
Status
Read Array
Program
Setup
Erase
Setup
Read Array
Read
Status
Read Array
Lock
(complete)
“1”
Status
Read Array
Program
Setup
Erase
Setup
Read Array
Read
Status
Read Array
Prot. Prog.
Setup
“1”
Status
Protection Register Program
Prot. Prog.
(continue)
“0”
Status
Protection Register Program continue
Prot. Prog.
(complete)
“1”
Status
Read
Status
Read Array
Prog. Setup
“1”
Status
Program
(continue)
“0”
Status
Prog. Sus
Status
“1”
Status
Prog. Sus
Read Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read Array
Program
(continue)
Prog. Sus
Read Sts
Prog. Sus
Read Array
Prog. Sus
Read Array
“1”
Array
Prog. Sus
Read Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read Array
Program
(continue)
Prog. Sus
Read Sts
Prog. Sus
Read Array
Prog. Sus
Read
Elect.Sg.
“1”
Electronic
Signature
Prog. Sus
Read Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read Array
Program
(continue)
Prog. Sus
Read Sts
Prog. Sus
Read Array
Prog. Sus
Read CFI
“1”
CFI
Prog. Sus
Read Array
Program Suspend to
Read Array
Program
(continue)
Prog. Sus
Read Array
Program
(continue)
Prog. Sus
Read Sts
Prog. Sus
Read Array
Program
(complete)
“1”
Status
Read Array
Read
Status
Read Array
Erase
Setup
“1”
Status
Erase
Cmd.Error
“1”
Status
Erase
(continue)
“0”
Status
Erase Sus
Read Sts
“1”
Status
Erase Sus
Read Array
Program
Setup
Erase Sus
Read Array
Erase
(continue)
Erase Sus
Read Array
Erase
(continue)
Erase Sus Erase Sus
Read Sts Read Array
Erase Sus
Read Array
“1”
Array
Erase Sus
Read Array
Program
Setup
Erase Sus
Read Array
Erase
(continue)
Erase Sus
Read Array
Erase
(continue)
Erase Sus Erase Sus
Read Sts Read Array
Erase Sus
Read
Elect.Sg.
“1”
Electronic
Signature
Erase Sus
Read Array
Program
Setup
Erase Sus
Read Array
Erase
(continue)
Erase Sus
Read Array
Erase
(continue)
Erase Sus Erase Sus
Read Sts Read Array
Erase Sus
Read CFI
“1”
CFI
Erase Sus
Read Array
Program
Setup
Erase Sus
Read Array
Erase
(continue)
Erase Sus
Read Array
Erase
(continue)
Erase Sus Erase Sus
Read Sts Read Array
Erase
(complete)
“1”
Status
Read Array
Program
Setup
Erase
Setup
“1”
Status
Read
Elect.Sg.
“1”
Read CFI
Query
Ers. Setup
Prog/Ers
Suspend
(B0h)
Program
Setup
Read
Status
Read Array Prog.Setup
Erase
Setup
(10/40h)
Lock
(complete)
Lock Command Error
Read Array
Program
Setup
Erase
Setup
Lock Cmd
Error
Lock
(complete)
Read Array
Lock Command Error
Program
Prog. Sus
Read Sts
Program (continue)
Program
Setup
Erase
Setup
Erase Command Error
Read Array
Program
Setup
Program (continue)
Read Array
Erase
(continue)
Erase
Setup
Erase (continue)
Erase
CmdError
Erase
(continue)
Erase Command Error
Read Array
Read
Status
Erase Sus
Read Sts
Erase (continue)
Read Array
Read
Status
Read Array
Read Array
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
55/57
M36W432T, M36W432B
Table 35. Write State Machine Current/Next, sheet 2 of 2
Command Input (and Next State)
Current State
Read Elect.Sg.
(90h)
Read CFI
Query
(98h)
Lock Setup
(60h)
Prot. Prog.
Setup (C0h)
Lock Confirm
(01h)
Lock Down
Confirm (2Fh)
Read Array
Read Elect.Sg. Read CFI Query
Lock Setup
Prot. Prog.
Setup
Read Array
Read Status
Read Elect.Sg. Read CFI Query
Lock Setup
Prot. Prog.
Setup
Read Array
Read Elect.Sg.
Read Elect.Sg. Read CFI Query
Lock Setup
Prot. Prog.
Setup
Read Array
Read CFI Query Read Elect.Sg. Read CFI Query
Lock Setup
Prot. Prog.
Setup
Read Array
Lock Setup
Lock Command Error
Lock (complete)
Lock Cmd Error
Read Elect.Sg. Read CFI Query
Lock Setup
Prot. Prog.
Setup
Lock (complete)
Read Elect.Sg. Read CFI Query
Lock Setup
Prot. Prog.
Setup
Prot. Prog.
Setup
Protection Register Program
Prot. Prog.
(continue)
Protection Register Program (continue)
Prot. Prog.
(complete)
Read Elect.Sg. Read CFI Query
Unlock
Confirm
(D0h)
Lock Setup
Prot. Prog.
Setup
Prog. Setup
Program
Program
(continue)
Program (continue)
Read Array
Read Array
Read Array
Prog. Suspend
Read Status
Prog. Suspend Prog. Suspend
Read Elect.Sg. Read CFI Query
Program Suspend Read Array
Program
(continue)
Prog. Suspend
Read Array
Prog. Suspend Prog. Suspend
Read Elect.Sg. Read CFI Query
Program Suspend Read Array
Program
(continue)
Prog. Suspend
Read Elect.Sg.
Prog. Suspend Prog. Suspend
Read Elect.Sg. Read CFI Query
Program Suspend Read Array
Program
(continue)
Prog. Suspend
Read CFI
Prog. Suspend Prog. Suspend
Read Elect.Sg. Read CFI Query
Program Suspend Read Array
Program
(continue)
Program
(complete)
Read Elect.Sg.
Read CFIQuery
Erase Setup
Erase
Cmd.Error
Lock Setup
Prot. Prog.
Setup
Read Array
Erase
(continue)
Erase Command Error
Read Elect.Sg. Read CFI Query
Lock Setup
Erase (continue)
Prot. Prog.
Setup
Read Array
Erase (continue)
Erase Suspend
Read Ststus
Erase Suspend Erase Suspend
Read Elect.Sg. Read CFI Query
Lock Setup
Erase Suspend Read Array
Erase
(continue)
Erase Suspend
Read Array
Erase Suspend Erase Suspend
Read Elect.Sg. Read CFI Query
Lock Setup
Erase Suspend Read Array
Erase
(continue)
Erase Suspend
Read Elect.Sg.
Erase Suspend Erase Suspend
Read Elect.Sg. Read CFI Query
Lock Setup
Erase Suspend Read Array
Erase
(continue)
Erase Suspend Erase Suspend Erase Suspend
Read CFI Query Read Elect.Sg. Read CFI Query
Lock Setup
Erase Suspend Read Array
Erase
(continue)
Erase
(complete)
Read Elect.Sg. Read CFI Query
Lock Setup
Prot. Prog.
Setup
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
56/57
Read Array
M36W432T, M36W432B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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