STMICROELECTRONICS M58CR064Q

M58CR064C, M58CR064D
M58CR064P, M58CR064Q
64 Mbit (4Mb x 16, Dual Bank, Burst )
1.8V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Package
– VDD = 1.65V to 2V for Program, Erase and
Read
– VDDQ = 1.65V to 3.3V for I/O Buffers
– VPP = 12V for fast Program (optional)
■
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode : 54MHz
FBGA
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 85, 90, 100, 120ns
■
PROGRAMMING TIME
– 10µs by Word typical
TFBGA56 (ZB)
6.5 x 10mm
– Double/Quadruple Word Program option
■
MEMORY BLOCKS
– Dual Bank Memory Array: 16/48 Mbit
– Parameter Blocks (Top or Bottom location)
■
DUAL OPERATIONS
– Program Erase in one Bank while Read in
other
– No delay between Read and Write operations
■
BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58CR064C: 88CAh
– Bottom Device Code, M58CR064D: 88CBh
– Top Device Code, M58CR064P: 8801h
– Bottom Device Code, M58CR064Q: 8802h
– WP for Block Lock-Down
■
SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device number
– One parameter block permanently lockable
■
COMMON FLASH INTERFACE (CFI)
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
June 2003
1/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Factory Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reserved Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-Down Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Dual Operations Allowed In Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 30
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 18. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. Asynchronous Random Access Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Single Synchronous Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 21. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline. . 46
Table 25. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . 46
Figure 18. TFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 47
Figure 19. TFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package). . . . . 48
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Top Boot Block Addresses, M58CR064C, M58CR064P . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29. Bottom Boot Block Addresses, M58CR064D, M58CR064Q . . . . . . . . . . . . . . . . . . . . . . 52
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 21. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 22. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 23. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 61
Figure 24. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 25. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 26. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 65
APPENDIX D. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 36. Command Interface States - Lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 37. Command Interface States - Modify Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 38. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
SUMMARY DESCRIPTION
The M58CR064 is a 64 Mbit (4Mbit x16) non-volatile Flash memory that may be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 1.65V to 2V VDD supply for the circuitry and a 1.65V to 3.3V VDDQ supply for the Input/Output pins. An optional 12V VPP
power supply is provided to speed up customer
programming. In M58CR064C and M58CR064D
the VPP pin can also be used as a control pin to
provide absolute protection against program or
erase. In M58CR064P and M58CR064Q this feature is disabled.
The device features an asymmetrical block architecture. M58CR064 has an array of 135 blocks,
and is divided into two banks, Banks A and B. The
Dual Bank Architecture allows Dual Operations,
while programming or erasing in one bank, Read
operations are possible in the other bank. Only
one bank at a time is allowed to be in Program or
Erase mode. It is possible to perform burst reads
that cross bank boundaries. The bank architecture
is summarized in Table 2, and the memory maps
are shown in Figure 4. The Parameter Blocks are
located at the top of the memory address space for
the M58CR064C and M58CR064P, and at the bottom for the M58CR064D and M58CR064Q.
Each block can be erased separately. Erase can
be suspended, in order to perform program in any
other block, and then resumed. Program can be
suspended to read data in any other block and
then resumed. Each block can be programmed
and erased over 100,000 cycles using the supply
voltage V DD.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the timings necessary for program and erase operations.
6/70
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC standards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In synchronous burst mode,
data is output on each clock cycle at frequencies
of up to 54MHz.
The M58CR064 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any accidental programming or erasure. In M58CR064C and
M58CR064D there is an additional hardware protection against program and erase. When VPP ≤
VPPLK all blocks are protected against program or
erase. All blocks are locked at Power- Up.
The device includes a Protection Register and a
Security Block to increase the protection of a system’s design. The Protection Register is divided
into two segments: a 64 bit segment containing a
unique device number written by ST, and a 128 bit
segment One-Time-Programmable (OTP) by the
user. The user programmable segment can be
permanently protected. The Security Block, parameter block 0, can be permanently protected by
the user. Figure 5, shows the Security Block and
Protection Register Memory Map.
The memory is offered in a TFBGA56, 6.5 x
10mm, 0.75 mm ball pitch package and is supplied
with all the bits erased (set to ’1’).
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 2. Logic Diagram
Table 1. Signal Names
VDD VDDQ VPP
22
16
A0-A21
DQ0-DQ15
W
E
G
RP
WAIT
M58CR064C
M58CR064D
M58CR064P
M58CR064Q
WP
L
K
VSS
A0-A21
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command
Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Power-Down
WP
Write Protect
K
Clock
L
Latch Enable
WAIT
Wait
VDD
Supply Voltage
VDDQ
Supply Voltage for Input/Output
Buffers
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS
Ground
VSSQ
Ground Input/Output Supply
NC
Not Connected Internally
VSSQ
AI90000
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A11
A8
VSS
VDD
VPP
A18
A6
A4
B
A12
A9
A20
K
RP
A17
A5
A3
C
A13
A10
A21
L
W
A19
A7
A2
D
A15
A14
WAIT
A16
DQ12
WP
NC
A1
E
VDDQ
DQ15
DQ6
DQ4
DQ2
DQ1
E
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
G
G
DQ7
VSSQ
DQ5
VDD
DQ3
VDDQ
DQ8
VSSQ
AI90001
Table 2. Bank Architecture
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Bank Size
Parameter Blocks
Main Blocks
Bank A
16 Mbit
8 blocks of 4 KWord
31 blocks of 32 KWord
Bank B
48 Mbit
-
96 blocks of 32 KWord
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 4. Memory Map
Top Boot Block
Address lines A21-A0
000000h
007FFFh
Bottom Boot Block
Address lines A21-A0
000000h
512 Kbit or
32 KWord
000FFFh
64 Kbit or
4 KWord
Total of 8
Parameter
Blocks
(bottom bank)
Total of 96
Main Blocks
(bottom bank)
Bank B
2F8000h
2FFFFFh
300000h
307FFFh
007000h
512 Kbit or
32 KWord
Bank A
512 Kbit or
32 KWord
007FFFh
008000h
00FFFFh
64 Kbit or
4 KWord
512 Kbit or
32 KWord
Total of 31
Main Blocks
(bottom bank)
Total of 31
Main Blocks
(top bank)
3F0000h
Bank A
3F7FFFh
3F8000h
3F8FFFh
0F8000h
512 Kbit or
32 KWord
0FFFFFh
100000h
64 Kbit or
4 KWord
107FFFh
Total of 8
Parameter
Blocks
(top bank)
3FF000h
3FFFFFh
64 Kbit or
4 KWord
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Total of 96
Main Blocks
(top bank)
Bank B
3F8000h
3FFFFFh
512 Kbit or
32 KWord
AI90002
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Bus Write
operation.
Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is
at VILand Reset/Power-Down is at VIH the device
is in active mode. When Chip Enable is at VIH the
memory is deselected, the outputs are high impedance and the power consumption is reduced to the
stand-by level.
Output Enable (G). The Output Enable controls
the outputs during the Bus Read operation of the
memory.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable or Write Enable
whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the LockDown is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (refer to Table 13, Lock Status).
Reset/Power-Down (RP). The
Reset/PowerDown input provides a hardware reset of the memory, and/or Power-Down functions, depending on
the Configuration Register status. When Reset/
Power-Down is at VIL, the memory is in reset
mode: the outputs are high impedance and if the
Power-Down function is enabled the current consumption is reduced to the Reset Supply Current
IDD2. Refer to Table 18, DC Characteristics - Currents for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Register is reset. When Reset/Power-Down is at VIH,
the device is in normal operation. Exiting reset
mode the device enters asynchronous read mode,
but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset/Power-Down pin can be interfaced with
3V logic without any additional circuitry. It can be
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tied to V RPH (refer to Table 19, DC Characteristics).
Latch Enable (L). Latch Enable latches the address bits on its rising edge. The address latch is
transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable
can be kept Low (also at board level) when the
Latch Enable function is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is
don't care during asynchronous read and in write
operations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high impedance when Chip Enable or Output Enable are at
VIH or Reset/Power-Down is at V IL. It can be configured to be active during the wait cycle or one
clock cycle in advance.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a
control input and a power supply pin. In
M58CR064C/D the two functions are selected by
the voltage range applied to the pin. In the
M58CR064P/Q the control feature is disabled.
In M58CR064C/D if VPP is kept in a low voltage
range (0V to VDDQ) V PP is seen as a control input.
In this case a voltage lower than VPPLK gives an
absolute protection against program or erase,
while VPP > VPP1 enables these functions (see Tables 18 and 19, DC Characteristics for the relevant
values). VPP is only sampled at the beginning of a
program or erase; a change in its value after the
operation has started does not have any effect and
program or erase operations continue.
If V PP is in the range of VPPH it acts as a power
supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.
VSS Ground. VSS ground is the reference for the
core supply. It must be connected to the system
ground.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by V DDQ. VSSQ
must be connected to V SS
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Note: Each device in a system should have
VDD, VDDQ and V PP decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors
should be as close as possible to the pack-
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset.
See Table 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at V IL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
Refer to the Read AC Waveform figures and Characteristics tables in the DC and AC Parameters
section for details of when the output becomes valid.
Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at VIL with
Output Enable at VIH. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
age). See Figure 9, AC Measurement Load Circuit. The PCB track widths should be sufficient
to carry the required V PP program and erase
currents.
the Latch Enable should be tied to VIH during the
bus write operation.
See Figures 14 and 15, Write AC Waveforms, and
Tables 22 and 23, Write AC Characteristics, for
details of the timing requirements.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch Enable must be at V IL during address latch operations. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high impedance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by
when Chip Enable and Reset/Power-Down are at
VIH. The power consumption is reduced to the
stand-by level and the outputs are set to high impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
VIH during a program or erase operation, the device enters Standby mode when finished.
Reset. During Reset mode the memory is deselected and the outputs are high impedance. The
memory is in Reset mode when Reset/PowerDown is at VIL. The power consumption is reduced
to the Standby level, independently from the Chip
Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a Program or Erase,
this operation is aborted and the memory content
is no longer valid.
Table 3. Bus Operations
Operation
E
G
W
L
RP
Bus Read
VIL
VIL
VIH
VIL(2)
VIH
Bus Write
VIL
VIH
VIL
VIL(2)
VIH
Address Latch
VIL
X
VIH
VIL
VIH
Output Disable
VIL
VIH
VIH
X
VIH
Hi-Z
Hi-Z
Standby
VIH
X
X
X
VIH
Hi-Z
Hi-Z
X
X
X
X
VIL
Hi-Z
Hi-Z
Reset
WAIT
DQ15-DQ0
Data Output
Hi-Z
Data Input
Data Output or Hi-Z (3)
Note: 1. X = Don’t care.
2. L can be tied to VIH if the valid address has been previously latched.
3. Depends on G.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution
of the Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
The Command Interface is reset to read mode
when power is first applied, when exiting from Reset or whenever V DD is lower than VLKO . Command sequences must be followed exactly. Any
invalid combination of commands will reset the device to read mode.
Refer to Table 4, Command Codes and Appendix
D, Tables 36 and 37, Command Interface States Modify and Lock Tables, for a summary of the
Command Interface.
The Command Interface is split into two types of
commands: Standard commands and Factory
Program commands. The following sections explain in detail how to perform each command.
12/70
Table 4. Command Codes
Hex Code
Command
01h
Block Lock Confirm
03h
Set Configuration Register Confirm
10h
Alternative Program Setup
20h
Block Erase Setup
2Fh
Block Lock-Down Confirm
30h
Double Word Program Setup
40h
Program Setup
50h
Clear Status Register
55h
Quadruple Word Program Setup
60h
Block Lock Setup, Block Unlock Setup,
Block Lock Down Setup and Set
Configuration Register Setup
70h
Read Status Register
80h
Bank Erase Setup
90h
Read Electronic Signature
98h
Read CFI Query
B0h
Program/Erase Suspend
C0h
Protection Register Program
D0h
Program/Erase Resume, Block Erase
Confirm, Bank Erase Confirm, Block
Unlock Confirm
FFh
Read Array
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
COMMAND INTERFACE - STANDARD COMMANDS
The following commands are the basic commands
Read CFI Query Command
used to read, write to and configure the device.
The Read CFI Query command is used to read
Refer to Table 5, Standard Commands, in condata from the Common Flash Interface (CFI)
junction with the following text descriptions.
memory area located in the bottom bank. The
Read Array Command
Read CFI Query Command consists of one Bus
Write cycle, to an address within the bottom bank.
The Read Array command returns the addressed
Once the command is issued subsequent Bus
bank to Read Array mode. One Bus Write cycle is
Read operations in the same bank read from the
required to issue the Read Array command and reCommon Flash Interface.
turn the addressed bank to Read Array mode.
Subsequent read operations will read the adIf a Read CFI Query command is issued in a bank
dressed location and output the data. A Read Arthat is executing a Program or Erase operation the
ray command can be issued in one bank while
bank will go into Read Status Register mode, subprogramming or erasing in the other bank. Howevsequent Bus Read cycles will output the Status
er if a Read Array command is issued to a bank
Register and the Program/Erase controller will
currently executing a Program or Erase operation
continue to Program or Erase in the background.
the command will be ignored.
When the Program or Erase operation has finished the device will enter Read CFI Query mode.
Read Status Register Command
This mode supports asynchronous or single synA Bank’s Status Register indicates when a Prochronous reads only, it does not support page
gram or Erase operation is complete and the sucmode or synchronous burst reads.
cess or failure of operation itself. Issue a Read
Status Register command to read the Status RegThe status of the other banks is not affected by the
ister content of the addressed Bank. The Read
command (see Table 11). After issuing a Read
Status Register command can be issued at any
CFI Query command, a Read Array command
time, even during Program or Erase operations.
should be issued to the addressed bank to return
the bank to read mode.
The following Bus Read operations output the content of the Status Register of the addressed bank.
See Appendix B, Common Flash Interface, Tables
The Status Register is latched on the falling edge
30, 31, 32, 33, 34 and 35 for details on the inforof E or G signals, and can be read until E or G remation contained in the Common Flash Interface
turns to VIH. Either E or G must be toggled to upmemory area.
date the latched data. See Table 8 for the
Clear Status Register Command
description of the Status Register Bits. This mode
The Clear Status Register command can be used
supports asynchronous or single synchronous
to reset (set to ‘0’) error bits SR1, SR3, SR4 and
reads only.
SR5 in the Status Register of the addressed bank.
Read Electronic Signature Command
One bus write cycle is required to issue the Clear
The Read Electronic Signature command reads
Status Register command. After the Clear Status
the Manufacturer and Device Codes, the Block
Register command the bank returns to Read Array
Locking Status, the Protection Register, and the
mode.
Configuration Register.
The error bits in the Status Register do not autoThe Read Electronic Signature command consists
matically return to ‘0’ when a new command is isof one write cycle to an address within the bottom
sued. The error bits in the Status Register should
bank. A subsequent read operation in the address
be cleared before attempting a new Program or
of the bottom bank will output the Manufacturer
Erase command.
Code, the Device Code, the protection Status of
Block Erase Command
Blocks of the bottom bank, the Die Revision Code,
The Block Erase command can be used to erase
the Protection Register, or the Read Configuration
a block. It sets all the bits within the selected block
Register (see Table 6).
to ’1’. All previous data in the block is lost. If the
If the first write cycle of Read Electronic Signature
block is protected then the Erase operation will
command is issued to an address within the top
abort, the data in the block will not be changed and
bank, a subsequent read operation in an address
the Status Register will output the error. The Block
of the top bank will output the protection Status of
Erase command can be issued at any moment, reblocks of the top bank. The status of the other
gardless of whether the block has been probank is not affected by the command (see Table
grammed or not.
11). This mode supports asynchronous or single
Two Bus Write cycles are required to issue the
synchronous reads only, it does not support page
command.
mode or synchronous burst reads.
■ The first bus cycle sets up the Erase command.
13/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits SR4 and SR5 are set
and the command aborts. Erase aborts if Reset
turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the
block must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued.
During Erase operations the bank containing the
block being erased will only accept the Read Status Register and the Program/Erase Suspend
command, all other commands will be ignored.
Refer to Dual Operations section for detailed information about simultaneous operations allowed in
banks not being erased. Typical Erase times are
given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles.
See Appendix C, Figure 24, Block Erase Flowchart and Pseudo Code, for a suggested flowchart
for using the Block Erase command.
Program Command
The memory array can be programmed word-byword. Only one Word in one bank can be programmed at any one time. Two bus write cycles
are required to issue the Program Command.
■ The first bus cycle sets up the Program
command.
■ The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
After programming has started, read operations in
the bank being programmed output the Status
Register content.
During Program operations the bank being programmed will only accept the Read Status Register and the Program/Erase Suspend command.
Refer to Dual Operations section for detailed information about simultaneous operations allowed in
banks not being programmed. Typical Program
times are given in Table 14, Program, Erase
Times and Program/Erase Endurance Cycles.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the memory location must be
reprogrammed.
See Appendix C, Figure 20, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
■
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Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Block Erase operation. A
Bank Erase operation cannot be suspended.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6
and/ or SR2 of the Status Register will be set to ‘1’.
The command must be addressed to the bank
containing the Program or Erase operation.
During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume,
Read Array (cannot read the suspended block),
Read Status Register, Read Electronic Signature
and Read CFI Query commands. Additionally, if
the suspend operation was Erase then the Clear
status Register, Program, Block Lock, Block LockDown or Protection Program commands will also
be accepted. The block being erased may be protected by issuing the Block Lock, Block LockDown or Protection Register Program commands.
Only the blocks not being erased may be read or
programmed correctly. When the Program/Erase
Resume command is issued the operation will
complete. Refer to the Dual Operations section for
detailed information about simultaneous operations allowed during Program/Erase Suspend.
During a Program/Erase Suspend, the device can
be placed in standby mode by taking Chip Enable
to VIH. Program/Erase is aborted if Reset turns to
VIL.
See Appendix C, Figure 23, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
25, Erase Suspend & Resume Flowchart and
Pseudo Code for flowcharts for using the Program/
Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend command has paused
it. One Bus Write cycle is required to issue the
command. The command must be written to the
bank containing the Program or Erase Suspend.
The Program/Erase Resume command changes
the read mode of the target bank to Read Status
Register mode.
If a Program command is issued during a Block
Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend
operations. For example: suspend an erase operation, start a programming operation, suspend the
programming operation then read the array. See
Appendix C, Figure 23, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 25,
Erase Suspend & Resume Flowchart and Pseudo
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Code for flowcharts for using the Program/Erase
Resume command.
Protection Register Program Command
The Protection Register Program command is
used to Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
■ The first bus cycle sets up the Protection
Register Program command.
■ The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register. Bit 1 of the Protection Lock Register also protects bit 2 of the Protection Lock Register. Programming bit 2 of the
Protection Lock Register will result in a permanent
protection of Parameter Block #0 (see Figure 5,
Security Block and Protection Register Memory
Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection
Register and/or the Security Block is not reversible.
The Protection Register Program cannot be suspended. See Appendix C, Figure 27, Protection
Register Program Flowchart and Pseudo Code,
for a flowchart for using the Protection Register
Program command.
Set Configuration Register Command.
The Set Configuration Register command is used
to write a new value to the Configuration Control
Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode
and the valid Clock edge configuration.
Two Bus Write cycles are required to issue the Set
Configuration Register command.
■ The first cycle writes the setup command and
the address corresponding to the Configuration
Register content.
■ The second cycle writes the Configuration
Register data and the confirm command.
Once the command is issued the memory returns
to Read mode.
The value for the Configuration Register is always
presented on A0-A15. CR0 is on A0, CR1 on A1,
etc.; the other address bits are ignored.
Block Lock Command
The Block Lock command is used to lock a block
and prevent Program or Erase operations from
changing the data in it. All blocks are locked at
power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 13 shows the Lock Status after issuing a
Block Lock command.
The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/
power-up. They are cleared by a Block Unlock
command. Refer to the section, Block Locking, for
a detailed explanation. See Appendix C, Figure
26, Locking Operations Flowchart and Pseudo
Code, for a flowchart for using the Lock command.
Block Unlock Command
The Block Unlock command is used to unlock a
block, allowing the block to be programmed or
erased. Two Bus Write cycles are required to issue the Block Unlock command.
■ The first bus cycle sets up the Block Unlock
command.
■ The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table 13 shows the protection status after issuing
a Block Unlock command. Refer to the section,
Block Locking, for a detailed explanation and Appendix C, Figure 26, Locking Operations Flowchart and Pseudo Code, for a flowchart for using
the Unlock command.
Block Lock-Down Command
A locked or unlocked block can be locked-down by
issuing the Block Lock-Down command. A lockeddown block cannot be programmed or erased, or
have its protection status changed when WP is
low, VIL. When WP is high, VIH, the Lock-Down
function is disabled and the locked blocks can be
individually unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latches the block
address.
15/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table. 13 shows the Lock Status af-
ter issuing a Block Lock-Down command. Refer to
the section, Block Locking, for a detailed explanation and Appendix C, Figure 26, Locking Operations Flowchart and Pseudo Code, for a flowchart
for using the Lock-Down command.
Commands
Cycles
Table 5. Standard Commands
Bus Operations
1st Cycle
2nd Cycle
Op.
Add
Data
Op.
Add
Data
Read Array
1+
Write
BKA
FFh
Read
WA
RD
Read Status Register
1+
Write
BKA
70h
Read
BKA(2)
SRD
Read Electronic Signature
1+
Write
BBKA or
BKA(3)
90h
Read
BBKA or
BKA(2,3)
ESD(3)
Read CFI Query
1+
Write
BBKA
98h
Read
BBKA (2)
QD
Clear Status Register
1
Write
BKA
50h
Block Erase
2
Write
BKA
20h
Write
BA
D0h
Program
2
Write
BKA
40h or 10h
Write
WA
PD
Program/Erase Suspend
1
Write
BKA
B0h
Program/Erase Resume
1
Write
BKA
D0h
Protection Register Program
2
Write
PRA
C0h
Write
PRA
PRD
Set Configuration Register
2
Write
CRD
60h
Write
CRD
03h
Block Lock
2
Write
BKA
60h
Write
BA
01h
Block Unlock
2
Write
BKA
60h
Write
BA
D0h
Block Lock-Down
2
Write
BKA
60h
Write
BA
2Fh
Note: 1. X = Don’t Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data,
QD=Query Data, BA=Block Address, BKA= Bank Address, BBKA= Bottom Bank Address, PD=Program Data, PRA=Protection
Register Address, PRD=Protection Register Data, CRD=Configuration Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6.
3. When addressed to a block in the Top Bank, reads Block Protection data only.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 6. Electronic Signature Codes
Code
Manufacturer Code
Address (h)
Data (h)
Bottom Bank Address + 00
0020
Top (M58CR064C)
88CA
Bottom (M58CR064D)
88CB
Device Code
Bottom Bank Address + 01
Top (M58CR064P)
8801
Bottom (M58CR064Q)
8802
Lock
0001
Unlocked
0000
Block Protection
Block Address + 02
Locked and Locked-Down
0003
Unlocked and Locked-Down
0002
Reserved
Bottom Bank Address + 03
Reserved
Configuration Register
Bottom Bank Address + 05
CR
Protection Register Lock
ST Factory Default
xx06
Security Block Permanently Locked
xx02
Bottom Bank Address + 80
OTP Area Permanently Locked
Security Block and OTP Area Permanently
Locked
xx04
xx00
Bottom Bank Address + 81
Bottom Bank Address + 84
Unique Device
Number
Bottom Bank Address + 85
Bottom Bank Address + 8C
OTP Area
Protection Register
Note: CR=Configuration Register.
Figure 5. Security Block and Protection Register Memory Map
PROTECTION REGISTER
8Ch
SECURITY BLOCK
User Programmable OTP
85h
84h
Parameter Block # 0
Unique device number
81h
80h
Protection Register Lock
2
1
0
AI06181
17/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
COMMAND INTERFACE - FACTORY PROGRAM COMMANDS
The Factory Program commands are used to
Double Word Program Command
speed up programming. They require V PP to be at
The Double Word Program command improves
VPPH except for the Bank Erase command which
the programming throughput by writing a page of
also operates at VPP = VDD. Refer to Table 7, Factwo adjacent words in parallel. The two words
tory Program Commands, in conjunction with the
must differ only for the address A0.
following text descriptions.
Programming should not be attempted when VPP
Bank Erase Command
is not at VPPH. The command can be executed if
VPP is below VPPH but the result is not guaranteed.
The Bank Erase command can be used to erase a
bank. It sets all the bits within the selected bank to
Three bus write cycles are necessary to issue the
’1’. All previous data in the bank is lost. The Bank
Double Word Program command.
Erase command will ignore any protected blocks
■ The first bus cycle sets up the Double Word
within the bank. If all blocks in the bank are proProgram Command.
tected then the Bank Erase operation will abort
■ The second bus cycle latches the Address and
and the data in the bank will not be changed. The
the Data of the first word to be written.
Status Register will not output any error.
■ The third bus cycle latches the Address and the
Bank Erase operations can be performed at both
Data of the second word to be written and starts
VPP = VPPH and V PP = VDD.
the Program/Erase Controller.
Two Bus Write cycles are required to issue the
Read
operations in the bank being programmed
command.
output the Status Register content after the pro■ The first bus cycle sets up the Bank Erase
gramming has started.
command.
During Double Word Program operations the bank
■ The second latches the bank address in the
being programmed will only accept the Read Stainternal state machine and starts the Program/
tus Register command, all other commands will be
Erase Controller.
ignored. Dual operations are not supported during
If the second bus cycle is not Write Bank Erase
Double Word Program operations. It is not recomConfirm (D0h), Status Register bits SR4 and SR5
mended to suspend the Double Word Program
are set and the command aborts. Erase aborts if
command. Typical Program times are given in TaReset turns to VIL. As data integrity cannot be
ble 14, Program, Erase Times and Program/Erase
guaranteed when the Erase operation is aborted,
Endurance Cycles.
the bank must be erased again.
Programming aborts if Reset goes to VIL. As data
Once the command is issued the device outputs
integrity cannot be guaranteed when the program
the Status Register data when any address within
operation is aborted, the memory locations must
the bank is read. At the end of the operation the
be reprogrammed.
bank will remain in Read Status Register mode unSee Appendix C, Figure 21, Double Word Protil a Read Array, Read CFI Query or Read Elecgram Flowchart and Pseudo Code, for the flowtronic Signature command is issued.
chart for using the Double Word Program
During Bank Erase operations the bank being
command.
erased will only accept the Read Status Register
Quadruple Word Program Command
command, all other commands will be ignored. A
The Quadruple Word Program command imBank Erase operation cannot be suspended.
proves the programming throughput by writing a
For optimum performance, Bank Erase compage of four adjacent words in parallel. The four
mands should be limited to a maximum of 100 Prowords must differ only for the addresses A0 and
gram/Erase cycles per Block. After 100 Program/
A1.
Erase cycles the internal algorithm will still operate
Programming should not be attempted when VPP
properly but some degradation in performance
is not at VPPH. The command can be executed if
may occur.
VPP is below VPPH but the result is not guaranteed.
Dual operations are not supported during Bank
Five
bus write cycles are necessary to issue the
Erase operations and the command cannot be
Quadruple Word Program command.
suspended.
■ The first bus cycle sets up the Double Word
Typical Erase times are given in Table 14, ProProgram Command.
gram, Erase Times and Program/Erase Endurance Cycles.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
18/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
The third bus cycle latches the Address and the
Data of the second word to be written.
■ The fourth bus cycle latches the Address and
the Data of the third word to be written.
■ The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations to the bank being programmed
output the Status Register content after the programming has started.
Programming aborts if Reset goes to VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the memory locations must
be reprogrammed.
■
During Quadruple Word Program operations the
bank being programmed will only accept the Read
Status Register command, all other commands
will be ignored.
Dual operations are not supported during Quadruple Word Program operations. It is not recommended to suspend the Quadruple Word Program
command. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase
Endurance Cycles.
See Appendix C, Figure 22, Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program
command.
Command
Phase
Cycles
Table 7. Factory Program Commands
Bus Write Operations
1st
2nd
3rd
Add
Data
Add
Data
4th
Add
Data
Bank Erase
2
BKA
80h
BKA
D0h
Double Word Program(2)
3
BKA
30h
WA1
PD1
WA2
PD2
Quadruple Word
Program(3)
5
BKA
55h
WA1
PD1
WA2
PD2
5th
Add
Data
Add
Data
WA3
PD3
WA4
PD4
Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, WA1 is the Start Address.
2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
3. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
19/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
STATUS REGISTER
The M58CR064 has two Status Registers, one for
each bank. The Status Registers provide information on the current or previous Program or Erase
operations executed in each bank. Issue a Read
Status Register command to read the contents of
the Status Register, refer to Read Status Register
Command section for more details. To output the
contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
or Output Enable returns to VIH. The Status Register can only be read using single asynchronous
or single synchronous reads. Bus Read operations from any address within the bank, always
read the Status Register during Program and
Erase operations.
The various bits convey information about the status and any errors of the operation. Bits SR7, SR6
and SR2 give information on the status of the bank
and are set and reset by the device. Bits SR5,
SR4, SR3 and SR1 give information on errors,
they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status
Register should be reset before issuing another
command.
The bits in the Status Register are summarized in
Table 8, Status Register Bits. Refer to Table 8 in
conjunction with the following text descriptions.
Program/Erase Controller Status Bit (SR7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive in the addressed bank. When the Program/Erase Controller Status bit is Low (set to ‘0’),
the Program/Erase Controller is active; when the
bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a
new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller pauses the bit is High.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Register should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Lock Status bits should be tested
for errors.
Erase Suspend Status Bit (SR6). The
Erase
Suspend Status bit indicates that an Erase operation has been suspended or is going to be sus-
20/70
pended in the addressed block. When the Erase
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
SR7 is set within 30µs of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than
entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.
Erase Status Bit (SR5). The Erase Status bit
can be used to identify if the memory has failed to
verify that the block or bank has erased correctly.
When the Erase Status bit is High (set to ‘1’), the
Program/Erase Controller has applied the maximum number of pulses to the block or bank and
still failed to verify that it has erased correctly. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a
hardware reset. If set High it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status Bit (SR4). The Program Status
bit is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum
number of pulses to the byte and still failed to verify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive).
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset before a new command is issued, otherwise the new
command will appear to fail.
VPP Status Bit (SR3). The V PP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can occur if V PP becomes invalid during an operation.
When the VPP Status bit is Low (set to ‘0’), the voltage on the V PP pin was sampled at a valid voltage;
when the V PP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the V PP Lockout
Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed.
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Once set High, the V PP Status bit can only be reset
Low by a Clear Status Register command or a
hardware reset. If set High it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program
operation has been suspended in the addressed
block. When the Program Suspend Status bit is
High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting
for a Program/Erase Resume command. The Program Suspend Status should only be considered
valid when the Program/Erase Controller Status
bit is High (Program/Erase Controller inactive).
SR2 is set within 5µs of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than
entering the Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.
Block Protection Status Bit (SR1). The Block
Protection Status bit can be used to identify if a
Program or Block Erase operation has tried to
modify the contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been attempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Reserved Bit (SR0). SR0 is reserved. Its value
must be masked.
Table 8. Status Register Bits
Bit
SR7
SR6
SR5
SR4
SR3
SR2
SR1
Name
P/E.C. Status
Erase Suspend Status
Erase Status
Program Status
VPP Status
Type
Logic Level
Definition
’1’
Ready
’0’
Busy
’1’
Erase Suspended
’0’
Erase In progress or Completed
’1’
Erase Error
’0’
Erase Success
’1’
Program Error
’0’
Program Success
’1’
VPP Invalid, Abort
’0’
VPP OK
’1’
Program Suspended
’0’
Program In Progress or Completed
’1’
Program/Erase on protected Block, Abort
’0’
No operation to protected blocks
Status
Status
Error
Error
Error
Program Suspend Status Status
Block Protection Status
SR0
Error
Reserved
Note: Logic level ’1’ is High, ’0’ is Low.
21/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
CONFIGURATION REGISTER
The Configuration Register is used to configure
the type of bus access that the memory will perform. Refer to Read Modes section for details on
read operations.
The Configuration Register is set through the
Command Interface. After a Reset or Power-Up
the device is configured for asynchronous page
read (CR15 = 1). The Configuration Register bits
are described in Table 9. They specify the selection of the burst length, burst type, burst X latency
and the Read operation. Refer to Figures 6 and 7
for examples of synchronous burst configurations.
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read
operations. When the Read Select bit is set to ’1’,
read operations are asynchronous; when the
Read Select bit is set to ’0’, read operations are
synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous access.
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available. For correct operation the
X-Latency bits can only assume the values in Table 9, Configuration Register.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system parameters. Two conditions must be satisfied:
1. Depending on whether tAVK_CPU or t DELAY is
supplied either one of the following two
equations must be satisfied:
(n + 1) t K ≥ tACC - tAVK_CPU + tQVK_CPU
(n + 2) tK ≥ tACC + tDELAY + tQVK_CPU
2. and also
tK > tKQV + tQVK_CPU
where
n is the chosen X-Latency configuration code
tK is the clock period
tAVK_CPU is clock to address valid, L Low, or E
Low, whichever occurs last
tDELAY is address valid, L Low, or E Low to clock,
whichever occurs last
tQVK_CPU is the data setup time required by the
system CPU,
tKQV is the clock to data valid time
tACC is the random access time of the device.
22/70
Refer to Figure 6, X-Latency and Data Output
Configuration Example.
Power-Down Bit (CR10)
The Power-Down bit is used to enable or disable
the power-down function.
When the Power-Down bit is set to ‘0’ the powerdown function is disabled. If the Reset/PowerDown, RP, pin goes Low, VIL, the device is reset
and the supply current, IDD, is reduced to the
standby value, IDD3.
When the Power-Down bit is set to ‘1’ the powerdown function is enabled. If the Reset/PowerDown, RP, pin goes Low, VIL, the device goes into
the power-down state and the supply current, IDD,
is reduced to the power-down value, IDD2.
The recovery time after a Reset/Power-Down, RP,
pulse is significantly longer when power-down is
enabled (see Table 24).
After a reset the Power-Down Bit is set to ‘0’.
Wait Configuration Bit (CR8)
In burst mode the Wait bit controls the timing of the
Wait output pin, WAIT. When the Wait bit is ’0’ the
Wait output pin is asserted during the wait state.
When the Wait bit is ’1’ (default) the Wait output
pin is asserted one clock cycle before the wait
state.
WAIT is asserted during a continuous burst and
also during a 4 or 8 burst length if no-wrap configuration is selected. WAIT is not asserted during
asynchronous reads, single synchronous reads or
during latency in synchronous reads.
Burst Type Bit (CR7)
The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory
outputs from interleaved addresses; when the
Burst Type bit is ’1’ (default) the memory outputs
from sequential addresses. See Tables 10, Burst
Type Definition, for the sequence of addresses
output from a given starting address in each mode.
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid
Clock Edge bit is ’0’ the falling edge of the Clock is
the active edge; when the Valid Clock Edge bit is
’1’ the rising edge of the Clock is active.
Wrap Burst Bit (CR3)
The burst reads can be confined inside the 4 or 8
Word boundary (wrap) or overcome the boundary
(no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit
is set to ‘0’ the burst read wraps; when it is set to
‘1’ the burst read does not wrap.
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Burst length Bits (CR2-CR0)
The Burst Length bits set the number of Words to
be output during a Synchronous Burst Read operation as result of a single address latch cycle.
They can be set for 4 words, 8 words or continuous burst, where all the words are read sequentially.
In continuous burst mode the burst sequence can
cross bank boundaries.
In continuous burst mode or in 4, 8 words no-wrap,
depending on the starting address, the device asserts the WAIT output to indicate that a delay is
necessary before the data is output.
If the starting address is aligned to a 4 word
boundary no wait states are needed and the WAIT
output is not asserted.
If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 64 word boundary, to
indicate that the device needs an internal delay to
read the successive words in the array. WAIT will
be asserted only once during a continuous burst
access. See also Table 10, Burst Type Definition.
CR14, CR9, CR5 and CR4 are reserved for future
use.
Table 9. Configuration Register
Bit
CR15
Description
Value
0
Synchronous Read
1
Asynchronous Read (Default at power-on)
Read Select
CR14
CR13-CR11
Description
Reserved
010
2 clock latency
011
3 clock latency
100
4 clock latency
101
5 clock latency
111
Reserved
X-Latency
Other configurations reserved
CR10
Power-Down
0
Power-Down disabled
1
Power-Down enabled
CR9
CR8
CR7
CR6
Reserved
0
WAIT is active during wait state
1
WAIT is active one data cycle before wait state (default)
0
Interleaved
1
Sequential (default)
0
Falling Clock edge
1
Rising Clock edge
Wait Configuration
Burst Type
Valid Clock Edge
CR5-CR4
CR3
CR2-CR0
Reserved
0
Wrap
1
No Wrap
001
4 words
010
8 words
111
Continuous (CR7 must be set to ‘1’)
Wrap Burst
Burst Length
23/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Mode
Table 10. Burst Type Definition
Start
Address
4 Words
8 Words
Continuous Burst
Sequential
Interleaved
Sequential
Interleaved
0
0-1-2-3
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6...
1
1-2-3-0
1-0-3-2
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
1-2-3-4-5-6-7...
2
2-3-0-1
2-3-0-1
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
2-3-4-5-6-7-8...
3
3-0-1-2
3-2-1-0
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
3-4-5-6-7-8-9...
7-4-5-6
7-6-5-4
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
7-8-9-10-11-12-13...
Wrap
...
7
...
60
60-61-62-63-64-65-66...
61
61-62-63-WAIT-64-65-66...
62
62-63-WAIT-WAIT-64-65-66...
63
63-WAIT-WAIT-WAIT-64-6566...
Sequential
Interleaved
Sequential
0
0-1-2-3
0-1-2-3-4-5-6-7
1
1-2-3-4
1-2-3-4-5-6-7-8
2
2-3-4-5
2-3-4-5-6-7-8-9...
3
3-4-5-6
3-4-5-6-7-8-9-10
7-8-9-10
7-8-9-10-11-12-13-14
60
60-61-62-63
60-61-62-63-64-65-6667
61
61-62-63-WAIT-64
61-62-63-WAIT-64-6566-67-68
62
62-63-WAIT-WAIT64-65
62-63-WAIT-WAIT-6465-66-67-68-69
63
63-WAIT-WAITWAIT-64-65-66
63-WAIT-WAIT-WAIT64-65-66-67-68-69-70
Interleaved
No-wrap
...
24/70
7
...
Same as for Wrap
(Wrap /No Wrap
has no effect on
Continuous Burst )
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 6. X-Latency and Data Output Configuration Example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
A21-A0
tDELAY
VALID ADDRESS
tAVK_CPU
tQVK_CPU
tK
tKQV
tACC
tQVK_CPU
DQ15-DQ0
VALID DATA VALID DATA
Note. Settings shown: X-latency = 4, Data Output held for one clock cycle
AI90005
Figure 7. Wait Configuration Example
E
K
L
A21-A0
DQ15-DQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT
CR8 = '0'
WAIT
CR8 = '1'
AI90006b
25/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
READ MODES
Read operations can be performed in two different
ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for
the data output, the read operation is Asynchronous; if the data output is synchronized with clock,
the read operation is Synchronous.
The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks
supports both asynchronous and synchronous
read operations. The Dual Bank architecture allows read operations in one bank, while write operations are being executed in the other (see
Tables 11 and 12).
Asynchronous Read Mode
In Asynchronous Read operations the clock signal
is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash
Interface or Electronic Signature depending on the
command issued. CR15 in the Configuration Register must be set to ‘1’ for Asynchronous operations.
In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The
Page has a size of 4 Words and is addressed by
A0 and A1 address inputs. The address inputs A0
and A1 are not gated by Latch Enable in Asynchronous Read mode.
The first read operation within the Page has a
longer access time (Tacc, Random access time),
subsequent reads within the same Page have
much shorter access times. If the Page changes
then the normal, longer timings apply again.
Asynchronous Read operations can be performed
in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only
Asynchronous Page Read takes full advantage of
the internal page storage so different timings are
applied.
See Table 20, Asynchronous Read AC Characteristics, Figure 10, Asynchronous Random Access
Read AC Waveform and Figure 11, Asynchronous
Page Read AC Waveform for details.
Synchronous Burst Read Mode
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank
boundaries.
Synchronous Burst Read mode can only be used
to read the memory array. For other read operations, such as Read Status Register, Read CFI
and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access
Read must be used.
26/70
In Synchronous Burst Read mode the flow of the
data output depends on parameters that are configured in the Configuration Register.
A burst sequence is started at the first clock edge
(rising or falling depending on Valid Clock Edge bit
CR6 in the Configuration Register) after the falling
edge of Latch Enable or Chip Enable, whichever
occurs last. Addresses are internally incremented
and after a delay of 2 to 5 clock cycles (X latency
bits CR13-CR11) the corresponding data are output on each clock cycle.
The number of Words to be output during a Synchronous Burst Read operation can be configured
as 4 or 8 Words or Continuous (Burst Length bits
CR2-CR0). The data can be configured to remain
valid for one or two clock cycles (Data Output Configuration bit CR9).
The order of the data output can be modified
through the Burst Type and the Wrap Burst bits in
the Configuration Register. The burst sequence
may be configured to be sequential or interleaved
(CR7). The burst reads can be confined inside the
4 or 8 Word boundary (Wrap) or overcome the
boundary (No Wrap). If the starting address is
aligned to the Burst Length (4 or 8 Words), the
wrapped configuration has no impact on the output
sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences.
A WAIT signal may be asserted to indicate to the
system that an output delay will occur. This delay
will depend on the starting address of the burst sequence; the worst case delay will occur when the
sequence is crossing a 64 word boundary and the
starting address was at the end of a four word
boundary.
WAIT is asserted during the Wait state and at the
end of 4- and 8-Word Burst. It is deasserted during
the X latency and when output data are valid. In
Continuous Burst Read mode a Wait state will occur when crossing the first 64 Word boundary. If
the burst starting address is aligned to a 4 Word
Page, the Wait state will not occur.
The WAIT signal is active Low. The WAIT signal is
meaningful only in Synchronous Burst Read
mode, in other modes, WAIT is not asserted (except for Read Array mode).
See Table 21, Synchronous Read AC Characteristics and Figure 12, Synchronous Burst Read AC
Waveform for details.
Single Synchronous Read Mode
Single Synchronous Read operations are similar
to Synchronous Burst Read operations except that
only the first data output after the X latency is valid.
Other Configuration Register parameters have no
effect on Single Synchronous Read operations.
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Synchronous Single Reads are used to read the
Electronic Signature, Status Register, CFI, Block
Protection Status, Configuration Register Status
or Protection Register. When the addressed bank
is in Read CFI, Read Status Register or Read
Electronic Signature mode, the WAIT signal is always deasserted.
See Table 21, Synchronous Read AC Characteristics and Figure 13, Single Synchronous Read AC
Waveform for details.
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Dual Operations feature simplifies the softthen a Program command can be issued to anothware management of the device and allows code
er block, so the device can have one block in
to be executed from one bank while the other bank
Erase Suspend mode, one programming and the
is being programmed or erased.
other bank in Read mode. Bus Read operations
are allowed in the other bank between setup and
The Dual operations feature means that while proconfirm cycles of program or erase operations.
gramming or erasing in one bank, Read operaThe combination of these features means that
tions are possible in the other bank with zero
read operations are possible at any moment.
latency (only one bank at a time is allowed to be in
Program or Erase mode). If a Read operation is reTables 11 and 12 show the dual operations possiquired in a bank which is programming or erasing,
ble in the other bank and in the same bank. For a
the Program or Erase operation can be suspendcomplete list of possible commands refer to Aped. Also if the suspended operation was Erase
pendix D, Command Interface State Tables.
Table 11. Dual Operations Allowed In Other Bank
Commands allowed in other bank
Read
Array
Read
Status
Register
Read
CFI
Query
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
Yes
Yes
Yes
Yes
–
–
–
–
Erasing
Yes
Yes
Yes
Yes
–
–
–
–
Program Suspended
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase Suspended
Yes
Yes
Yes
Yes
Yes
–
–
Yes
Block
Erase
Program/
Erase
Suspend
Program/
Erase
Resume
Status of bank
Read
Electronic Program
Signature
Block
Erase
Program/ Program/
Erase
Erase
Suspend Resume
Table 12. Dual Operations Allowed In Same Bank
Commands allowed in same bank
Status of bank
Idle
Read
Array
Read
Read
Read
Status
Electronic Program
CFI Query
Register
Signature
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
–
Yes
–
–
–
–
Yes
–
Erasing
–
Yes
–
–
–
–
Yes
–
Program Suspended
Yes(1)
Yes
Yes
Yes
–
–
–
Yes
Erase Suspended
Yes(1)
Yes
Yes
Yes
Yes(1)
–
–
Yes
Note: 1. Not allowed in the Block or Word that is being erased or programmed.
27/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
BLOCK LOCKING
The M58CR064 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has three levels of protection.
■ Lock/Unlock - this first level allows softwareonly control of block locking.
■
■
Lock-Down - this second level requires
hardware interaction before locking can be
changed.
VPP ≤ VPPLK - the third level offers a complete
hardware protection against program and erase
on all blocks (M58CR064C/D only).
The first two levels (Lock/Unlock and Lock-Down)
are available in M58CR064C/D and M58CR064P/
Q. The third level (VPP ≤ VPPLK) is only available
for the M58CR064C/D versions, in the
M58CR064P/Q this feature has been disabled.
For all devices the protection status of each block
can be set to Locked, Unlocked, and Lock-Down.
Table 13, defines all of the possible protection
states (WP, DQ1, DQ0), and Appendix C, Figure
26, shows a flowchart for the locking operations.
Reading a Block’s Lock Status
The lock status of every block can be read in the
Read Electronic Signature mode of the device. To
enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6,
will output the protection status of that block. The
lock status is represented by DQ0 and DQ1. DQ0
indicates the Block Lock/Unlock status and is set
by the Lock command and cleared by the Unlock
command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked State
The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase operations attempted on a locked block will return an
error in the Status Register. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
Unlocked State
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
28/70
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be unlocked by issuing the Unlock command.
Lock-Down State
Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status cannot be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the
device is reset or powered-down.
The Lock-Down function is dependent on the WP
input pin. When WP=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When
WP=1 (V IH) the Lock-Down function is disabled
(1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WP
remains high. When WP is low , blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP was high. Device reset or power-down
resets all blocks , including those in Lock-Down, to
the Locked state.
Locking Operations During Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After completing any desired lock, read, or program operations,
resume the erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operations cannot be performed during a
program suspend. Refer to Appendix D, Command Interface State Table, for detailed information on which commands are valid during erase
suspend.
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 13. Lock Status
Current
Protection Status(1)
(WP, DQ1, DQ0)
Next Protection Status(1)
(WP, DQ1, DQ0)
Current State
Program/Erase
Allowed
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
After
WP transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
1,0,1(2)
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
0,0,1(2)
no
0,0,1
0,0,0
0,1,1
1,0,1
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Read Electronic Signature command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
29/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES
The Program and Erase times and the number of
Program/ Erase cycles depends on the voltage
Program/ Erase cycles per block are shown in Tasupply used.
ble 14. In the M58CR064 the maximum number of
Table 14. Program, Erase Times and Program, Erase Endurance Cycles
Typ
Typical
after
100k W/E
Cycles
Max
Unit
0.3
1
2.5
s
Preprogrammed
0.8
3
4
s
Not Preprogrammed
1.1
4
s
Preprogrammed
11
s
Not Preprogrammed
18
s
Preprogrammed
33
s
Not Preprogrammed
54
s
Parameter Block (4 KWord) Program(3)
40
ms
Main Block (32 KWord) Program(3)
300
ms
Word Program (3)
10
Program Suspend Latency
Erase Suspend Latency
Parameter
Condition
Min
Parameter Block (4 KWord) Erase(2)
Main Block (32 KWord) Erase
VPP = VDD
Bank A (16Mbit) Erase
Bank B (48Mbit) Erase
10
100
µs
5
10
µs
5
20
µs
Main Blocks
100,000
cycles
Parameter Blocks
100,000
cycles
Program/Erase Cycles (per Block)
Parameter Block (4 KWord) Erase
0.3
2.5
s
Main Block (32 KWord) Erase
0.9
4
s
Bank A (16Mbit) Erase
13
s
Bank B (48Mbit) Erase
39
s
510
ms
VPP = VPPH
4Mbit Program
Quadruple Word
Word/ Double Word/ Quadruple Word Program(3)
Parameter Block (4 KWord)
Program(3)
Main Block (32 KWord) Program(3)
8
100
µs
Quadruple Word
8
ms
Word
32
ms
Quadruple Word
64
ms
Word
256
ms
Main Blocks
1000
cycles
Parameter Blocks
2500
cycles
Program/Erase Cycles (per Block)
Note: 1. TA = –40 to 85°C; VDD = 1.65V to 2V; VDDQ = 1.65V to 3.3V.
2. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).
3. Excludes the time needed to execute the command sequence.
30/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 15. Absolute Maximum Ratings
Value
Symbol
Min
Max
Unit
Ambient Operating Temperature
–40
85
°C
TBIAS
Temperature Under Bias
–40
125
°C
TSTG
Storage Temperature
–55
155
°C
VIO
Input or Output Voltage
–0.5
VDDQ+0.5
V
VDD
Supply Voltage
–0.5
2.7
V
Input/Output Supply Voltage
–0.5
3.6
V
Program Voltage
–0.5
13
V
Output Short Circuit Current
100
mA
Time for VPP at VPPH
100
hours
TA
VDDQ
VPP
IO
tVPPH
Parameter
31/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 16, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when relying on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
85
90
100
120
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
VDD Supply Voltage
1.8
2.0
1.7
2.0
1.65
2.0
1.65
2.0
V
VDDQ Supply Voltage
1.8
3.3
1.7
3.3
1.65
3.3
1.65
3.3
V
VPP Supply Voltage (Factory environment)
11.4
12.6
11.4
12.6
11.4
12.6
11.4
12.6
V
VPP Supply Voltage (Application
environment)
–0.4
VDDQ
+0.4
–0.4
VDDQ
+0.4
–0.4
VDDQ
+0.4
–0.4
VDDQ
+0.4
V
Ambient Operating Temperature
–40
85
–40
85
–40
85
–40
85
°C
Load Capacitance (CL)
30
30
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
30
30
pF
4
4
4
4
ns
0 to VDDQ
0 to VDDQ
0 to VDDQ
0 to VDDQ
V
VDDQ/2
VDDQ/2
VDDQ/2
VDDQ/2
V
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
VDDQ
VDDQ
VDDQ
VDDQ/2
VDD
0V
16.7kΩ
AI06161
DEVICE
UNDER
TEST
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
AI06162
Table 17. Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
32/70
Test Condition
Min
Max
Unit
VIN = 0V
6
8
pF
VOUT = 0V
8
12
pF
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 18. DC Characteristics - Currents
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
ILO
Output Leakage Current
Supply Current
Asynchronous Read (f=6MHz)
IDD1
Supply Current
Synchronous Read (f=40MHz)
Supply Current
Synchronous Read (f=54MHz)
IDD2
Supply Current
(Power-Down)
IDD3
Supply Current (Standby)
Min
Typ
Max
Unit
0V ≤ VIN ≤ VDDQ
±1
µA
0V ≤ VOUT ≤ VDDQ
±1
µA
E = VIL, G = VIH
3
6
mA
4 Word
6
13
mA
8 Word
8
14
mA
Continuous
6
10
mA
4 Word
7
16
mA
8 Word
10
18
mA
Continuous
13
25
mA
RP = VSS ± 0.2V
2
10
µA
E = VDD ± 0.2V
10
50
µA
VPP = VPPH
8
15
mA
VPP = VDD
10
20
mA
VPP = VPPH
8
15
mA
VPP = VDD
10
20
mA
Program/Erase in one
Bank, Asynchronous
Read in another Bank
13
26
mA
Program/Erase in one
Bank, Synchronous
Read in another Bank
16
30
mA
E = VDD ± 0.2V
10
50
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
100
400
µA
VPP ≤ VDD
0.2
5
µA
VPP ≤ VDD
0.2
5
µA
Supply Current (Program)
IDD4 (1)
Supply Current (Erase)
Supply Current
IDD5 (1,2) (Dual Operations)
IDD6(1)
Supply Current Program/ Erase
Suspended (Standby)
VPP Supply Current (Program)
IPP1(1)
VPP Supply Current (Erase)
IPP2
IPP3(1)
VPP Supply Current (Read)
VPP Supply Current (Standby)
Note: 1. Sampled only, not 100% tested.
2. VDD Dual Operation current is the sum of read and program or erase currents.
33/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 19. DC Characteristics - Voltages
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
IOH = –100µA
VDDQ –0.1
VPP1
VPP Program Voltage-Logic
Program, Erase
1
1.8
1.95
V
VPPH
VPP Program Voltage Factory
Program, Erase
11.4
12
12.6
V
VPPLK
Program or Erase Lockout
0.9
V
VLKO
VDD Lock Voltage
VRPH
RP pin Extended High Voltage
34/70
V
1
V
3.3
V
Hi-Z
Hi-Z
tELLH
tLLLH
tAVLH
tELQV
tAVQV
tELTV
tGLQV
tAVAV
Outputs Enabled
tGLTV
tGLQX
tLHGL
tLLQV
tLHAX
tELQX
VALID
Valid Address Latch
Note. Write Enable, W, is High.
DQ0-DQ15
WAIT
G
E
L
A0-A21
Data Valid
VALID
tAXQX
tEHTZ
tGHQZ
tGHQX
tEHQX
tEHQZ
Standby
VALID
AI90009b
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 10. Asynchronous Random Access Read AC Waveforms
35/70
36/70
DQ0-DQ15
WAIT
G
E
L
A0-A1
A2-A21
Hi-Z
tELTV
tELQX
tGLQV
tGLTV
tGLQX
tELQV
tLLQV
Valid Address Latch
tELLH
tLLLH
tAVLH
VALID ADDRESS
tAVAV
Enabled
Outputs
tLHGL
tLHAX
VALID DATA
VALID DATA
VALID ADDRESS
Valid Data
VALID DATA
tAVQV1
VALID ADDRESS
VALID ADDRESS
VALID DATA
VALID ADDRESS
Standby
AI90048c
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 11. Asynchronous Page Read AC Waveforms
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 20. Asynchronous Read AC Characteristics
Symbol
Alt
Read Timings
85
90
100
120
Unit
tAVAV
tRC
Address Valid to Next Address Valid
Min
85
90
100
120
ns
tAVQV
tACC
Address Valid to Output Valid (Random)
Max
85
90
100
120
ns
tAVQV1
tPAGE
Address Valid to Output Valid (Page)
Max
30
30
45
45
ns
tAXQX (1)
tOH
Address Transition to Output Transition
Min
0
0
0
0
ns
Chip Enable Low to Wait Valid
Max
14
14
14
18
ns
tELTV
tELQV (2)
tCE
Chip Enable Low to Output Valid
Max
85
90
100
120
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
Min
0
0
0
0
ns
Chip Enable High to Wait Hi-Z
Max
20
20
20
20
ns
tEHTZ
(1)
tOH
Chip Enable High to Output Transition
Min
0
0
0
0
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
Max
20
20
20
20
ns
tGLQV (2)
tOE
Output Enable Low to Output Valid
Max
25
25
25
25
ns
tGLQX (1)
tOLZ
Output Enable Low to Output Transition
Min
0
0
0
0
ns
Output Enable Low to Wait Valid
Max
14
14
14
18
ns
tEHQX
tGLTV
Latch Timings
M58CR064
Parameter
tGHQX (1)
tOH
Output Enable High to Output Transition
Min
0
0
0
0
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
Max
20
20
20
20
ns
tAVLH
tAVADVH
Address Valid to Latch Enable High
Min
10
10
10
10
ns
tELLH
tELADVH
Chip Enable Low to Latch Enable High
Min
10
10
10
10
ns
tLHAX
tADVHAX
Latch Enable High to Address Transition
Min
10
10
10
10
ns
tLLLH
tADVLADVH
Latch Enable Pulse Width
Min
10
10
10
10
ns
tLLQV
tADVLQV
Latch Enable Low to Output Valid (Random)
Max
85
90
100
120
ns
tLHGL
tADVHGL
Latch Enable High to Output Enable Low
Min
10
10
10
10
ns
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV .
37/70
38/70
Hi-Z
tELKH
Hi-Z
tLLLH
Address
Latch
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
X Latency
tGLTV
tGLQX
Note 1
tKHQV
tKHKH
VALID
Valid Data Flow
tKHQV
VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before.
3. Address latched and data output on the rising clock edge.
WAIT
G
E
K
L
A0-A21
DQ0-DQ15
Note 2
tKHTX
tKHKL
tKHQX
tKHQX
VALID
Boundary
Crossing
Note 2
tKHTV
tKHTX
tKLKH
tKHQV
tKHQX
NOT VALID
Data
Valid
tGHQZ
tGHQX
AI90010b
Standby
tEHTZ
tEHQZ
tEHQX
tEHEL
VALID
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 12. Synchronous Burst Read AC Waveforms
Hi-Z
tELKH
Hi-Z
tLLLH
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
tGLTV
tGLQV
tGLQX
Note 1
tKHQV
Note 3
VALID
tKHKH
NOT VALID
tKHKL
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state.
3. WAIT is always deasserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode.
WAIT signals valid data if the addressed bank is in Read Array mode.
4. Address latched and data output on the rising clock edge.
WAIT(2)
G
E
K(4)
L
A0-A21
DQ0-DQ15
NOT VALID
tKLKH
tGHQZ
tGHQX
tEHEL
tEHQZ
tEHTZ
NOT VALID
tEHQX
NOT VALID
AI06232
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 13. Single Synchronous Read AC Waveforms
39/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 21. Synchronous Read AC Characteristics
M58CR064
Clock Specifications
Synchronous Read Timings
Symbol
Alt
Parameter
Unit
90
100
120
tAVKH
tAVCLKH
Address Valid to Clock High
Min
7
7
7
7
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
7
7
7
7
ns
tELTV
Chip Enable Low to Wait Valid
Max
14
14
14
18
ns
tEHEL
Chip Enable Pulse Width
(subsequent synchronous reads)
Min
20
20
20
20
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
20
20
20
20
ns
tKHAX
tCLKHAX
Clock High to Address Transition
Min
10
10
10
10
ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
14
14
14
18
ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
4
4
4
4
ns
tLLKH
tADVLCLKH
Latch Enable Low to Clock High
Min
7
7
7
7
ns
Clock Period (f=40MHz)
Min
25
ns
tKHKH
tCLK
Clock Period (f=54MHz)
Min
18
18
18
ns
tKHKL
tCLKHCLKL
Clock High to Clock Low
Min
5
5
5
5
ns
tKLKH
tCLKLCLKH
Clock Low to Clock High
Max
5
5
5
5
ns
Note: 1. Sampled only, not 100% tested.
2. For other timings please refer to Table 20, Asynchronous Read AC Characteristics.
40/70
85
K
VPP
WP
DQ0-DQ15
W
G
E
L
A0-A21
tWLWH
tLHAX
COMMAND
tLLLH
SET-UP COMMAND
tDVWH
tGHWL
tELWL
tELLH
tAVLH
BANK ADDRESS
tWHDX
CMD or DATA
tWHKV
tWHEL
tWHVPL
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
tWHWPL
tWHQV
tWHGL
tWHAX
tWHAV
CONFIRM COMMAND
OR DATA INPUT
tVPHWH
tWPHWH
tWHWL
tWHEH
tWHLL
tAVWH
VALID ADDRESS
tAVAV
PROGRAM OR ERASE
AI90011b
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 14. Write AC Waveforms, Write Enable Controlled
41/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 22. Write AC Characteristics, Write Enable Controlled
M58CR064
Symbol
tAVAV
Alt
tWC
tAVLH
90
100
120
Address Valid to Next Address Valid
Min
85
90
100
120
ns
Address Valid to Latch Enable High
Min
10
10
10
10
ns
tWC
Address Valid to Write Enable High
Min
60
60
60
60
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
40
40
40
40
ns
Chip Enable Low to Latch Enable High
Min
10
10
10
10
ns
Chip Enable Low to Write Enable Low
Min
0
0
0
0
ns
tELQV
Chip Enable Low to Output Valid
Min
85
90
100
120
ns
tGHWL
Output Enable High to Write Enable Low
Min
20
20
20
20
ns
tLHAX
Latch Enable High to Address Transition
Min
10
10
10
10
ns
tLLLH
Latch Enable Pulse Width
Min
10
10
10
10
ns
tWHAV
Write Enable High to Address Valid
Min
0
0
0
0
ns
tELWL
Write Enable Controlled Timings
Unit
85
tAVWH
tELLH
tCS
tWHAX
tAH
Write Enable High to Address Transition
Min
0
0
0
0
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
0
0
ns
Write Enable High to Chip Enable Low
Min
50
50
50
50
ns
tWHGL
Write Enable High to Output Enable Low
Min
0
0
0
0
ns
tWHLL
Write Enable High to Latch Enable Low
Min
0
0
0
0
ns
tWHKV
Write Enable High to Clock Valid
Min
25
25
25
25
ns
tWHWL
tWPH Write Enable High to Write Enable Low
Min
30
30
30
30
ns
Write Enable High to Output Valid
Min
105
110
120
140
ns
Write Enable Low to Write Enable High
Min
50
50
50
50
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
0
0
0
ns
tQVWPL
Output (Status Register) Valid to Write Protect Low
Min
0
0
0
0
ns
VPP High to Write Enable High
Min
200
200
200
200
ns
tWHVPL
Write Enable High to VPP Low
Min
200
200
200
200
ns
tWHWPL
Write Enable High to Write Protect Low
Min
200
200
200
200
ns
tWPHWH
Write Protect High to Write Enable High
Min
200
200
200
200
ns
tWHEL(2)
tWHQV
tWLWH
Protection Timings
Parameter
tVPHWH
tWP
tVPS
Note: 1. Sampled only, not 100% tested.
2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing a command. If the read operation is in a different
bank tWHEL is 0ns.
42/70
K
VPP
WP
DQ0-DQ15
E
G
W
L
A0-A21
tGHEL
tELEH
tLHAX
COMMAND
SET-UP COMMAND
tDVEH
tLLLH
tELLH
tWLEL
tAVLH
BANK ADDRESS
tEHDX
tEHEL
tEHWH
CMD or DATA
tEHAX
CONFIRM COMMAND
OR DATA INPUT
tVPHEH
tWPHEH
tAVEH
VALID ADDRESS
tAVAV
tEHVPL
tEHWPL
tWHKV
tWHEL
tEHGL
tQVVPL
tQVWPL
STATUS REGISTER
STATUS REGISTER
READ
1st POLLING
tELQV
VALID ADDRESS
PROGRAM OR ERASE
AI90012b
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 15. Write AC Waveforms, Chip Enable Controlled
43/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 23. Write AC Characteristics, Chip Enable Controlled
M58CR064
Symbol
Alt
Chip Enable Controlled Timings
Unit
85
90
100
120
tAVAV
tWC
Address Valid to Next Address Valid
Min
85
90
100
120
ns
tAVEH
tWC
Address Valid to Chip Enable High
Min
60
60
60
60
ns
Address Valid to Latch Enable High
Min
10
10
10
10
ns
tAVLH
tDVEH
tDS
Input Valid to Write Enable High
Min
40
40
40
40
ns
tEHAX
tAH
Chip Enable High to Address Transition
Min
0
0
0
0
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
0
0
ns
Min
30
30
30
30
ns
Chip Enable High to Output Enable Low
Min
0
0
0
0
ns
Chip Enable High to Write Enable High
Min
0
0
0
0
ns
Min
60
60
60
60
ns
tEHEL
tWPH Chip Enable High to Chip Enable Low
tEHGL
tEHWH
tCH
tELEH
tWP Chip Enable Low to Chip Enable High
tELLH
Chip Enable Low to Latch Enable High
Min
10
10
10
10
ns
tELQV
Latch Enable Low to Output Valid
Min
85
90
100
120
ns
tGHEL
Output Enable High to Chip Enable Low
Min
20
20
20
20
ns
tLHAX
Latch Enable High to Address Transition
Min
10
10
10
10
ns
tLLLH
Latch Enable Pulse Width
Min
10
10
10
10
ns
Write Enable High to Chip Enable Low
Min
50
50
50
50
ns
Write Enable High to Clock Valid
Min
25
25
25
25
ns
Write Enable Low to Chip Enable Low
Min
0
0
0
0
ns
tEHVPL
Chip Enable High to VPP Low
Min
200
200
200
200
ns
tEHWPL
Chip Enable High to Write Protect Low
Min
200
200
200
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
0
0
0
ns
tQVWPL
Output (Status Register) Valid to Write Protect Low
Min
0
0
0
0
ns
Min
200
200
200
200
ns
Min
200
200
200
200
ns
tWHEL(2)
tWHKV
tWLEL
Protection Timings
Parameter
tVPHEH
tWPHEH
tCS
tVPS VPP High to Chip Enable High
Write Protect High to Chip Enable High
Note: 1. Sampled only, not 100% tested.
2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing a command. If the read operation is in a different
bank tWHEL is 0ns.
44/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 16. Reset and Power-up AC Waveforms
tPLWL
tPLEL
tPLGL
tPLLL
W, E, G, L
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI90013c
Table 24. Reset and Power-up AC Characteristics
Symbol
tPLWL
tPLEL
tPLGL
tPLLL
Parameter
Reset Low to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
Test Condition
85
90
100
120
Unit
During Program
Min
10
10
10
10
µs
During Erase
Min
20
20
20
20
µs
Other Conditions
Min
80
80
80
80
ns
tPLPH (1,2)
RP Pulse Width
Min
50
50
50
50
ns
tVDHPH (3)
Supply Voltages High to Reset
High
Min
50
50
50
50
µs
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
45/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
PACKAGE MECHANICAL
Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline
D
D1
SD
FD
FE
E
E1
e
BALL "A1"
ddd
b
e
A2
A
A1
BGA-Z20
Note: Drawing is not to scale.
Table 25. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
A
1.010
A1
0.250
Min
Max
1.200
0.0398
0.0472
0.400
0.0098
0.0157
A2
0.790
0.0311
b
0.400
0.350
0.450
0.0157
0.0138
0.0177
D
6.500
6.400
6.600
0.2559
0.2520
0.2598
D1
5.250
–
–
0.2067
–
–
ddd
46/70
Typ
0.100
0.0039
E
10.000
9.900
10.100
0.3937
0.3898
0.3976
E1
4.500
–
–
0.1772
–
–
e
0.750
–
–
0.0295
–
–
FD
0.625
–
–
0.0246
–
–
FE
2.750
–
–
0.1083
–
–
SD
0.375
–
–
0.0148
–
–
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 18. TFBGA56 Daisy Chain - Package Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
AI07731
47/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 19. TFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package)
1
2
3
4
5
6
7
8
START POINT
A
B
C
D
E
F
G
END POINT
AI07755
48/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
PART NUMBERING
Table 26. Ordering Information Scheme
Example:
M58CR064C
85 ZB
6
T
Device Type
M58
Architecture
C = Dual Bank, Burst Mode
Operating Voltage
R = VDD = 1.65V to 2.0V, VDDQ = 1.65V to 3.3V
Device Function
064C = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot
064D = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot
064P = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot,
VPP protection feature disabled
064Q = 64 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot,
VPP protection feature disabled
Speed
85 = 85ns
90 = 90ns
10 = 100ns
12 = 120ns
Package
ZB = TFBGA56: 6.5 x 10mm, 0.75 mm pitch
Temperature Range
6 = –40 to 85°C
Option
T = Tape & Reel packing
Table 27. Daisy Chain Ordering Scheme
Example:
M58CR064
-ZB T
Device Type
M58CR064
Daisy Chain
ZB = TFBGA56: 6.5 x 10mm, 0.75 mm pitch
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
49/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
APPENDIX A. BLOCK ADDRESS TABLES
Table 28. Top Boot Block Addresses,
M58CR064C, M58CR064P
#
Bank A
2F8000-2FFFFF
32
2F0000-2F7FFF
Address Range
41
32
2E8000-2EFFFF
32
2E0000-2E7FFF
0
4
3FF000-3FFFFF
42
1
4
3FE000-3FEFFF
43
32
2D8000-2DFFFF
44
32
2D0000-2D7FFF
45
32
2C8000-2CFFFF
3FB000-3FBFFF
46
32
2C0000-2C7FFF
47
32
2B8000-2BFFFF
48
32
2B0000-2B7FFF
32
2A8000-2AFFFF
2
4
3FD000-3FDFFF
3
4
3FC000-3FCFFF
4
50/70
32
40
4
5
4
3FA000-3FAFFF
6
4
3F9000-3F9FFF
7
4
3F8000-3F8FFF
49
8
32
3F0000-3F7FFF
50
32
2A0000-2A7FFF
51
32
298000-29FFFF
52
32
290000-297FFF
32
288000-28FFFF
9
32
3E8000-3EFFFF
10
32
3E0000-3E7FFF
11
32
3D8000-3DFFFF
53
12
32
3D0000-3D7FFF
54
32
280000-287FFF
55
32
278000-27FFFF
13
32
3C8000-3CFFFF
14
32
3C0000-3C7FFF
56
32
270000-277FFF
15
32
3B8000-3BFFFF
57
32
268000-26FFFF
58
32
260000-267FFF
59
32
258000-25FFFF
32
250000-257FFF
248000-24FFFF
16
32
3B0000-3B7FFF
17
32
3A8000-3AFFFF
Bank B
Bank
Size
(KWord)
39
18
32
3A0000-3A7FFF
60
19
32
398000-39FFFF
61
32
62
32
240000-247FFF
32
238000-23FFFF
20
32
390000-397FFF
21
32
388000-38FFFF
63
22
32
380000-387FFF
64
32
230000-237FFF
65
32
228000-22FFFF
23
32
378000-37FFFF
24
32
370000-377FFF
66
32
220000-227FFF
32
218000-21FFFF
25
32
368000-36FFFF
67
26
32
360000-367FFF
68
32
210000-217FFF
69
32
208000-20FFFF
27
32
358000-35FFFF
28
32
350000-357FFF
70
32
200000-207FFF
71
32
1F8000-1FFFFF
72
32
1F0000-1F7FFF
29
32
348000-34FFFF
30
32
340000-347FFF
31
32
338000-33FFFF
73
32
1E8000-1EFFFF
32
1E0000-1E7FFF
32
32
330000-337FFF
74
33
32
328000-32FFFF
75
32
1D8000-1DFFFF
32
1D0000-1D7FFF
34
32
320000-327FFF
76
35
32
318000-31FFFF
77
32
1C8000-1CFFFF
78
32
1C0000-1C7FFF
36
32
310000-317FFF
37
32
308000-30FFFF
38
32
300000-307FFF
Bank B
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
32
1B8000-1BFFFF
110
32
0C0000-0C7FFF
80
32
1B0000-1B7FFF
111
32
0B8000-0BFFFF
81
32
1A8000-1AFFFF
112
32
0B0000-0B7FFF
82
32
1A0000-1A7FFF
113
32
0A8000-0AFFFF
83
32
198000-19FFFF
114
32
0A0000-0A7FFF
84
32
190000-197FFF
115
32
098000-09FFFF
85
32
188000-18FFFF
116
32
090000-097FFF
86
32
180000-187FFF
117
32
088000-08FFFF
87
32
178000-17FFFF
118
32
080000-087FFF
88
32
170000-177FFF
119
32
078000-07FFFF
89
32
168000-16FFFF
120
32
070000-077FFF
90
32
160000-167FFF
121
32
068000-06FFFF
91
32
158000-15FFFF
122
32
060000-067FFF
92
32
150000-157FFF
123
32
058000-05FFFF
93
32
148000-14FFFF
124
32
050000-057FFF
94
32
140000-147FFF
125
32
048000-04FFFF
95
32
138000-13FFFF
126
32
040000-047FFF
96
32
130000-137FFF
127
32
038000-03FFFF
97
32
128000-12FFFF
128
32
030000-037FFF
98
32
120000-127FFF
129
32
028000-02FFFF
99
32
118000-11FFFF
130
32
020000-027FFF
100
32
110000-117FFF
131
32
018000-01FFFF
101
32
108000-10FFFF
132
32
010000-017FFF
102
32
100000-107FFF
133
32
008000-00FFFF
103
32
0F8000-0FFFFF
134
32
000000-007FFF
104
32
0F0000-0F7FFF
105
32
0E8000-0EFFFF
106
32
0E0000-0E7FFF
107
32
0D8000-0DFFFF
108
32
0D0000-0D7FFF
109
32
0C8000-0CFFFF
Bank B
79
51/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 29. Bottom Boot Block Addresses,
M58CR064D, M58CR064Q
Bank B
32
2B8000-2BFFFF
2B0000-2B7FFF
Size
(KWord)
Address Range
92
32
2A8000-2AFFFF
134
32
3F8000-3FFFFF
91
32
2A0000-2A7FFF
90
32
298000-29FFFF
89
32
290000-297FFF
32
288000-28FFFF
133
32
3F0000-3F7FFF
132
32
3E8000-3EFFFF
131
32
3E0000-3E7FFF
88
130
32
3D8000-3DFFFF
87
32
280000-287FFF
32
278000-27FFFF
129
32
3D0000-3D7FFF
86
128
32
3C8000-3CFFFF
85
32
270000-277FFF
127
32
3C0000-3C7FFF
84
32
268000-26FFFF
83
32
260000-267FFF
82
32
258000-25FFFF
32
250000-257FFF
126
32
3B8000-3BFFFF
125
32
3B0000-3B7FFF
124
32
3A8000-3AFFFF
81
123
32
3A0000-3A7FFF
80
32
248000-24FFFF
79
32
240000-247FFF
238000-23FFFF
122
32
398000-39FFFF
121
32
390000-397FFF
78
32
388000-38FFFF
77
32
230000-237FFF
76
32
228000-22FFFF
75
32
220000-227FFF
74
32
218000-21FFFF
73
32
210000-217FFF
72
32
208000-20FFFF
120
32
119
32
380000-387FFF
118
32
378000-37FFFF
117
32
370000-377FFF
116
32
368000-36FFFF
115
32
360000-367FFF
114
32
358000-35FFFF
71
32
200000-207FFF
32
1F8000-1FFFFF
113
32
350000-357FFF
70
112
32
348000-34FFFF
69
32
1F0000-1F7FFF
111
32
340000-347FFF
68
32
1E8000-1EFFFF
32
1E0000-1E7FFF
110
32
338000-33FFFF
67
109
32
330000-337FFF
66
32
1D8000-1DFFFF
65
32
1D0000-1D7FFF
108
32
328000-32FFFF
107
32
320000-327FFF
64
32
1C8000-1CFFFF
63
32
1C0000-1C7FFF
62
32
1B8000-1BFFFF
308000-30FFFF
61
32
1B0000-1B7FFF
32
1A8000-1AFFFF
106
32
318000-31FFFF
105
32
310000-317FFF
104
52/70
32
93
#
Bank B
Bank
94
32
103
32
300000-307FFF
60
102
32
2F8000-2FFFFF
59
32
1A0000-1A7FFF
58
32
198000-19FFFF
101
32
2F0000-2F7FFF
100
32
2E8000-2EFFFF
57
32
190000-197FFF
56
32
188000-18FFFF
55
32
180000-187FFF
99
32
2E0000-2E7FFF
98
32
2D8000-2DFFFF
97
32
2D0000-2D7FFF
96
32
2C8000-2CFFFF
95
32
2C0000-2C7FFF
Bank A
54
32
178000-17FFFF
22
32
53
32
170000-177FFF
21
32
070000-077FFF
52
32
168000-16FFFF
20
32
068000-06FFFF
51
32
160000-167FFF
19
32
060000-067FFF
50
32
158000-15FFFF
18
32
058000-05FFFF
49
32
150000-157FFF
17
32
050000-057FFF
48
32
148000-14FFFF
16
32
048000-04FFFF
47
32
140000-147FFF
15
32
040000-047FFF
46
32
138000-13FFFF
14
32
038000-03FFFF
45
32
130000-137FFF
13
32
030000-037FFF
44
32
128000-12FFFF
12
32
028000-02FFFF
43
32
120000-127FFF
11
32
020000-027FFF
42
32
118000-11FFFF
10
32
018000-01FFFF
41
32
110000-117FFF
9
32
010000-017FFF
40
32
108000-10FFFF
8
32
008000-00FFFF
39
32
100000-107FFF
7
4
007000-007FFF
38
32
0F8000-0FFFFF
6
4
006000-006FFF
37
32
0F0000-0F7FFF
5
4
005000-005FFF
36
32
0E8000-0EFFFF
4
4
004000-004FFF
35
32
0E0000-0E7FFF
3
4
003000-003FFF
34
32
0D8000-0DFFFF
2
4
002000-002FFF
33
32
0D0000-0D7FFF
1
4
001000-001FFF
32
32
0C8000-0CFFFF
0
4
000000-000FFF
31
32
0C0000-0C7FFF
30
32
0B8000-0BFFFF
29
32
0B0000-0B7FFF
28
32
0A8000-0AFFFF
27
32
0A0000-0A7FFF
26
32
098000-09FFFF
25
32
090000-097FFF
24
32
088000-08FFFF
23
32
080000-087FFF
Bank A
Bank B
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
078000-07FFFF
53/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
APPENDIX B. COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the Read CFI Query Command is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 30, 31,
32, 33, 34 and 35 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0-DQ7),
the other outputs (DQ8-DQ15) are set to 0.
The CFI data structure also contains a security
area where a 64 bit unique security number is written (see Figure 5, Security Block and Protection
Register Memory Map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has
been written by ST. Issue a Read Array command
to return to Read mode.
Table 30. Query Structure Overview
Offset
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Security Code Area
Lock Protection Register
Unique device Number and
User Programmable OTP
80h
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailed in Tables 31, 32, 33, 34 and 35. Query data is always presented on the lowest order data outputs.
Table 31. CFI Query Identification String
Offset
Sub-section Name
Description
00h
0020h
Manufacturer Code
01h
88CAh
88CBh
8801h
8802h
Device Code (M58CR064C/D/P/Q)
02h
reserved
Reserved
03h
reserved
Reserved
04h-0Fh
reserved
Reserved
10h
0051h
11h
0052h
12h
0059h
13h
0003h
14h
0000h
15h
offset = P = 0039h
16h
0000h
17h
0000h
18h
0000h
19h
value = A = 0000h
1Ah
0000h
54/70
Value
ST
Top
Bottom
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16
bit ID code defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 33)
p = 39h
Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported
NA
Address for Alternate Algorithm extended Query table
NA
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 32. CFI Query System Interface Information
Offset
Data
Description
Value
1Bh
0017h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
1.7V
1Ch
0020h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
2.0V
1Dh
0017h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
1.7V
1Eh
00C0h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
12V
1Fh
0004h
Typical time-out per single byte/word program = 2n µs
16µs
20h
0003h
Typical time-out for quadruple word program = 2n µs
8µs
21h
000Ah
Typical time-out per individual block erase = 2n ms
1s
22h
0000h
Typical time-out for full chip erase = 2n ms
NA
23h
0003h
Maximum time-out for word program = 2n times typical
128µs
24h
0004h
Maximum time-out for quadruple word = 2n times typical
128µs
25h
0002h
Maximum time-out per individual block erase = 2n times typical
4s
26h
0000h
Maximum time-out for chip erase = 2n times typical
NA
Table 33. Device Geometry Definition
Data
27h
0017h
Device Size = 2n in number of bytes
28h
29h
0001h
0000h
Flash Device Interface Code description
x16
Async.
2Ah
2Bh
0003h
0000h
Maximum number of bytes in multi-byte program or page = 2n
8 Byte
2Ch
0002h
Number of identical sized erase block regions within the device
bit 7 to 0 = x = number of Erase Block Regions
2Dh
2Eh
007Eh
0000h
Region 1 Information
Number of identical-size erase blocks = 007Eh+1
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase blocks = 000Eh+1
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
35h
38h
0000h
Reserved for future erase block region information
M58CR064C/P
Offset Word
Mode
Description
Value
8 MByte
2
127
64 KByte
8
8 KByte
NA
55/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
M58CR064D/Q
Offset Word
Mode
Data
Description
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
31h
32h
007Eh
0000h
Region 2 Information
Number of identical-size erase block = 007Eh+1
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
35h
38h
0000h
Reserved for future erase block region information
Value
8
8 KByte
127
64 KByte
NA
Table 34. Primary Algorithm-Specific Extended Query Table
Offset
Data
(P)h = 39h
0050h
0052h
Description
Value
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
0049h
"R"
"I"
(P+3)h = 3Ch
0031h
Major version number, ASCII
"1"
(P+4)h = 3Dh
0030h
Minor version number, ASCII
"0"
(P+5)h = 3Eh
00E6h
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
0003h
(P+7)h = 40h
0000h
(P+8)h = 41h
0000h
(P+9)h = 42h
0001h
(P+A)h = 43h
0003h
(P+B)h = 44h
0000h
(P+C)h = 45h
56/70
0018h
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
0
1
2
3
4
5
6
7
8
9
10 to 31
Chip Erase supported
(1 = Yes, 0 = No)
Erase Suspend supported
(1 = Yes, 0 = No)
Program Suspend supported
(1 = Yes, 0 = No)
Legacy Lock/Unlock supported
(1 = Yes, 0 = No)
Queued Erase supported
(1 = Yes, 0 = No)
Instant individual block locking supported (1 = Yes, 0 = No)
Protection bits supported
(1 = Yes, 0 = No)
Page mode read supported
(1 = Yes, 0 = No)
Synchronous read supported
(1 = Yes, 0 = No)
Simultaneous operation supported
(1 = Yes, 0 = No)
Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31
bit field of optional features follows at the end of the bit-30
field.
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
bit 0
Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1
Reserved; undefined bits are ‘0’
Block Protect Status
Defines which bits in the Block Status Register section of the Query are
implemented.
bit 0 Block protect Status Register Lock/Unlock
bit active
(1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
VDD Logic Supply Optimum Program/Erase voltage (highest performance)
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.8V
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Offset
Data
Description
(P+D)h = 46h
00C0h
VPP Supply Optimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
(P+E)h = 47h
(P+F)h = 48h
(P+10)h = 49h
(P+11)h = 4Ah
(P+12)h = 4Bh
0000h
Reserved
Value
12V
Table 35. Burst Read Information
Offset
Data
Description
Value
(P+13)h = 4Ch
0003h
Page-mode read capability
bits 0-7
’n’ such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to
determine page-mode data output width.
(P+14)h = 4Dh
0003h
Number of synchronous mode read configuration fields that follow.
3
(P+15)h = 4Eh
0001h
Synchronous mode read capability configuration 1
bit 3-7
Reserved
bit 0-2
’n’ such that 2n+1 HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h
indicates that the device is capable of continuous linear bursts
that will output data until the internal burst counter reaches
the end of the device’s burstable address space. This field’s
3-bit value can be written directly to the read configuration
register bit 0-2 if the device is configured for its maximum
word width. See offset 28h for word width to determine the
burst data output width.
4
(P+16)h = 4Fh
0002h
Synchronous mode read capability configuration 2
8
(P+17)h = 50h
0007h
Synchronous mode read capability configuration 3
Cont.
(P+18)h = 51h
0036h
Max operating clock frequency (MHz)
(P+19)h = 52h
0001h
Supported handshaking signal (WAIT pin)
bit 0 during synchronous read (1 = Yes, 0 = No)
bit 1 during asynchronous read (1 = Yes, 0 = No)
8 Bytes
54 MHz
Yes
No
57/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
APPENDIX C. FLOWCHARTS AND PSEUDO CODES
Figure 20. Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (bank_address, 0x40) ;
/*or writeToFlash (bank_address, 0x10) ; */
Write 40h or 10h
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06170
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or
after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
58/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 21. Double Word Program Flowchart and Pseudo code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (bank_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 1
& Data 1 (3)
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.b7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
YES
SR4 = 0
YES
SR1 = 0
NO
Program to Protected
Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06171
Note: 1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation or after
a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
59/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 22. Quadruple Word Program Flowchart and Pseudo Code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
writeToFlash (bank_address, 0x55) ;
Write 55h
Write Address 1
& Data 1 (3)
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.b7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06172
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or
after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
60/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 23. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR2 = 1
NO
Program Complete
YES
Write FFh
}
Read data from
another address
Write D0h
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
else
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
}
Write FFh
}
Program Continues
Read Data
AI06173
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 24. Block Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (bank_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1)
YES
Command
Sequence Error (1)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
SR4, SR5 = 1
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
NO
SR5 = 0
NO
Erase Error (1)
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
YES
SR1 = 0
NO
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06174
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 25. Erase Suspend & Resume Flowchart and Pseudo Code
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR6 = 1
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
YES
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
}
else
Write D0h
Write FFh
Erase Continues
Read Data
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
/*read or program data from another address*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
AI06175
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 26. Locking Operations Flowchart and Pseudo Code
Start
locking_operation_command (address, lock_operation) {
writeToFlash (bank_address, 0x60) ; /*configuration setup*/
Write 60h
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
Write
01h, D0h or 2Fh
writeToFlash (bank_address, 0x90) ;
Write 90h
Read Block
Lock States
Locking
change
confirmed?
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
NO
YES
writeToFlash (bank_address, 0xFF) ; /*Reset to Read Array mode*/
Write FFh
}
End
AI06176
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Figure 27. Protection Register Program Flowchart and Pseudo Code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (bank_address, 0xC0) ;
Write C0h
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06177
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or
after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
APPENDIX D. COMMAND INTERFACE STATE TABLES
Table 36. Command Interface States - Lock table
Current State of the
Current Bank
Current
State of
Other
Bank
Any State
Mode
State
Read
Array
CFI
Electronic
Signature
Status
Setup
Any State
Lock
Unlock
Lock-Down
CR
Command Input to the Current Bank (and Next State of the Current Bank)
Others
Read
Array
(FFH)
Erase
Confirm
P/E
Resume
Unlock
Confirm
(D0h)
Read
Status
Register
(70h)
Block Lock
Clear
Read
Unlock
Block lock
Read
Status Electronic
Lock-Down
Confirm
CFI Query
Register Signature
setup
(01h)
(98h)
(50h)
(90h)
Set CR
setup (60h)
SEE
Read
MODIFY Read Array Read Array Status Read Array
TABLE
Register
Block Lock
Unlock
Lock-Down
Error, Set
CR Error
Block lock
Block Lock
Unlock
Unlock
Lock-Down
Lock-Down
Error, Set
Block
CR Error
Block Lock
Unlock
Lock-Down
Error, Set
CR Error
Block Lock
Unlock
Lock-Down
Error, Set
CR Error
Read
Elect.
Sign.
Read
Elect.
Sign.
Read
Elect.
Sign.
Done
SEE
Read
MODIFY Read Array Read Array Status Read Array
TABLE
Register
ProgramDouble/
Quadruple
Program
Done
SEE
Read
MODIFY Read Array Read Array Status Read Array
TABLE
Register
Setup
Idle
Erase
Suspend
Read
Array, CFI,
Program
Elect.
Suspend
Sign.,
Status
Setup
Idle
Any State
Block/
Bank
Erase
Idle
Program
Suspend
Erase
Suspend
Read
Array, CFI,
Elect.
Sign.,
Status
Block Lock Block Lock
Block Lock Block Lock
Unlock
Unlock
Unlock
Unlock
Lock-Down Lock-Down
Lock-Down Lock-Down
Error, Set Error, Set
Block
Block
CR Error CR Error
Set CR
Block LocK
Unlock
Read CFI Lock-Down Read Array Read Array Read Array
Setup, Set
CR Setup
Block LocK
Unlock
Read CFI Lock-Down Read Array Read Array Read Array
Setup, Set
CR Setup
Block LocK
Unlock
Read CFI Lock-Down Read Array Read Array Read Array
Setup, Set
CR Setup
Program
(Busy)
PS Read
Status
Register
PS Read
Array
PS Read
Elect.
Sign.
PS Read
CFI
PS Read
Array
PS Read
Array
PS Read
Array
PS Read
Array
Erase
Error
Erase
Error
Erase
(Busy)
Erase
Error
Erase
Error
Erase
Error
Erase
Error
Erase Error
Erase
Error
Erase
Error
Erase
Error
SEE
Read
MODIFY Read Array Read Array Status Read Array
TABLE
Register
Read
Elect.
Sign.
Erase
(Busy)
ES Read
Array
Erase
(Busy)
ES Read
Array
ES Read
Elect.
Sign.
SEE
MODIFY
TABLE
ES Read
Array
Note: PS = Program Suspend, ES = Erase Suspend.
66/70
Block Lock,
Unlock,
Read CFI Lock-Down, Read Array Read Array Read Array
Set CR
Setup
PS Read
Array
Error
Done
Set CR
Confirm
(03h)
SEE
MODIFY
TABLE
Setup
Busy
Block Lock
Unlock
Lock-Down
Error, Set
CR Error
Error
Lock
SEE
Read
Unlock
MODIFY Read Array Read Array Status Read Array
Lock-Down
TABLE
Register
Block
Set CR
Protection
Any State
Register
Any State
Read
Elect.
Sign.
Block
LockDown
Confirm
(2Fh)
ES Read
Status
Register
ES Read
Array
Block LocK
Unlock
Read CFI Lock-Down Read Array Read Array Read Array
Setup, Set
CR Setup
ES Read
CFI
Block LocK
Unlock
ES Read
Lock-Down
Array
Setup, Set
CR Setup
ES Read
Array
ES Read
Array
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Table 37. Command Interface States - Modify Table
Current State
of the Other
Bank
Current State of the Current
Bank
Mode
State
Read
Array, CFI,
Electronic
Signature,
Status Register
Setup
Busy
Idle
Erase Suspend
Program
Suspend
Setup
Busy
Idle
Erase Suspend
Program
Suspend
Idle
Setup
Busy
Idle
Lock Unlock
Lock-Down CR
Error,
Lock Unlock
Lock-Down
Block,
Set CR
Setup
Busy
Done
Busy
Erase Suspend
Idle
Double/
Protection
Quadruple
Program-Erase
Register
Suspend (B0h) Program Setup Program Setup
(30h/55h)
(C0h)
Bank Erase
Setup (80h)
Read Array
Read Array
Read Array
Read Array
Read Array
Program setup
Block Erase
Setup
Protection
Register Setup
Double/
Quadruple
Program Setup
Bank Erase
Setup
SEE LOCK
TABLE
Program
Double/
Quadruple
Word Program
Done
Read Array
Read Array
Read Array
Read Array
Read Array
Read Array
Program setup
Block Erase
Setup
Protection
Register Setup
Double/
Quadruple
Program Setup
Bank Erase
Setup
Block/ Bank
Erase
Erase Suspend
Read Array
Read Array
Read Array
Read Array
Read Array
Read Array
Read Array
Protection
Protection
Protection
Protection
Protection
Protection
Protection
Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy)
SEE LOCK
TABLE
Program Setup
Read Array
Block Erase
Setup
Read Array
Read Array
Read Array
Protection
Register Setup
Read Array
Read Array
Double/
Quadruple
Program Setup
Read Array
Read Array
Bank Erase
Setup
Read Array
Program (Busy)
Program (Busy) Program (Busy) Program (Busy) PS Read Status Program (Busy) Program (Busy) Program (Busy)
Register
SEE LOCK
TABLE
Read Array
Read Array
Program Setup
Block Erase
Setup
Read Array
Program
Suspend
Read Array
Read Array
Read Array
Setup
Busy
Idle
Block Erase
Setup (20h)
Read Array
Protection
Register
Setup
Erase Suspend
Program
Suspend
Setup
Idle
SEE LOCK
TABLE
Program Setup
(10h/40h)
Read Array
Idle
Idle
Others
Read Array
Erase Suspend
Program
Suspend
Any State
Setup
Busy
Command Input to the Current Bank (and Next State of the Current Bank)
Read Array
Read Array
Read Array
Read Array
Read Array
Protection
Register Setup
Double/
Quadruple
Program Setup
Bank Erase
Setup
Read Array
Read Array
Read Array
Read Array,
CFI, Elect.
Sign., Status
Register
SEE LOCK
TABLE
Setup
SEE LOCK
TABLE
Erase Error
Erase Error
Erase Error
Erase Error
Erase Error
Erase Error
Busy
Erase (Busy)
Erase (Busy)
Erase (Busy)
ES Read Status
Register
Erase (Busy)
Erase (Busy)
Erase (Busy)
Read Array,
CFI, Elect.
Sign., Status
Register
SEE LOCK
TABLE
Program
Suspend
PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array
ES Read Array
ES Read Array
Program Setup ES Read Array ES Read Array ES Read Array
Double/
ES Read Array
Quadruple
Program Setup
ES Read Array
ES Read Array
Note: PS = Program Suspend, ES = Erase Suspend.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
REVISION HISTORY
Table 38. Document Revision History
Date
Version
November 2000
-01
First Issue
12/20/00
-02
Protection/Security clarification
Memory Map diagram clarification (Figure 4)
Single Synchronous Read clarification (Figure 6)
Identifier Codes clarification (Table 6)
X-Latency configuration clarification
CFI Query Identification String change (Table 31)
Synchronous Burst Read Waveforms change (Figure 12)
Reset AC Characteristics clarification (Table 24)
Program Time clarification (Table )
1/08/01
-03
Reset AC Characteristics clarification (Table 24)
Reset AC Waveforms diagram change (Figure 1)
3/02/01
-04
Document type: from Target Specification to Product Preview
Read Status Register clarification
Read Electronic Signature clarification
Protection Register Program clarification
Write Configuration Register clarification
Wait Configuration Sequence change (Figure 7)
CFI Query System Interface clarification (Table 32)
CFI Device Geometry change (Table 33)
Asynchronous Read AC Waveforms change (Figure 10)
Page Read AC Waveforms added (Figure 11)
Write AC Waveforms W Contr. and E Contr. change (Figure 14, 15)
Reset and Power-up AC Characteristics and Waveform change (Table 24, Figure 1)
TFBGA Package Mechanical Data and Outline added (Table 25, Figure 17)
4/05/01
-05
TFBGA Connections change
X-Latency Configuration Sequence change
Reset and Power-up AC Characteristics clarification
VDDQ clarification
23-Jul-2001
-06
Complete rewrite and restructure
23-Oct-2001
-07
85ns speed class added, document classified as Preliminary Data
15-Mar-2002
-08
Part numbers M58CR064P/Q added. CFI information clarified: Table 31,data
modified at Offset 13h. Table 32, data modified at Offsets 20h, 23h, 24h and 25h.
Table 35, Offset addresses modified. DC Characteristics table modified, Program,
Erase Times and Program, Erase Endurance Cycles table modified.
23-May-2002
-09
Document changed to new structure
27-Aug-2002
9.1
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot.
(revision version 09 equals 9.0).
Document status changed from Preliminary Data to Datasheet.
Minimum VDD and VDDQ supply voltages for 85ns speed class changed to 1.8V in
Table16, Operating and AC Measurement Conditions.
68/70
Revision Details
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
Date
Version
Revision Details
24-Feb-2003
9.2
Revision History moved to end of document.
90ns Speed Class added. Bank Erase Command moved to Factory Program
Commands section. Bank Erase cycles limited to 100 per Block.
WAIT signal modified in Figure 7, Wait Configuration Example. WAIT behavior
modified. Burst sequence in wrapped configuration and Burst sequence start
specified in Synchronous Burst Read Mode paragraph. Erase replaced by Block
Erase in Tables 11 and 12, Dual Operations allowed in Other Bank and in Same
Bank, respectively. Latch signal corrected in Figure 11, Asynchronous Page Read
AC Waveforms. Daisy Chain added.
06-Jun-2003
9.3
VDD and VDDQ minimum values changed for 90ns speed class in Table 16, Operating
and AC Measurement Conditions. Minor text changes.
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M58CR064C, M58CR064D, M58CR064P, M58CR064Q
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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