SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995 PERIPHERAL DRIVERS FOR HIGH-VOLTAGE, HIGH-CURRENT DRIVER APPLICATIONS • • • • 1A 1B 1Y GND LOGIC SN55461 AND FK, JG SN55462 NAND FK, JG SN55463 OR FK, JG SN75461 AND D, P SN75462 NAND D, P SN75463 OR D, P 8 2 7 3 6 4 5 VCC 2B 2A 2Y SN55461, SN55462, SN55463 . . . FK PACKAGE (TOP VIEW) NC 1B NC 1Y NC SUMMARY OF SERIES 55461/75461 DEVICE 1 NC 1A NC VCC NC • • Characterized for Use to 300 mA High-Voltage Outputs No Output Latch-Up at 30 V (After Conducting 300 mA) Medium-Speed Switching Circuit Flexibility for Varied Applications and Choice of Logic Function TTL-Compatible Diode-Clamped Inputs Standard Supply Voltages Plastic DIP (P) With Copper Lead Frame for Cooler Operation and Improved Reliability Package Options Include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC 2B NC 2A NC NC GND NC 2Y NC • • • SN55461, SN55462, SN55463 . . . JG PACKAGE SN75461, SN75462, SN75463 . . . D OR P PACKAGE (TOP VIEW) PACKAGES NC − No internal connection description These dual peripheral drivers are functionally interchangeable with SN55451B through SN55453B and SN75451B through SN75453B peripheral drivers, but are designed for use in systems that require higher breakdown voltages than those devices can provide at the expense of slightly slower switching speeds. Typical applications include logic buffers, power drivers, relay drivers, lamp drivers, MOS drivers, line drivers, and memory drivers. The SN55461/SN75461, SN55462/SN75462, and SN55463/SN75463 are dual peripheral AND, NAND, and OR drivers respectively (assuming positive logic), with the output of the gates internally connected to the bases of the npn output transistors. Series SN55461 drivers are characterized for operation over the full military temperature range of − 55°C to 125°C. Series SN75461 drivers are characterized for operation from 0°C to 70°C. Copyright 1995, Texas Instruments Incorporated ! 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'' %$$!) • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† SN55’ Supply voltage, VCC (see Note 1) SN75’ UNIT 7 7 V Input voltage, VI 5.5 5.5 V Intermitter voltage (see Note 2) 5.5 5.5 V Off-state output voltage, VO 35 35 V Continuous collector or output current (see Note 3) 400 400 mA Peak collector or output current (tw ≤ 10 ms, duty cycle ≤ 50%, see Note 4) 500 500 mA Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA Storage temperature range, Tstg −55 to 125 0 to 70 °C −65 to 150 −65 to 150 °C Case temperature for 60 seconds, TC FK package 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds JG package 300 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D or P package 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network GND unless otherwise specified. 2. This is the voltage between two emitters A and B. 3. This value applies when the base-emitter resistance (RBE) is equal to or less than 500 Ω. 4. Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time interval must fall within the continuous dissipation rating. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C 25 C POWER RATING D 725 mW FK JG P DERATING FACTOR ABOVE TA = 25°C TA = 70 70°C C POWER RATING TA = 125 125°C C POWER RATING 5.8 mW/°C 464 mW − 1375 mW 11.0 mW/°C 880 mW 275 mW 1050 mW 8.4 mW/°C 672 mW 210 mW 1000 mW 8.0 mW/°C 640 mW − recommended operating conditions SN55’ Supply voltage, VCC High-level input voltage, VIH MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 2 Low-level input voltage, VIL 2 0.8 Operating free-air temperature, TA 2 SN75’ −55 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 125 0 UNIT V V 0.8 V 70 °C SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995 logic symbol† 1A 1B 2A 2B logic diagram (positive logic) 1 & 2 3 6 5 7 1Y 1A 1B 2Y 2A 2B † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, JG, and P packages. B Y L L L (on state) L (on state) L H H L L (on state) H H H (off state) 1Y 2 5 6 2Y 7 4 GND schematic (each driver) FUNCTION TABLE (each driver) A 3 1 VCC 4 kΩ 1.6 kΩ 130 Ω Y A positive logic: Y = AB or A + B B 500 Ω 1 kΩ GND Resistor values shown are nominal. electrical characteristics over recommended operating free-air temperature range TEST CONDITIONS† PARAMETER VIK IOH VOL MIN Input clamp voltage VCC = MIN, II = − 12 mA High-level output current VCC = MIN, VOH = 35 V VIH = MIN, Low-level output voltage II IIH Input current at maximum input voltage IIL ICCH Low-level input current High-level input current SN55461 TYP‡ MAX −1.2 MIN SN75461 TYP‡ MAX −1.5 −1.2 300 −1.5 V 100 µA A VCC = MIN, VIL = 0.8 V, IOL = 100 mA 0.25 0.5 0.25 0.4 VCC = MIN, VIL = 0.8 V, IOL = 300 mA 0.5 0.8 0.5 0.7 VCC = MAX, VCC = MAX, VI = 5.5 V VI = 2.4 V VCC = MAX, VCC = MAX, VI = 0.4 V VI = 5 V UNIT V 1 1 mA 40 40 µA −1 −1.6 −1 −1.6 mA 8 11 8 11 mA ICCL Supply current, outputs low VCC = MAX, VI = 0 56 76 56 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. 76 mA Supply current, outputs high switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tTLH tTHL Transition time, low-to-high-level output VOH Propagation delay time, high-to-low-level output IO ≈ 200 mA, RL = 50 Ω,, MIN CL = 15 pF, See Figure 1 Transition time, high-to-low-level output High-level output voltage after switching SN55461 VS = 30 V, See Figure 2 SN75461 • • MAX 30 55 25 40 8 20 10 20 VS −10 IO ≈ 300 mA, POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TYP VS −10 UNIT ns mV 3 SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995 logic symbol† 1A 1B 2A 2B logic diagram (positive logic) 1 & 2 3 6 5 7 1Y 1A 1B 2Y 2A 2B 3 1 2 5 6 4 Y L L H (off state) L H H (off state) H L H (off state) H H L (on state) GND schematic (each driver) FUNCTION TABLE (each driver) B 2Y 7 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, JG, and P packages. A 1Y VCC 1.6 kΩ 1.6 kΩ 4 kΩ 130 Ω Y A positive logic: Y = AB or A + B B 1 kΩ 500 Ω 1 kΩ GND Resistor values shown are nominal. electrical characteristics over recommended operating free-air temperature range TEST CONDITIONS† PARAMETER VIK IOH VOL Input clamp voltage VCC = MIN, II = − 12 mA High-level output current VCC = MIN, VOH = 35 V VIL = 0.8 V, Low-level output voltage II IIH Input current at maximum input voltage IIL ICCH Low-level input current High-level input current MIN SN55462 TYP‡ MAX −1.2 MIN SN75462 TYP‡ MAX −1.5 −1.2 300 −1.5 V 100 µA A VCC = MIN, VIH = MIN, IOL = 100 mA 0.25 0.5 0.25 0.4 VCC = MIN, VIH = MIN, IOL = 300 mA 0.5 0.8 0.5 0.7 VCC = MAX, VCC = MAX, VI = 5.5 V VI = 2.4 V VCC = MAX, VCC = MAX, VI = 0.4 V VI = 0 UNIT V 1 1 40 40 mA µA −1.1 −1.6 −1.1 −1.6 mA 13 17 13 17 mA ICCL Supply current, outputs low VCC = MAX, VI = 5 V 61 76 61 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. 76 mA Supply current, outputs high switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tTLH tTHL Transition time, low-to-high-level output VOH 4 Propagation delay time, high-to-low-level output IO ≈ 200 mA, RL = 50 Ω,, CL = 15 pF, See Figure 1 VS = 30 V, See Figure 2 IO ≈ 300 mA, MIN Transition time, high-to-low-level output High-level output voltage after switching SN55462 SN75462 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • TYP MAX 45 65 30 50 13 25 10 20 VS −10 VS −10 UNIT ns mV SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995 logic symbol† 1A 1B 2A 2B logic diagram (positive logic) 1 ≥1 2 3 6 5 7 1Y 1A 5 6 2A 4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, JG, and P packages. B Y L L (on state) L H H (off state) H L H (off state) H H GND schematic (each driver) FUNCTION TABLE (each driver) L 2Y 7 2B A 1Y 2 1B 2Y 3 1 VCC 4 kΩ 1.6 kΩ 130 Ω 4 kΩ Y A H (off state) positive logic: Y = A + B or A B B 500 Ω 1 kΩ GND Resistor values shown are nominal. electrical characteristics over recommended operating free-air temperature range TEST CONDITIONS† PARAMETER VIK IOH VOL Input clamp voltage VCC = MIN, II = − 12 mA High-level output current VCC = MIN, VOH = 35 V VIH = MIN, Low-level output voltage II IIH Input current at maximum input voltage IIL ICCH Low-level input current High-level input current MIN SN55463 MAX TYP‡ −1.2 MIN SN75463 MAX TYP‡ −1.5 −1.2 300 −1.5 V 100 µA A VCC = MIN, VIL = 0.8 V, IOL = 100 mA 0.25 0.5 0.25 0.4 VCC = MIN, VIL = 0.8 V, IOL = 300 mA 0.5 0.8 0.5 0.7 VCC = MAX, VCC = MAX, VI = 5.5 V VI = 2.4 V VCC = MAX, VCC = MAX, VI = 0.4 V VI = 5 V UNIT V 1 1 mA 40 40 µA −1 −1.6 −1 −1.6 mA 8 11 8 11 mA ICCL Supply current, outputs low VCC = MAX, VI = 0 58 76 58 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. 76 mA Supply current, outputs high switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output tTLH tTHL Transition time, low-to-high-level output VOH Propagation delay time, high-to-low-level output IO ≈ 200 mA, RL = 50 Ω,, CL = 15 pF, See Figure 1 VS = 30 V, See Figure 2 IO ≈ 300 mA, MIN Transition time, high-to-low-level output High-level output voltage after switching SN55463 SN75463 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • TYP MAX 30 55 25 40 8 25 10 25 VS −10 VS −10 UNIT ns mV 5 SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995 PARAMETER MEASUREMENT INFORMATION ≤ 10 ns ≤ 5 ns Input 2.4 V 10 V RL = 50 Ω ’461 ’462 Output Pulse Generator (see Note A) 90% 1.5 V Input ’461 ’463 Circuit Under Test (see Note B) 10% 10% 0V 0.5 µs ≤ 5 ns Input ’462 CL = 15 pF (see Note B) 90% 1.5 V ≤ 10 ns 3V 90% 1.5 V 10% 10% tPHL GND ’463 tPLH 90% SUB 3V 90% 1.5 V 90% 50% 10% Output 0V VOH 50% 10% VOL 0.4 V tTLH tTHL VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω. B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms for Switching Times ≤ 5 ns VS = 30 V Input 2.4 V ’461 ’462 Input ’461 ’463 2 mH 5V 90% 90% 1.5 V Circuit Under Test (see Note B) 10% CL = 15 pF (see Note B) 10% 0V 40 µs ≤ 5 ns 90% Input ’462 3V 1.5 V 65 Ω 1N3064 Output Pulse Generator (see Note A) ≤ 10 ns 1.5 V ≤ 10 ns 3V 90% 1.5 V 10% 10% 0V VOH ’463 GND SUB Output VOL 0.4 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: PRR ≤ 12.5 kHz, ZO = 50 Ω . B. CL includes probe and jig capacitance. Figure 2. Test Circuit and Voltage Waveforms for Latch-Up Test 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty 1 Eco Plan (2) Lead/ Ball Finish A42 TBD Call TI ACTIVE CDIP JG 8 JM38510/12909BPA OBSOLETE CDIP JG 8 M38510/12908BPA ACTIVE CDIP JG 8 TBD A42 SN55461JG OBSOLETE CDIP JG 8 TBD Call TI Call TI SN55462JG OBSOLETE CDIP JG 8 TBD Call TI Call TI SN55463JG OBSOLETE CDIP JG 8 TBD Call TI Call TI SN75461D OBSOLETE SOIC D 8 TBD Call TI Call TI Call TI Call TI TBD N / A for Pkg Type Call TI N / A for Pkg Type SN75461P OBSOLETE PDIP P 8 SN75462D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75462DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75462DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75462DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75462DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75462DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75462P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75462PE4 ACTIVE PDIP P 8 SN75463D OBSOLETE SOIC D 8 TBD Call TI Call TI SN75463DR OBSOLETE SOIC D 8 TBD Call TI Call TI SN75463P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75463PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SNJ55461FK OBSOLETE LCCC FK 20 SNJ55461JG OBSOLETE CDIP JG 8 SNJ55462FK ACTIVE LCCC FK 20 1 TBD SNJ55462JG ACTIVE CDIP JG 8 1 TBD A42 SNJ55463JG OBSOLETE CDIP JG 8 TBD Call TI TBD TBD Addendum-Page 1 (3) Samples (Requires Login) JM38510/12908BPA 1 TBD MSL Peak Temp Call TI Call TI Call TI Call TI POST-PLATE N / A for Pkg Type N / A for Pkg Type Call TI PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2012 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN55461, SN55462, SN55463, SN75461, SN75462, SN75463 : • Catalog: SN75461, SN75462, SN75463 • Military: SN55461, SN55462, SN55463 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75462DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.4 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75462DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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