STMICROELECTRONICS M48Z58Y

M48Z58
M48Z58Y
5V, 64Kbit (8Kbit x 8) ZEROPOWER ® SRAM
Features
■
Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■
READ cycle time equals WRITE cycle time
■
Automatic power-fail chip deselect and WRITE
protection
■
28
1
WRITE protect voltages:
(VPFD = Power-fail deselect voltage)
– M48Z58: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V
– M48Z58Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
■
Self-contained battery in the CAPHAT™ DIP
package
■
Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately)
■
SOIC package provides direct connection for a
SNAPHAT top which contains the battery
■
Pin and function compatible with JEDEC
standard 8Kbit x 8 SRAMs
■
RoHS compliant
– Lead-free second level interconnect
November 2007
PCDIP28 (PC)
Battery CAPHAT
SNAPHAT (SH)
battery
28
1
SOH28 (MH)
Rev 8
1/23
www.st.com
1
Contents
M48Z58, M48Z58Y
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
M48Z58, M48Z58Y
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PMDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data. . . . . . . . . . . . . . . . 17
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 18
SH – 4-pin SNAPHAT housing for 48mAh battery, package mechanical data . . . . . . . . . . 19
SH – 4-pin SNAPHAT housing for 120mAh battery, pack. mech. data . . . . . . . . . . . . . . . 20
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
List of figures
M48Z58, M48Z58Y
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
4/23
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 17
SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 18
SH – 4-pin SNAPHAT housing for 48mAh battery, package outline. . . . . . . . . . . . . . . . . . 19
SH –4-pin SNAPHAT housing for 120mAh battery, package outline . . . . . . . . . . . . . . . . . 20
M48Z58, M48Z58Y
1
Description
Description
The M48Z58/Y ZEROPOWER® RAM is an 8Kbit x 8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is
available in two special packages to provide a highly integrated battery backed-up memory
solution.
The M48Z58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8
SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the M48Z58/Y silicon with a long life lithium
button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing containing the battery. The unique design
allows the SNAPHAT battery package to be mounted on top of the SOIC package after the
completion of the surface mount process. Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape
& Reel form.
For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is “M4Z28BR00SH1” (see Table 16 on page 21).
Figure 1.
Logic diagram
VCC
13
8
A0-A12
W
DQ0-DQ7
M48Z58
M48Z58Y
E
G
VSS
AI01176B
5/23
Description
M48Z58, M48Z58Y
Table 1.
Signal names
A0-A12
Address inputs
DQ0-DQ7
Figure 2.
Data inputs / outputs
E
Chip enable input
G
Output enable input
W
WRITE enable input
VCC
Supply voltage
VSS
Ground
NC
Not connected internally
DIP connections
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
M48Z58 22
8 M48Z58Y 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01177B
Figure 3.
SOIC connections
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7
22
M48Z58Y
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AI01178B
6/23
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
M48Z58, M48Z58Y
Figure 4.
Description
Block diagram
A0-A12
LITHIUM
CELL
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8K x 8
SRAM ARRAY
DQ0-DQ7
E
VPFD
W
G
VCC
VSS
AI01394
7/23
Operating modes
2
M48Z58, M48Z58Y
Operating modes
The M48Z58/Y also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below battery
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
Table 2.
Operating modes
Mode
VCC
Deselect
WRITE
READ
4.75 to 5.5V
or
4.5 to 5.5V
READ
Deselect
VSO to VPFD
Deselect
(min)(1)
≤ VSO(1)(1)
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery back-up
mode
1. See Table 10 on page 16 for details.
Note:
X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2.1
Read mode
The M48Z58/Y is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)
is low. Thus, the unique address specified by the 13 Address Inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within
Address Access time (tAVQV) after the last address input signal is stable, providing that the E
and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable
Access time (tGLQV).
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
8/23
M48Z58, M48Z58Y
Figure 5.
Operating modes
Read mode AC waveforms
tAVAV
VALID
A0-A12
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01385
Note:
WRITE Enable (W) = High.
Table 3.
Read mode AC characteristics
M48Z58/Y
Parameter(1)
Symbol
Unit
Min
Max
tAVAV
READ cycle time
tAVQV
Address valid to output valid
70
ns
tELQV
Chip enable low to output valid
70
ns
tGLQV
Output enable low to output valid
35
ns
tELQX(2)
tGLQX(2)
tEHQZ(2)
tGHQZ(2)
tAXQX
70
ns
Chip enable low to output transition
5
ns
Output enable low to output transition
5
ns
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
25
ns
25
ns
10
ns
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. CL = 5pF (see Figure 9 on page 14).
2.2
Write mode
The M48Z58/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable
prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs tWLQZ after W falls.
9/23
Operating modes
Figure 6.
M48Z58, M48Z58Y
Write enable controlled, write mode AC waveforms
tAVAV
VALID
A0-A12
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01386
Figure 7.
Chip enable controlled, write mode AC waveforms
tAVAV
VALID
A0-A12
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
10/23
M48Z58, M48Z58Y
Table 4.
Operating modes
Write mode AC characteristics
M48Z58/Y
Parameter(1)
Symbol
Unit
Min
Max
tAVAV
WRITE cycle time
70
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
50
ns
tELEH
Chip enable low to chip enable high
55
ns
tWHAX
WRITE enable high to address transition
0
ns
tEHAX
Chip enable high to address transition
0
ns
tDVWH
Input valid to WRITE enable high
30
ns
tDVEH
Input valid to chip enable high
30
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ(2)(3)
WRITE enable low to output Hi-Z
25
ns
tAVWH
Address valid to WRITE enable high
60
ns
tAVEH
Address valid to chip enable high
60
ns
WRITE enable high to output transition
5
ns
tWHQX(2)(3)
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. CL = 5pF (see Figure 9 on page 14).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z58/Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48Z58/Y may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data. The internal button cell will maintain data in the M48Z58/Y for an
accumulated period of at least 10 years when VCC is less than VSO.
As system power returns and VCC rises above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Normal RAM operation can resume trec after VCC
exceeds VPFD (max).
For more information on Battery Storage Life refer to the Application Note AN1012.
11/23
Operating modes
2.4
M48Z58, M48Z58Y
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 8)
is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, ST recommends connecting a schottky
diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817
is recommended for through hole and MBRS120T3 is recommended for surface mount).
Figure 8.
Supply voltage protection
VCC
VCC
0.1μF
DEVICE
VSS
AI02169
12/23
M48Z58, M48Z58Y
3
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 5.
Absolute maximum ratings
Symbol
TA
Parameter
Value
Unit
0 to 70
°C
top
–40 to 85
°C
CAPHAT DIP
–40 to 85
°C
SOIC
–55 to 125
°C
260
°C
Ambient operating temperature
SNAPHAT®
TSTG
TSLD(1)(2)
Storage temperature (VCC off, oscillator off)
®
Lead solder temperature for 10 seconds
VIO
Input or output voltages
–0.3 to 7.0
V
VCC
Supply voltage
–0.3 to 7.0
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for
longer than 30 seconds).
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed
245°C for greater than 30 seconds).
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the battery back-up
mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
13/23
DC and AC parameters
4
M48Z58, M48Z58Y
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in Table 6:
Operating and AC measurement conditions. Designers should check that the operating
conditions in their projects match the measurement conditions when using the quoted
parameters.
Table 6.
Operating and AC measurement conditions
Parameter
M48Z58
M48Z58Y
Unit
4.75 to 5.5V
4.5 to 5.5
V
0 to 70
0 to 70
°C
Load capacitance (CL)
100
100
pF
Input rise and fall times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply voltage (VCC)
Ambient operating temperature (TA)
Input pulse voltages
Input and output timing ref. voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC measurement load circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL = 100pF or 5pF
CL includes JIG capacitance
Table 7.
Capacitance
Parameter(1)(2)
Symbol
CIN
CIO
(3)
AI01030
Min
Max
Unit
Input capacitance
10
pF
Input / output capacitance
10
pF
1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
14/23
M48Z58, M48Z58Y
Table 8.
DC and AC parameters
DC characteristics
Symbol
ILI
Test condition(1)
Parameter
Input leakage current
ILO(2)
Output leakage current
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Outputs open
50
mA
E = VIH
3
mA
E = VCC – 0.2V
3
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.8
V
VIH
Input high voltage
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1mA
0.4
V
VOH
Output high voltage
IOH = –1mA
2.4
V
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. Outputs deselected.
Figure 10. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tDR
tPD
INPUTS
tRB
RECOGNIZED
trec
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
Table 9.
Symbol
tPD
Power down/up AC characteristics
Parameter(1)
Max
Unit
0
µs
VPFD (max) to VPFD (min) VCC fall time
300
µs
VPFD (min) to VSS VCC fall time
10
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
trec
VPFD (max) to inputs recognized
40
tF
(2)
tFB
(3)
E or W at VIH before power down
Min
200
ms
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
15/23
DC and AC parameters
Table 10.
M48Z58, M48Z58Y
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
Min
Typ
Max
Unit
M48Z58
4.5
4.6
4.75
V
M48Z58Y
4.2
4.35
4.5
V
VPFD
Power-fail deselect voltage
VSO
Battery back-up switchover voltage
tDR(3)
Expected data retention time
3.0
10
V
YEARS
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
3. At 25°C, VCC = 0V.
16/23
M48Z58, M48Z58Y
5
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 11. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline
A2
A
A1
B1
B
L
C
e1
eA
e3
D
N
E
1
Note:
PCDIP
Drawing is not to scale.
Table 11.
PMDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data
mm
inches
Symbol
Typ
Min
Max
A
8.89
A1
A2
Typ
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
17/23
Package mechanical data
M48Z58, M48Z58Y
Figure 12. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
Table 12.
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech.
data
mm
inches
Symbol
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
a
0°
8°
0°
8°
N
28
e
CP
18/23
Max
1.27
0.050
28
0.10
0.004
M48Z58, M48Z58Y
Package mechanical data
Figure 13. SH – 4-pin SNAPHAT housing for 48mAh battery, package outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHZP-A
Note:
Drawing is not to scale.
Table 13.
SH – 4-pin SNAPHAT housing for 48mAh battery, package mechanical data
mm
inches
Symbol
Typ
Min
A
Max
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
19/23
Package mechanical data
M48Z58, M48Z58Y
Figure 14. SH –4-pin SNAPHAT housing for 120mAh battery, package outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHZP-A
Note:
Drawing is not to scale.
Table 14.
SH – 4-pin SNAPHAT housing for 120mAh battery, pack. mech. data
mm
inches
Symb
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
A3
20/23
Max
0.38
0.015
M48Z58, M48Z58Y
6
Part numbering
Part numbering
Table 15.
Ordering information scheme
Example:
M48Z
58Y
–70
MH
1
E
Device type
M48Z
Supply voltage and write protect voltage
58(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V
58Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed
–70 = 70ns (for M48Z58/Y)
Package
PC = PCDIP28
MH(2) = SOH28
Temperature range
1 = 0 to 70°C
Shipping method
For SOH28:
E = ECOPACK package, tubes
F = ECOPACK package, tape & reel
For PCDIP28:
blank = ECOPACK package, tubes
1. The M48Z58 part is offered with the PCDIP28 (ie., CAPHAT™) package only.
2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under
the part number “M4Zxx-BR00SH1” in plastic tubes (see Table 16).
Caution:
Do not place the SNAPHAT battery package “M4Zxx-BR00SH1” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 16.
SNAPHAT battery table
Part number
Description
Package
M4Z28-BR00SH1
Lithium Battery (48mAh) SNAPHAT
SH
M4Z32-BR00SH1
Lithium Battery (120mAh) SNAPHAT
SH
21/23
Revision history
7
M48Z58, M48Z58Y
Revision history
Table 17.
22/23
Document revision history
Date
Revision
Changes
March 1999
1.0
First issue
10-Feb-2000
1.1
2-socket SOH and 2-pin SH packages removed
22-Feb-2000
1.2
Data retention mode paragraph changed
14-Sep-2001
2.0
Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10)
29-May-2002
2.1
Modify reflow time and temperature footnotes (Table 5)
16-Sep-2002
2.2
Remove footnote from ordering information (Table 15)
02-Apr-2003
3.0
v2.2 template applied; test condition updated (Table 10)
23-Mar-2004
4.0
Reformatted; updated lead-free information (Table 5, 15)
23-Nov-2004
5.0
Remove references to industrial temperature grade (Table 3, 4, 5, 6, 8,
9, 10, 15)
09-Jun-2005
6.0
Removal of SNAPHAT, industrial temperature sales types (Table 3, 4,
5, 6, 7, 8, 10, 15)
14-Dec-2005
7.0
Updated Lead-free text (Table 15)
06-Nov-2007
8.0
Reformatted; added lead-free second level interconnect information to
cover page and Section 5: Package mechanical data; updated Table 5,
15, 16.
M48Z58, M48Z58Y
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