MITSUBISHI LSIs 1998.11.30 Ver.B M5M54R16AJ,ATP-10,-12,-15 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R16A is a family of 262144-word by 16-bit PIN CONFIGURATION (TOP VIEW) static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. ADDRESS INPUTS They include a power down feature as well. In write and read cycles, the lower and upper bytes are able CHIP SELECT INPUT to be controled either togethe or separately by LB DATA INPUTS/ OUTPUTS and UB. FEATURES •Fast access time M5M54R16AJ,ATP-10 ... 10ns(max) M5M54R16AJ,ATP-12 ... 12ns(max) M5M54R16AJ,ATP-15 ... 15ns(max) •Single +3.3V power supply •Fully static operation : No clocks, No refresh •Common data I/O •Easy memory expansion by S •Three-state outputs : OR-tie capability •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs •Separate control of lower and upper bytes by LB and UB APPLICATION (3.3V) (0V) A0 A1 A2 A3 A4 S DQ1 DQ2 DQ3 DQ4 VCC GND DQ5 DATA DQ6 INPUTS/ DQ7 OUTPUTS DQ8 WRITE CONTROL INPUT W A5 A6 ADDRESS INPUTS A7 A8 A9 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 A17 ADDRESS A16 INPUTS A15 OUTPUT OE ENABLE INPUT BYTE UB CONTROL LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V) 12 33 VCC 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 DQ12 DQ11 DQ10 DQ9 N.C A14 A13 A12 A11 A10 Outline (3.3V) DATA INPUTS/ OUTPUTS ADDRESS INPUTS 44P0K PACKAGE M5M54R16AJ .......... 44pin 400mil SOJ M5M54R16ATP .......... 44pin 400mil TSOP(II) High-speed memory system FUNCTION The operation mode of the M5M54R16A is determined by a combination of the device control inputs S, W, OE, LB, and UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with low level LB and/or low level UB and low level S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of W, LB, UB or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while LB and/or UB and S are in an active state. (LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upperByte are in a non-selectable mode. When setting LB and UB at a high level or S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by LB, UB and S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION TABLE Read cycle All Bytes DQ1~8 D OUT Read cycle Upper Bytes High-impedance D OUT L Read cycle Lower Bytes Write cycle All Bytes L Write cycle Upper Bytes L H Write cycle Lower Bytes H X X X H H X X X S L L W H H OE L L LB L H UB L L L H L L H L L X L L L X H L L X L H L X H X Mode DQ9~16 D OUT D OUT Icc Active Active Active D IN High-impedance D IN High-impedance D IN Active D IN High-impedance Active Output disable High-impedance High-impedance Active Non selection High-impedance High-impedance Stand by Active BLOCK DIAGRAM ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1 2 3 4 5 18 MEMORY ARRAY 1024 ROWS 4096 COLUMNS 7 8 9 10 13 14 15 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 29 30 31 32 35 36 37 38 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 11 33 VCC DATA INPUTS/ OUTPUTS 19 20 21 22 CHIP SELECT INPUT S 6 WRITE CONTROL INPUT W 17 OUTPUT ENABLE INPUT OE 41 UPPER BYTE CONTROL INPUT UB 40 LOWER BYTE CONTROL INPUT LB 39 COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS DATA INPUTS/ OUTPUTS COLUMN INPUT BUFFERS 12 34 (3.3V) GND (0V) 23 24 25 26 27 42 43 44 A10 A11A12 A13 A14 A15A16A17 ADDRESS INPUTS MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS V cc Symbol Parameter Supply voltage VI Input voltage VO Output voltage Power dissipation Operating temperature Pd T opr Tstg(bias) Storage temperature(bias) Tstg Conditions Ratings With respect to GND - 2.0*~ 4.6 - 2.0*~ Vcc+0.5 - 2.0*~ Vcc 1000 Ta=25°C 0 ~ 70 Storage temperature Unit V V V mW - 10 ~ 85 °C °C - 65 ~ 150 °C *Pulse width ≤3ns, In case of DC: - 0.5V DC ELECTRICAL CHARACTERISTICS Symbol +10% -5% ,unless (Ta=0~70°C, Vcc=3.3V Parameter VIH VIL VOH VOL II High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current IOZ Output current in off-state otherwise noted) Condition Min 2.0 IOH = - 4mA IOL= 8mA V I = 0 ~ Vcc VI (S)= VIH VO= 0 ~ Vcc Limits Typ Max Vcc+0.3 0.8 0.4 2 V V V V uA 2 uA 2.4 I CC1 Active supply current (TTL level) VI (S)= VIL other inputs VIH or VIL Output-open(duty 100%) I CC2 Stand-by supply current (TTL level) VI (S)= VIH I CC3 Stand-by current (MOS level) VI (S)= Vcc - 0.2V other inputs VI≤0.2V or VI≥Vcc - 0.2V AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC Unit 260 250 230 120 90 70 60 40 mA mA 10 mA Max 7 8 Unit Note 1: Direction for current flowing into an IC is positive (no mark). CAPACITANCE Symbol (Ta=0~70°C , Vcc=3.3V +10% -5% ,unless otherwise noted) Parameter Test Condition Min Limit Typ CI Input capacitance VI =GND,Vi =25mVrms,f=1MHz CO Output capacitance Vo =GND,Vo =25mVrms,f=1MHz Note 2: CI,CO are periodically sampled and are not 100% tested. pF pF AC ELECTRICAL CHARACTERISTICS (Ta= 0~70 °C ,VCC=3.3V +10% -5% ,unless otherwise noted) (1) MEASUREMENT CONDITION Input pulse levels ................................... VIH=3.0V,VIL=0.0V Input rise and fall time ................................................... 3ns Input timing reference levels ...................... VIH=1.5V,VIL=1.5V Output timing reference levels ................ VOH=1.5V, VOL=1.5V Output loads ....................................................... Fig1 ,Fig2 OUTPUT 5.0V Z0=50Ω 480Ω DQ RL=50Ω VL=1.5V Fig.1 Output load MITSUBISHI ELECTRIC DQ 255Ω 5pF Including ( scope and JIG ) Fig.2 Output load for t en, t dis 3 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM READ CYCLE Limits Symbol tCR ta(A) ta(S) ta(OE) ta(B) tdis(S) tdis(OE) tdis(B) ten(S) ten(OE) ten(B) tv(A) tPU tPD Parameter Read cycle time M5M54R16AJ,ATP-10 M5M54R16AJ,ATP-12M5M54R16AJ,ATP-15 Unit Min 10 Address access time Chip select access time Output enable access time LB,UB access time Output disable time after S high Output disable time after OE high Output disable time after LB,UB high Output enable time after S low Output enable time after OE low Output enable time after LB,UB low Data valid time after address change Power-up time after chip selection Power-down time after chip selection 0 0 0 2 0 0 2 0 Max 10 10 5 5 5 5 5 Min 12 Max 12 12 6 6 6 6 6 0 0 0 3 1 1 3 0 10 Min 15 0 0 0 3 1 1 3 0 12 Max 15 15 7 7 7 7 7 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write cycle Limits Symbol Parameter M5M54R16AJ,ATP-10 M5M54R16AJ,ATP-12 M5M54R16AJ,ATP-15 Unit Min tCW tw(W) tw(W) tsu(B) tsu(A)1 tsu(A)2 tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) ten(B) tsu(A-WH) tsu(A-SH) tsu(A-BH) Write cycle time Write pulse width (OE low) Write pulse width(OE high) LB,UB setup time Address setup time(W) Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low Output enable time after LB,UB low Address to W High Address to S High Address to LB,UB High Max 10 10 8 Max 12 10 10 0 0 8 0 0 8 5 0 1 0 0 0 0 0 8 8 8 Min 12 5 5 Min 15 10 6 15 10 10 0 0 10 7 0 1 0 0 0 0 0 0 1 0 0 0 0 0 10 10 10 6 6 10 10 10 Max 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI ELECTRIC 4 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (4)TIMING DIAGRAMS Read cycle 1 A 0~17 t CR VIH VIL ta(A) tv(A) tv(A) DQ1~16 VOH PREVIOUS DATA VALID VOL W=H LB=L S=L UB=L UNKNOWN DATA VALID OE=L Read cycle 2 (Note 3) t CR VIH S VIL tdis(S) ta(S) (Note 4) ten(S) DQ1~16 (Note 4) VOH UNKNOWN DATA VALID VOL tPU ICC1 Icc tPD 50% ICC2 W=H 50% UB=L OE=L LB=L Note 3. Addresses valid prior to or coincident with S transition low. 4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2. Read cycle 3 (Note 5) t CR VIH OE VIL ta(OE) (Note 4) DQ1~16 VOH tdis(OE) (Note 4) ten(OE) UNKNOWN DATA VALID VOL W=H UB=L S=L LB=L Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE)) MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Read cycle 4 (Note 6) UB,LB t CR VIH VIL tdis(B) ta(B) (Note 4) DQ1~16 (Note 4) ten(B) VOH UNKNOWN DATA VALID VOL W=H OE=L S=L Note 6. Addresses , S and OE valid prior to LB,UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)). Write cycle (W control mode) t CW A 0~17 VIH VIL S VIH VIL tsu(S) (Note 7) (Note 7) tsu(A-WH) OE VIH VIL tsu(A) W tw(W) trec(W) VIH VIL tsu(B) LB,UB VIH VIL (Note 7) (Note 7) tsu(D) th(D) DQ1~16 (Input Data) VIH VIL DATA STABLE tdis(W) (Note 4) ten(OE) ten(W) tdis(OE) DQ1~16 (Output Data) VOH VOL (Note 4) Hi-Z Note 7: Hatching indicates the state is don't care. 8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 9: ten,tdis are periodically sampled and are not 100% tested. MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Write cycle(S control) t CW A 0~17 VIH VIL tsu(A) S VIH VIL W VIH VIL tsu(A-SH) tsu(S) trec(W) tw(W) (Note 6) (Note 6) tsu(B) LB,UB VIH VIL (Note 6) (Note 6) tsu(D) DQ1~16 (Input Data) VIH VIL DATA STABLE (Note 4) DQ1~16 (Output Data) VOH VOL th(D) ten(S) tdis(W) ten(B) (Note 4) Hi-Z (Note 8) Write cycle(LB,UB control) t CW A 0~17 VIH VIL tsu(S) S VIH VIL (Note 6) (Note 6) tw(W) W VIH VIL (Note 6) tsu(A) LB,UB tsu(A-BH) tsu(B) (Note 6) trec(W) VIH VIL tsu(D) DQ1~16 (Input Data) VIH VIL DATA STABLE tdis(W) (Note 4) DQ1~16 (Output Data) VOH VOL th(D) ten(B) (Note 4) ten(S) Hi-Z (Note 8) MITSUBISHI ELECTRIC 7