STMICROELECTRONICS M74HC40102F1R

M54/74HC40102
M54/74HC40103
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
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.
.
.
.
.
.
.
HIGH SPEED
fMAX = 40 MHz (TYP.) at VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
PIN AND FUNCTION COMPATIBLE WITH
40102B/40103B
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXXXF1R M74HCXXXXXM1R
M74HCXXXXXB1R M74HCXXXXX C1R
DESCRIPTION
PIN CONNECTIONS (top view)
The M54/74HC40102/40103 are high speed CMOS
8-STAGE PRESETTABLE
SYNCHRONOUS
DOWN COUNTERS fabricated with silicon gate
2
C MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.
The HC40102, and HC40103 consist of an 8-stage
synchronous down counter with a single output
which is active when the internal count is zero. The
HC40102 is configured as two cascaded 4-bit BCD
counters, and the HC40103 contains a single 8-bit
binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter
to its maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic. In normal operation, the
counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETECT
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the J
input is clocked into the counter on the next positive
clock transition regardless of the state of the CI/CE
input.
March 1993
NC =
No Internal
Connection
1/14
M54/M74HC40102/40103
DESCRIPTION (Continued)
When the ASYNCHRONOUS PRESET-ENABLE
(APE) input is low, data at the J inputs is asynchronously forced into the counter regardless of the state
of the SPE, CI/CE, or CLOCK inputs. J Inputs J0-J7
represent two 4-bit BCD words for the HC40102 and
a single 8-bit binary word for the HC40103. When
the CLEAR (CLR input is low, the counter is asynchronously cleared to its maximum count (9910 for
the HC40102 and 25510 for the HC40103 regardless of the state of any other input. The precedence
relationship between control input is indicated in the
truth table. If all control inputs are high at the time of
zero count, the counters will jump to the maximum
count, giving a counting sequence of 100 pr 256
clock pulses long. The HC40102 and HC40103 may
be cascaded using the CI/CE input and the CO/ZD
output, in either a synchronous or ripple mode. All
inputs are equipped with protection circuits against
static discharge and transient excess voltage.
TRUTH TABLE
CONTROL INPUTS
MODE
FUNCTIONAL DESCRIPTION
CLEAR
APE
SPE
CI/CE
H
H
H
H
COUNT INHIBIT
H
H
H
H
H
L
L
X
REGULAR COUNT
SYNCHRONOUS PRESET
H
L
X
X
ASYNCRONOUS PRESET
DATA PF PI TERMINAL IS
ASYNCHRONOUSLY PRESET TO CLOCK
L
X
X
X
CLEAR
COUNTER IS SET TO MAXIMUM COUNT
EVEN IF CLOCK IS GIVEN, NO COUNT IS
MADE
DOWN COUNT AT RISING EDGE OF CLOCK
DATA OF PI TERMINAL IS PRESET AT
RISING EDGE OF CLOCK
X: DON’T CARE - MAXIMUM COUNT: ”99” FOR HC40102 AND ”255”: FOR HC40103
LOGIC DIAGRAM (HC40102)
2/14
M54/M74HC40102/40103
LOGIC DIAGRAM (HC40103)
TIMING CHART
3/14
M54/M74HC40102/40103
PIN DESCRIPTION
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK
2
CLEAR
CLock Input (LOW to
HIGH edge triggered)
Asynchronous Master
Reset Input (Active LOW)
Terminal Enable Input
3
CI/CE
4, 5, 6, 7, 10,
11, 12, 13
J0 to J9
9
APE
Asynchronous Preset
Enable Input (Active LOW)
14
CO/ZD
15
SPE
Terminal Count Output
(Active LOW)
Synchronous Preset
Enable Input (Active LOW)
8
GND
Ground (0V)
16
VCC
Positive Supply Voltage
Jam Inputs
IEC LOGIC SYMBOLS
HC40102
HC40103
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
VI
Supply Voltage
DC Input Voltage
-0.5 to +7
-0.5 to VCC + 0.5
V
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
IOK
DC Input Diode Current
DC Output Diode Current
± 20
± 20
mA
mA
IO
DC Output Source Sink Current Per Output Pin
± 25
mA
ICC or IGND
DC VCC or Ground Current
PD
Power Dissipation
Tstg
TL
Storage Temperature
Lead Temperature (10 sec)
± 50
mA
500 (*)
mW
-65 to +150
300
o
o
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
4/14
M54/M74HC40102/40103
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VI
Supply Voltage
Input Voltage
VO
Output Voltage
Top
Operating Temperature: M54HC Series
M74HC Series
Input Rise and Fall Time
tr, tf
Value
Unit
2 to 6
0 to VCC
V
V
0 to VCC
V
o
-55 to +125
-40 to +85
0 to 1000
VCC = 2 V
VCC = 4.5 V
0 to 500
VCC = 6 V
0 to 400
C
C
ns
o
DC SPECIFICATIONS
Test Conditions
Symbol
VIH
V IL
V OH
VOL
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level
Output Voltage
Low Level Output
Voltage
VCC
(V)
2.0
Min.
1.5
4.5
3.15
6.0
2.0
4.2
6.0
2.0
ICC
Quiescent Supply
Current
Max.
-40 to 85 oC -55 to 125 oC
74HC
54HC
Min.
1.5
Max.
3.15
Min.
1.5
4.2
4.2
0.5
0.5
1.35
1.35
1.35
1.8
2.0
1.9
1.9
4.5
4.4
4.4
6.0
4.5
5.9
4.18
6.0
4.31
5.9
4.13
5.9
4.10
6.0
IO=-5.2 mA
5.68
5.8
5.63
5.60
6.0
6.0
V
1.8
1.9
4.4
2.0
4.5
V
0.5
1.8
Unit
Max.
3.15
VI =
IO=-20 µA
VIH
or
V IL IO=-4.0 mA
4.5
4.5
6.0
Input Leakage
Current
Typ.
4.5
6.0
II
Value
TA = 25 oC
54HC and 74HC
V
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.0
0.1
0.1
0.1
0.17
0.18
0.26
0.26
0.33
0.33
0.40
0.40
VI = VCC or GND
±0.1
±1
±1
µA
VI = VCC or GND
4
40
80
µA
VI =
IO= 20 µA
VIH
or
V IL IO= 4.0 mA
IO= 5.2 mA
V
5/14
M54/M74HC40102/40103
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)
Test Conditions
Value
Symbol
Parameter
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
-40 to 85 oC -55 to 125 oC
74HC
54HC
Min. Max. Min. Max.
tTLH
tTHL
Output Transition
Time
2.0
30
75
95
110
4.5
6.0
8
7
15
13
19
16
22
19
tPLH
tPHL
Propagation
Delay Time
(CK - CO/ZD)
2.0
96
185
230
280
4.5
24
37
46
56
tPLH
tPHL
Propagation
Delay Time
(APE - CO/ZD)
tPLH
tPHL
Propagation
Delay Time
(CL - CO/ZD)
tPLH
tPHL
Propagation
Delay Time
(CI/CE - CO/ZD)
fMAX
Propagation
Delay Time
6.0
20
31
39
47
2.0
116
225
280
340
4.5
6.0
29
25
45
38
56
48
68
57
2.0
104
200
250
300
4.5
6.0
26
22
40
34
50
43
60
51
2.0
48
95
120
145
4.5
6.0
12
10
19
16
24
20
29
24
2.0
4
8
3
2.6
4.5
6.0
20
24
32
38
16
19
13
15
CIN
Input Capacitance
5
CPD (*)
Power Dissipation
Capacitance
60
10
10
Unit
ns
ns
ns
ns
ns
pF
10
pF
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC
TEST CIRCUIT ICC (Opr.)
INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST.
6/14
M54/M74HC40102/40103
FUNCTIONAL DESCRIPTION
The HC40102 and HC40103 are 8-stage presettable synchronous down counters. Carry Out/Zero
Detect (CO/ZD) is output at the ”L” level for the
period of 1 bit when the readout becomes ”0”. The
HC40102 adopts binary coded decimal notation,
making setting up to 99 counts possible. While the
HC40103 adopts 8-bit binary counter and can set up
to 255 counts.
COUNT OPERATION
At the ”H” level of control input of CLEAR, SPE and
APE, the counter carriers out down count operation
one by one at the rise of pulse given to CLOCK input.
Count operation can be inhibited by setting Carry
Input/Clock Enable CI/CE to the ”H” level.
CO/ZD is output at the ”L” level when the readout
becomes ”0” but is not output even if the readout
becomes ”0” when CI/CE is at the ”H” level, thus
maintaining the ”H” level.
Synchronous cascade operation can be carried out
by using CI/CE input and CO/ZD output.
The contents of count jump to maximum count (99
for the HC40102 and 225 for the HC40103) if clock
is given when the readout is ”0”. Therefore, operation of 100-frequency division and that of 256-frequency division are carried out for the HC40102 and
HC40103, respectively, when clock input alone is
given without various kinds of preset operation.
PRESET OPERATION AND RESET OPERATION
When Clear (CLEAR) input is set to the ”L” level, the
readout is set to the maximum count independetly
of other inputs. When Asynchronous Preset Enable
(APE) input is set to the ”L” level, readouts given on
J0 to J7 can be preset asynchronously to counter independently of inputs other than CLEAR input.
When Synchronous Preset Enable (SPE) is set to
the ”L” level, the readouts given on J0 to J7 can be
preset to counter synchronously with the rise of
clock.
As to these operation modes, refer to the truth table.
Input
CLEAR APE SPE J
L
X
X
H
L
H
L
H
Output
T E CLO CK
Qn + 1
X
X
X
X
L
X
X
L
X
H
X
H
H
L
L
X
X
_

_▲_
H
H
L
H
X
H
H
L
X
X
H
__
Qn
H
H
H
X
L
▲_
_

_▼
_
_
▲
H
H
H
X
H
X

L
L
Qn
__
Qn
7/14
M54/M74HC40102/40103
SWITCHING CHARACTERISTICS TEST WAVEFORM
WAVEFORM 1
WAVEFORM 2
WAVEFORM 3
WAVEFORM 4
WAVEFORM 5
WAVEFORM 6
(** F/F output is internal signal of IC)
8/14
M54/M74HC40102/40103
EXAMPLE OF TYPICAL APPLICATION
PROGRAMMABLE DIVIDE-BY-N COUNTER
fIN
N+ 1
•Timing chart when N = ”3”
(J0, J1 = VCC, J2 – J7 = GND)
• fOUT =
• HC40102... 1/2 to 1/100 are dividable
• HC40103... 1/2 to 1/256 are dividable
PARALLEL CARRY CASCADING
* At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digitplace changes, due to delay arrival. Therefore,
take gate from HC32 or the like, not from C0 output at the rear stage directly.
PROGRAMMABLE TIMER
Note :The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the
above formula-1/fIN ∼ the above formula.
9/14
M54/M74HC40102/40103
Plastic DIP16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
10/14
M54/M74HC40102/40103
Ceramic DIP16/1 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
20
0.787
B
7
0.276
D
E
3.3
0.130
0.38
e3
0.015
17.78
0.700
F
2.29
2.79
0.090
0.110
G
0.4
0.55
0.016
0.022
H
1.17
1.52
0.046
0.060
L
0.22
0.31
0.009
0.012
M
0.51
1.27
0.020
0.050
N
P
Q
10.3
7.8
8.05
5.08
0.406
0.307
0.317
0.200
P053D
11/14
M54/M74HC40102/40103
SO16 (Narrow) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.004
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
E
5.8
10
0.385
6.2
0.228
0.393
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
P013H
12/14
M54/M74HC40102/40103
PLCC20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
9.78
10.03
0.385
0.395
B
8.89
9.04
0.350
0.356
D
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
E
7.37
8.38
0.290
0.330
e
1.27
0.050
e3
5.08
0.200
F
0.38
0.015
G
0.101
0.004
M
1.27
0.050
M1
1.14
0.045
P027A
13/14
M54/M74HC40102/40103
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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14/14