INTEL M80C287

M80C287
80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION
Military
Y
High Performance 80-Bit Internal
Architecture
Y
Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point
Arithmetic
Y
Implements Extended M387 Numerics
Coprocessor Instruction Set
Y
Two to Three Times M8087/M80287
Performance at Equivalent Clock Speed
Y
Low Power Consumption
Y
Upward Object-Code Compatible from
M8087 and M80287
Y
Interfaces with M80286 and M80C286
CPUs
Y
Expands CPU’s Data Types to Include
32-, 64-, 80-Bit Floating Point, 32-, 64Bit Integers and 18-Digit BCD Operands
Y
Directly Extends CPU’s Instruction Set
to Trigonometric, Logarithmic,
Exponential, and Arithmetic
Instructions for All Data Types
Y
Full-Range Transcendental Operations
for SINE, COSINE, TANGENT.
ARCTANGENT and LOGARITHM
Y
Built-In Exception Handling
Y
Operates in Both Real and Protected
Mode Systems
Y
Eight 80-Bit Numeric Registers, Usable
as Individually Addressable General
Registers or as a Register Stack
Y
Available in 40-pin CERDIP
(See Packaging Outlines and Dimensions, order Ý231369)
Y
Military Temperature Range:
b 55§ C to a 125§ C (TC)
The Intel M80C287 is a high-performance numerics processor extension that extends the architecture of the
M80C286 CPU with floating point, extended integer, and BCD data types. A computing system that includes
the M80C287 fully conforms to the IEEE Floating Point Standard. Using a numerics oriented architecture, the
M80C287 adds over seventy mnemonics to the instruction set of the M80C286 CPU, making a complete
solution for high-performance numerics processing. The M80C287 is implemented with 1.5 micron, high-speed
CHMOS III technology and packaged in a 40-pin CERDIP. The M80C287 is upward object-code compatible
from the M80287 and M8087 numerics coprocessors. With proper socket design, either an M80287 or an
M80C287 can use the same socket.
271092 – 1
Figure 1. M80C287 Block Diagram
November 1991
Order Number: 271092-005
M80C287
M80C287 Data Registers
79
78
R0 Sign
64 63
0
Exponent
Significand
R1
R2
R3
R4
R5
R6
R7
15
0
31
15
Control Register
Instruction Pointer
Status Register
Data Pointer
0
Tag Word
Figure 2. M80C287 Register Set
FUNCTIONAL DESCRIPTION
The M80C287 Numeric Processor Extension (NPX)
provides arithmetic instructions for a variety of numeric data types. It also executes numerous built-in
transcendental functions (e.g. tangent, sine, cosine,
and log functions). The M80C287 effectively extends the register and instruction set of the CPU for
existing data types and adds several new data types
as well. Figure 2 shows the additional registers visible to programs in a system that includes the
M80C287. Essentially, the M80C287 can be treated
as an additional resource or an extension to the
M80C286 CPU. The M80C286 CPU together with an
M80C287 NPX can be used as a single unified system.
The M80C287 has two operating modes. After reset,
the M80C287 is in the real-address mode. It can be
placed into protected mode by executing the
FSETPM instruction. It can be switched back to realaddress mode by executing the FRSTPM instruction
(note that this feature is useful only with CPU’s that
can also switch back to real-address mode). These
instructions control the format of the administrative
instructions FLDENV, FSTENV, FRSTOR, and
FSAVE. Regardless of operating mode, all references to memory for numerics data or status information are performed by the M80C286 CPU, and
therefore obey the memory-management and protection rules of the M80C286 CPU.
In real-address mode, a system that includes the
M80C287 is completely upward compatible with
software for the M8086/M8087 and for M80286/
M80287 real-address mode.
In protected mode, a system that includes the
M80C287 is completely upward compatible with
software for M80286/M80287 protected mode systems.
2
The only differences of operation that may appear
when M8086/M8087 programs are ported to a protected-mode M80C287 system are in the format of
operands for the administrative instructions
FLDENV, FSTENV, FRSTOR, and FSAVE. These instructions are normally used only by exception handlers and operating systems, not by applications
programs.
PROGRAMMING INTERFACE
The M80C287 adds to the CPU additional data
types, registers, instructions, and interrupts specifically designed to facilitate high-speed numerics processing. To use the M80C287 requires no special
programming tools, because all new instructions and
data types are directly supported by the assembler
and compilers for high-level languages. All 8086/
8088 development tools that support the M8087 can
also be used to develop software for the M80C286/
M80C287 in real-address mode. All M80286 development tools that support the M80287 can also be
used to develop software for the M80C286/
M80C287. The M80C287 supports all M387 NPX instructions, producing the same binary results.
All communication between the M80C286 CPU and
the M80C287 is transparent to applications software. The M80C286 CPU automatically controls the
M80C287 whenever a numerics instruction is executed. All physical memory and virtual memory of
the M80C286 CPU are available for storage of the
instructions and operands of programs that use the
M80C287. All memory addressing modes are available for addressing numerics operands.
The instructions that the M80C287 adds to the instruction set are listed at the end of this data sheet.
M80C287
Data Types
Table 1 lists the seven data types that the M80C287
supports and presents the format for each type. Operands are stored in memory with the least significant digit at the lowest memory address. Programs
retrieve these values by generating the lowest address. For maximum system performance, all operands should start at physical-memory addresses
that correspond to the word size of the CPU; operands may begin at any other addresses, but will require extra memory cycles to access the entire operand.
Internally, the M80C287 holds all numbers in the extended-precision real format. Instructions that load
operands from memory automatically convert operands represented in memory as 16-, 32-, or 64-bit
integers, 32- or 64-bit floating-point numbers, or 18digit packed BCD numbers into extended-precision
real format. Instructions that store operands in memory perform the inverse type conversion.
Numeric Operands
A typical NPX instruction accepts one or two operands and produces one (or sometimes two) results.
In two-operand instructions, one operand is the contents of an NPX register, while the other may be a
memory location. The operands of some instructions
are predefined; for example, FSQRT always takes
the square root of the number in the top stack element.
Register Set
Figure 2 shows the M80C287 register set. When an
M80C287 is present in a system, programmers may
use these registers in addition to the registers normally available on the CPU.
DATA REGISTERS
M80C287 computations use the M80C287’s data
registers. These eight 80-bit registers provide the
equivalent capacity of 20 32-bit registers. Each of
the eight data registers in the M80C287 is 80 bits
wide and is divided into ‘‘fields’’ corresponding to
the NPX’s extended-precision real data type.
The M80C287 register set can be accessed either
as a stack, with instructions operating on the top one
or two stack elements, or as individually addressable
registers. The TOP field in the status word identifies
the current top-of-stack register. A ‘‘push’’ operation
decrements TOP by one and loads a value into the
new top register. A ‘‘pop’’ operation stores the value
from the current top register and then increments
TOP by one. The M80C287 register stack grows
‘‘down’’ toward lower-addressed registers.
Instructions may address the data registers either
implicitly or explicitly. Many instructions operate on
the register at the TOP of the stack. These instructions implicitly address the register at which TOP
points. Other instructions allow the programmer to
explicitly specify which register to use. This explicit
register addressing is also relative to TOP.
TAG WORD
The tag word marks the content of each numeric
data register, as Figure 3 shows. Each two-bit tag
represents one of the eight data registers. The principal function of the tag word is to optimize the
NPX’s performance and stack handling by making it
possible to distinguish between empty and nonempty register locations. It also enables exception handlers to identify special values (e.g. NaNs or denormals) in the contents of a stack location without the
need to perform complex decoding of the actual
data.
STATUS WORD
The 16-bit status word (in the status register) shown
in Figure 4 reflects the overall state of the M80C287.
It may be read and inspected by programs.
Bit 15, the B-bit (busy bit) is included for M8087
compatibility only. It always has the same value as
the ES bit (bit 7 of the status word); it does not
indicate the status of the BUSY output of M80C287.
Bits 13 – 11 (TOP) point to the M80C287 register that
is the current top-of-stack.
The four numeric condition code bits (C3 –C0) are
similar to the flags in a CPU; instructions that perform arithmetic operations update these bits to reflect the outcome. The effects of these instructions
on the condition code are summarized in Tables 2
through 5.
Bit 7 is the error summary (ES) status bit. This bit is
set if any unmasked exception bit is set; it is clear
otherwise. If this bit is set, the ERROR signal is asserted.
Bit 6 is the stack flag (SF). This bit is used to distinguish invalid operations due to stack overflow or underflow from other kinds of invalid operations. When
SF is set, bit 9 (C1) distinguishes between stack
overflow (C1 e 1) and underflow (C1 e 0).
3
M80C287
Table 1. M80C287 Data Type Representation in Memory
271092 – 2
NOTES:
1. S e Sign bit (0 e positive, 1 e negative)
2. dn e Decimal digit (two per byte)
3. X e Bits have no significance: M80C287 ignores when loading, zeroes when storing
4. U e Position of implicit binary point
5. I e Integer bit of significand; stored in temporary real, implicit in single and double precision
6. Exponent Bias (normalized values):
Single: 127 (7FH)
Double: 1023 (3FFH)
Extended Real: 16383 (3FFFH)
7. Packed BCD: (b1)S (D17 . . . D0)
8. Real: ( b1)S (2E-BIAS) (F0 F1 . . . )
15
TAG (7)
0
TAG (6)
TAG (5)
TAG (4)
TAG (3)
TAG (2)
TAG (1)
TAG (0)
NOTE:
The index i of tag(i) is not top-relative. A program typically uses the ‘‘top’’ field of Status Word to determine which tag(i)
field refers to logical top of stack.
TAG VALUES:
00 e Valid
01 e Zero
10 e QNaN, SNaN, Infinity, Denormal and Unsupported Formats
11 e Empty
Figure 3. M80C287 Tag Word
4
M80C287
Figure 4 shows the six exception flags in bits 5– 0 of
the status word. Bits 5–0 are set to indicate that the
M80C287 has detected an exception while executing an instruction. A later section entitled ‘‘Exception
Handling’’ explains how they are set and used.
Note that when a new value is loaded into the status
word by the FLDENV or FRSTOR instruction, the
value of ES (bit 7) and its reflection in the B-bit (bit
15) are not derived from the values loaded from
memory but rather are dependent upon the values of
the exception flags (bits 5 – 0) in the status word and
their corresponding masks in the control word. If ES
is set in such a case, the ERROR output of the
M80C287 is activated immediately.
271092 – 3
ES is set if any unmasked exception bit is set; cleared otherwise.
See Table 2.2 for interpretation of condition code.
TOP Values:
000 e Register 0 is Top of Stack
001 e Register 1 is Top of Stack
#
#
#
111 e Register 7 is Top of Stack
For definitions of exceptions, refer to the section entitled ‘‘Exception Handling.’’
Figure 4. Status Word
5
M80C287
Table 2. Condition Code Interpretation
Instruction
FPREM, FPREM1
(See Table 3)
FCOM, FCOMP,
FCOMPP, FTST,
FUCOM, FUCOMP,
FUCOMPP, FICOM,
FICOMP
C0 (S)
C3 (Z)
C1 (A)
Three Least Significant Bits
of Quotient
Q2
Q0
Q1
or O/U
C2 (C)
Reduction
0 e Complete
1 e Incomplete
Result of Comparison
(See Table 2.4)
Zero
or O/U
Operand is Not Comparable
(Table 2.4)
Operand Class
(See Table 2.5)
Sign
or O/U
Operand Class
(Table 2.5)
FCHS, FABS, FXCH,
FINCTOP, FDECTOP,
Constant Loads,
FXTRACT, FLD,
FILD, FBLD,
FSTP (Ext Real)
UNDEFINED
Zero
or O/U
UNDEFINED
FIST, FBSTP,
FRNDINT, FST
FSTP, FADD, FMUL,
FDIV, FDIVR,
FSUB, FSUBR,
FSCALE, FSQRT,
FPATAN, F2XM1,
FYL2X, FYL2XP1
UNDEFINED
Roundup
or O/U
UNDEFINED
UNDEFINED
Roundup
or O/U
Undefined
if C2 e 1
Reduction
0 e Complete
1 e Incomplete
FXAM
FPTAN, FSIN,
FCOS, FSINCOS
FLDENV, FRSTOR
Each Bit Loaded from Memory
FLDCW, FSTENV,
FSTCW, FSTSW,
FCLEX, FINIT,
FSAVE
UNDEFINED
O/U
When both IE and SF bits of status word are set, indicating a stack exception, this bit distinguishes between
stack overflow (C1 e 1) and underflow (C1 e 0).
Reduction
If FPREM or FPREM1 produces a remainder that is less than the modulus, reduction is complete. When
reduction is incomplete the value at the top of the stack is a partial remainder, which can be used as input to
further reduction. For FPTAN, FSIN, FCOS, and FSINCOS, the reduction bit is set if the operand at the top of
the stack is too large. In this case the original operand remains at the top of the stack.
Roundup
When the PE bit of the status word is set, this bit indicates whether one was added to the least significant bit of
the result during the last rounding.
UNDEFINED Do not rely on finding any specific value in these bits.
6
M80C287
Table 3. Condition Code Interpretation after FPREM and FPREM1 Instructions
Condition Code
Interpretation after
FPREM and FPREM1
C2
C3
C1
C0
1
X
X
X
Q1
Q0
Q2
Q MOD 8
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
2
3
4
5
6
7
0
Incomplete Reduction: Further iteration required for complete
reduction.
Table 4. Condition Code
Resulting from Comparison
Order
C3
C2
C0
TOP l Operand
TOP k Operand
0
0
1
1
0
0
0
1
0
1
0
1
TOP e Operand
Unordered
Table 5. Condition Code
Defining Operand Class
C3
C2
C1
C0
Value at TOP
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
a Unsupported
a NaN
b Unsupported
b Nan
a Normal
a Infinity
b Normal
b Infinity
a0
a Empty
b0
b Empty
a Denormal
b Denormal
CONTROL WORD
The NPX provides several processing options that
are selected by loading a control word from memory
into the control register. Figure 5 shows the format
and encoding of fields in the control word.
Complete Reduction: C0, C3, C1 contain three
least significant bits of quotient.
The low-order byte of this control word configures
exception masking. Bits 5 – 0 of the control word
contain individual masks for each of the six exceptions that the M80C287 recognizes.
The high-order byte of the control word configures
the M80C287 operating mode, including precision,
rounding, and infinity control.
# The ‘‘infinity control bit’’ (bit 12) is not meaningful
to the M80C287, and programs must ignore its
value. To maintain compatibility with the M8087
and M80287, this bit can be programmed; however, regardless of its value, the M80C287 always
treats infinity in the affine sense ( b % k a % ).
This bit is initialized to zero both after a hardware
reset and after the FINIT instruction.
# The rounding control (RC) bits (bits 11 – 10) provide for directed rounding and true chop, as well
as the unbiased round to nearest even mode
specified in the IEEE standard. Rounding control
affects only those instructions that perform
rounding at the end of the operation (and thus
can generate a precision exception); namely,
FST, FSTP, FIST, all arithmetic instructions (except FPREM, FPREM1, FXTRACT, FABS, and
FCHS), and all transcendental instructions.
# The precision control (PC) bits (bits 9 – 8) can be
used to set the M80C287 internal operating precision of the significand at less than the default of
64 bits (extended precision). This can be useful in
providing compatibility with early generation arithmetic processors of smaller precision. PC affects
only the instructions ADD, SUB, DIV, MUL, and
SQRT. For all other instructions, either the precision is determined by the opcode or extended
precision is used.
7
M80C287
INSTRUCTION AND DATA POINTERS
Because the NPX operates in parallel with the CPU,
any exceptions detected by the NPX may be reported after the CPU has executed the ESC instruction
which caused it. To allow identification of the failing
numeric instruction, the M80C287 contains registers
that aid in diagnosis. These registers supply the opcode of the failing numeric instruction, the address
of the instruction, and the address of its numeric
memory operand (if appropriate).
The instruction and data pointers are provided for
user-written exception handlers. Whenever the
M80C287 executes a new ESC instruction, it saves
the address of the instruction (including any prefixes
that may be present), the address of the operand (if
present), and the opcode. CPUs with 32-bit internal
architectures contain 32-bit versions of these registers and do not use the contents of the NPX registers. This difference is not apparent to programmers,
however.
The instruction and data pointers appear in one of
four formats depending on the operating mode of
the system (protected mode or real-address mode)
and (for CPUs with 32-bit internal architectures) depending on the operand-size attribute in effect (32bit operand or 16-bit operand). (See Figures 6 and 7)
The ESC instructions FLDENV, FSTENV, FSAVE,
and FRSTOR are used to transfer these values between the registers and memory. Note that the value
of the data pointer is undefined if the prior ESC instruction did not have a memory operand.
271092 – 4
Precision Control
00 – 24 bits (single precision)
01 – (reserved)
10 – 53 bits (double precision)
11 – 64 bits (extended precision)
Rounding Control
00 – Round to nearest or even
01 – Round down (toward b % )
10 – Round up (toward a % )
11 – Chop (truncate toward zero)
*The ‘‘infinity control’’ bit is not meaningful to the M80C287. To maintain compatibility with the M80287, this bit can be
programmed; however, regardless of its value, the M80C287 treats infinity in the affine sense ( b % k a % ).
Figure 5. Control Word
8
M80C287
15
Protected Mode Format
7
0
Real-Address Mode Format
7
15
0
Control Word
a0
Control Word
a0
Status Word
a2
Status Word
a2
Tag Word
a4
Tag Word
a4
IP Offset
a6
Instruction Pointer 15..0
a6
CS Selector
a8
Operand Offset
aA
Operand Selector
aC
IP 19..16
OP 19..16
Figure 6. Protected Mode Instruction and Data
Pointer Image in Memory
0
0
OPCODE 10..0
a8
Operand Pointer 15..0
aA
0
0
0
0
0
0
0
0
0
0
0
aC
Figure 7. Real Mode Instruction and Data
Pointer Image in Memory
Table 6. CPU Interrupt Vectors Reserved for NPX
Interrupt
Number
Cause of Interrupt
7
In a system with a CPU that has control registers, an ESC instruction was encountered when
EM or TS of CPU control register zero (CR0) was set. EM e 1 indicates that software
emulation of the instruction is required. When TS is set, either an ESC or WAIT instruction
causes interrupt 7. This indicates that the current NPX context may not belong to the current
task.
9
In a protected-mode system, an operand of a coprocessor instruction wrapped around an
addressing limit (0FFFFH for expand-up segments, zero for expand-down segments) and
spanned inaccessible addresses (See Note). The failing numerics instruction is not restartable.
The address of the failing numerics instruction and data operand may be lost; an FSTENV does
not return reliable addresses. The segment overrun exception should be handled by executing
an FNINIT instruction (i.e., an FINIT without a preceding WAIT). The exception can be avoided
by never allowing numerics operands to cross the end of a segment.
13
In a protected-mode system, the first word of a numeric operand is not entirely within the limit
of its segment. The return address pushed onto the stack of the exception handler points at the
ESC instruction that caused the exception, including any prefixes. The M80C287 has not
executed this instruction; the instruction pointer and data pointer register refer to a previous,
correctly executed instruction.
16
The previous numerics instruction caused an unmasked exception. The address of the faulty
instruction and the address of its operand are stored in the instruction pointer and data pointer
registers. Only ESC and WAIT instructions can cause this interrupt. The CPU return address
pushed onto the stack of the exception handler points to a WAIT or ESC instruction (including
prefixes). This instruction can be restarted after clearing the exception condition in the NPX.
FNINIT, FNCLEX, FNSTSW, FNSTENV, and FNSAVE cannot cause this interrupt.
NOTE:
An operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near
the largest valid address in the segment. Because of the wrap-around, the beginning and ending addresses of such an
operand will be at opposite ends of the segment. There are two ways that such an operand may also span inaccessible
addresses: 1) if the segment limit is not equal to the addressing limit (e.g. addressing limit is FFFFH and segment limit is
FFFDH) the operand will span addresses that are not within the segment (e.g. an 8-byte operand that starts at valid offset
FFFCH will span addresses FFFC–FFFFH and 0000– 0003H; however addresses FFFEH and FFFFH are not valid, because
they exceed the limit); 2) if the operand begins and ends in present and accessible segments but intermediate bytes of the
operand fall in a not-present segment or page or in a segment or page to which the procedure does not have access rights.
Interrupt Description
Exception Handling
CPU interrupts are used to report exceptional conditions while executing numeric programs in either real
or protected mode. Table 6 shows these interrupts
and their functions.
The M80C287 detects six different exception conditions that can occur during instruction execution. Table 7 lists the exception conditions in order of precedence, showing for each the cause and the
9
M80C287
Table 7. Exceptions
Exception
Default Action
(If Exception is Masked)
Cause
Invalid
Operation
Operation on a signalling NaN,
unsupported format, indeterminate form
(0* % , 0/0, ( a % ) a ( b % ), etc.), or
stack overflow/underflow (SF is also
set).
Result is a quiet NaN, integer indefinite,
or BCD indefinite.
Denormalized
Operand
At least one of the operands is
denormalized, i.e., it has the smallest
exponent but a nonzero significand.
The operand is normalized, and normal
processing continues.
Zero Divisor
The divisor is zero while the dividend is a
noninfinite, nonzero number.
Result is % .
Overflow
The result is too large in magnitude to fit
in the specified format.
Result is largest finite value or % .
Underflow
The true result is nonzero but too small
to be represented in the specified
format, and, if underflow exception is
masked, denormalization causes loss of
accuracy.
Result is denormalized or zero.
Inexact
Result
(Precision)
The true result is not exactly
representable in the specified format
(e.g. (/3); the result is rounded according
to the rounding mode.
Normal processing continues.
default action taken by the M80C287 if the exception is masked by its corresponding mask bit in the
control word.
Any exception that is not masked by the control
word sets the corresponding exception flag of the
status word, sets the ES bit of the status word, and
asserts the ERROR signal. When the CPU attempts
to execute another ESC instruction or WAIT, exception 16 occurs. The exception condition must be resolved via an interrupt service routine. The return
address pushed onto the CPU stack upon entry to
the service routine does not necessarily point to the
failing instruction nor to the following instruction. The
M80C287 saves the address of the floating-point instruction that caused the exception and the address
of any memory operand required by that instruction.
Initialization
After FNINIT or RESET, the control word contains
the value 037FH (all exceptions masked, precision
control 64 bits, rounding to nearest) the same values
as in an 80287 after RESET. For compatibility with
the M8087 and M80287, the bit that used to indicate
infinity control (bit 12) is set to zero; however, re-
10
gardless of its setting, infinity is treated in the affine
sense. After FNINIT or RESET, the status word is
initialized as follows:
# All exceptions are set to zero.
# Stack TOP is zero, so that after the first push the
stack top will be register seven (111B).
# The condition code C3 –C0 is undefined.
# The B-bit is zero.
The tag word contains FFFFH (all stack locations
are empty).
M80C286/M80C287 initialization software should
execute an FNINIT instruction (i.e an FINIT without a
preceding WAIT) after RESET. The FNINIT is not
strictly required for either M80287 or M80C287 software, but Intel recommends its use to help ensure
upward compatibility with other processors.
M8087 and M80287 Compatibility
This section summarizes the differences between
the M80C287 and the M80287. Any migration from
the M8087 directly to the M80C287 must also take
into account the differences between the M8087
and the M80287 as listed in Appendix A.
M80C287
Many changes have been designed into the
M80C287 to directly support the IEEE standard in
hardware. These changes result in increased performance by eliminating the need for software that
supports the standard.
4. The FSQRT, FBSTP, and FPREM instructions
may cause underflow, because they support denormal operands.
GENERAL DIFFERENCES
6. The denormal exception no longer takes precedence over all other exceptions.
7. When the denormal exception is masked, the
M80C287 automatically normalizes denormal
operands. The M8087/M80287 performs unnormal arithmetic, which might produce an unnormal result.
The M80C287 supports only affine closure for infinity arithmetic, not projective closure.
Operands for FSCALE and FPATAN are no longer
restricted in range (except for g % ); F2XM1 and
FPTAN accept a wider range of operands.
Rounding control is in effect for FLD constant .
Software cannot change entries of the tag word to
values (other than empty) that differ from actual register contents.
After reset, FINIT, and incomplete FPREM, the
M80C287 resets to zero the condition code bits C3 –
C0 of the status word.
In conformance with the IEEE standard, the
M80C287 does not support the special data formats
pseudozero, pseudo-NaN, pseudoinfinity, and unnormal.
The denormal exception has a different purpose on
the M80C287. A system that uses the denormal-exception handler solely to normalize the denormal operands, would better mask the denormal exception
on the M80C287. The M80C287 automatically normalizes denormal operands when the denormal exception is masked.
EXCEPTIONS
A number of differences exist due to changes in the
IEEE standard and to functional improvements to
the architecture of the M80C287:
1. When the overflow or underflow exception is
masked, the M80C287 differs from the M80287
in rounding when overflow or underflow occurs.
The M80C287 produces results that are consistent with the rounding mode.
2. When the underflow exception is masked, the
M80C287 sets its underflow flag only if there is
also a loss of accuracy during denormalization.
3. Fewer invalid-operation exceptions due to denormal operands, because the instructions
FSQRT, FDIV, FPREM, and conversions to BCD
or to integer normalize denormal operands before proceeding.
5. The denormal exception can occur during the
transcendental instructions and the FXTRACT
instruction.
8. When the operand is zero, the FXTRACT instruction reports a zero-divide exception and
leaves b % in ST(1).
9. The status word has a new bit (SF) that signals
when invalid-operation exceptions are due to
stack underflow or overflow.
10. FLD extended precision no longer reports denormal exceptions, because the instruction is not
numeric.
11. FLD single/double precision when the operand
is denormal converts the number to extended
precision and signals the denormalized operand
exception. When loading a signalling NaN, FLD
single/double precision signals an invalid-operand exception.
12. The M80C287 only generates quiet NaNs (as on
the M80287); however, the M80C287 distinguishes between quiet NaNs and signaling
NaNs. Signaling NaNs trigger exceptions when
they are used as operands; quiet NaNs do not
(except for FCOM, FIST, and FBSTP which also
raise IE for quiet NaNs).
13. When stack overflow occurs during FPTAN and
overflow is masked, both ST(0) and ST(1) contain quiet NaNs. The M8087/M80287 leaves the
original operand in ST(1) intact.
14. When the scaling factor is g % , the FSCALE
(ST(0), ST(1)) instruction behaves as follows
(ST(0) and ST(1) contain the scaled and scaling
operands respectively):
# FSCALE(0, % ) generates the invalid operation
exception.
# FSCALE(finite, b % ) generates zero with the
same sign as the scaled operand.
# FSCALE(finite, a % ) generates -in with the
same sign as the scaled operand.
The M8087/M80287 returns zero in the first
case and raises the invalid-operation exception
in the other cases.
11
M80C287
15. The M80C287 returns signed infinity/zero as the
unmasked response to massive overflow/underflow. The M8087 and M80287 support a limited
range for the scaling factor; within this range either massive overflow/underflow do not occur or
undefined results are produced.
HARDWARE INTERFACE
Signal Description
In the following signal descriptions, the M80C287
pins are grouped by function as follows:
1. Execution controlÐCLK, CKM, RESET
2. NPX handshakeÐPEREQ,
ERROR
BUSY,
PEACK,
3. Bus interface pinsÐD15 –D0, NPWR, NPRD
4. Chip/Port SelectÐNPS1, NPS2, CMD0, CMD1
5. Power suppliesÐVCC, VSS
Table 8 lists every pin by its identifier, gives a brief
description of its function, and lists some of its characteristics. Figure 8 shows the locations of pins on
the CERDIP package. Table 9 helps to locate pin
identifiers in Figure 8.
271092 – 5
*The corresponding pins of the M80287 differ.
Figure 8. CERDIP Pin Configuration
Table 8. Pin Summary
12
Active
State
Input/
Output
CLocK
ClocKing Mode
System reset
High
I
I
I
PEREQ
PEACK
BUSY
ERROR
Processor Extension REQuest
Processor Extension ACKnowledge
Busy status
Error status
High
Low
Low
Low
O
I
O
O
D15–D0
NPRD
NPWR
Data pins
Numeric Processor ReaD
Numeric Processor WRite
High
Low
Low
I/O
I
I
NPS1
NPS2
CMD0
CMD1
NPX select 1
NPX select 2
CoMmanD 0
CoMmanD 1
Low
High
High
High
I
I
I
I
VCC
VSS
System power
System ground
Pin Name
Function
CLK
CKM
RESET
I
I
M80C287
Table 9. CERDIP Pin Cross-Reference
Pin
Name
CERDIP
Package
CLK
CKM
RESET
PEREQ
PEACK
BUSY
ERROR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
NPRD
NPWR
NPS1
NPS2
CMD0
CMD1
VCC
VSS
No Connect
32
39
35
24
36
25
26
23
22
21
20
19
18
17
16
15
14
12
11
8
7
6
5
27
28
34
33
29
31
3,9,13,37,40
1,4,10,30,38
2
CLOCK (CLK)
This input provides the basic timing for internal operation. This pin does not require MOS-level input; it
will operate at either TTL or MOS levels up to the
maximum allowed frequency. A minimum frequency
must be provided to keep the internal logic properly
functioning. Depending on the signal on CKM, the
signal on CLK can be divided by two to produce the
internal clock signal.
CLOCKING MODE (CKM)
two to produce the internal clock signal. During the
RESET sequence, this input must be stable at least
four internal clock cycles (i.e. CLK clocks when CKM
is HIGH; 2 c CLK clocks when CKM is LOW) before
RESET goes LOW.
SYSTEM RESET (RESET)
A LOW to HIGH transition on this pin causes the
M80C287 to terminate its present activity and to enter a dormant state. RESET must remain active
(HIGH) for at least four CLK periods (i.e., the RESET
signal presented to the M80C287 must be at least
four M80C287 clocks long, regardless of the frequency of the CPU). Note that the M80C287 is active internally for 25 clock cycles after the termination of the RESET signal (the HIGH to LOW transition of RESET); therefore, the first instruction
should not be written to the M80C287 until 25 clocks
after the falling edge of RESET. Table 10 shows the
status of the output pins during the reset sequence.
After a reset, all output pins return to their inactive
states.
Table 10. Output Pin Status during Reset
Output Pin Name
Value During Reset
BUSY
HIGH
ERROR
HIGH
PEREQ
LOW
D15 –D0
Tristate OFF
PROCESSOR EXTENSION REQUEST (PEREQ)
When active, this pin signals to the CPU that the
M80C287 is ready for data transfer to/from its data
FIFO. With M80286 or M80C286 CPUs, PEREQ can
be deactivated after assertion of PEACK. These
CPUs rely on the NPX to deassert PEREQ when all
operands have been transfered. When there are
more than five data transfers, PEREQ is deactiviated
after the first three transfers and subsequently after
every four transfers. This signal always goes inactive
before BUSY goes inactive.
BUSY STATUS (BUSY)
When active, this pin signals to the CPU that the
M80C287 is currently executing an instruction. It
should be connected to the CPU’s BUSY pin. During
the RESET sequence this pin is HIGH.
This pin is a strapping option. When it is strapped to
VCC (HIGH), the CLK input is used directly; when
strapped to VSS (LOW), the CLK input is divided by
13
M80C287
ERROR STATUS (ERROR)
COMMAND SELECTS (CMD0 AND CMD1)
This pin reflects the ES bit of the status register.
When active, it indicates that an unmasked exception has occurred. This signal can be changed to
inactive state only by the following instructions (without a preceding WAIT): FNINIT, FNCLEX,
FNSTENV, FNSAVE, FLDCW, FLDENV, and
FRSTOR. This pin should be connected to the
ERROR pin of the CPU. ERROR can change state
only when BUSY is active.
These pins along with the select pins allow the CPU
to direct the operation of the M80C287.
PROCESSOR EXTENSION ACKNOWLEDGE
(PEACK)
During execution of escape instructions, an M80286
or M80C286 CPU asserts PEACK to acknowledge
that the request signal (PEREQ) has been recognized and that data transfer is in progress. The
M80286/M80C286 also drives this signal HIGH during RESET.
This input may be asynchronous with respect to the
M80C287 clock except during a RESET sequence,
when it must satisfy setup and hold requirements
relative to RESET.
DATA PINS (D15 –D0)
These bidirectional pins are used to transfer data
and opcodes between the CPU and M80C287. They
are normally connected directly to the corresponding CPU data pins. Other buffers/drivers driving the
local data bus must be disabled when the CPU
reads from the NPX. HIGH state indicates a value of
one. D0 is the least significant data bit.
NUMERIC PROCESSOR WRITE (NPWR)
A signal on this pin enables transfers of data from
the CPU to the NPX. This input is valid only when
NPS1 and NPS2 are both active.
NUMERIC PROCESSOR READ (NPRD)
A signal on this pin enables transfers of data from
the NPX to the CPU. This input is valid only when
NPS1 and NPS2 are both active.
NUMERIC PROCESSOR SELECTS (NPS1 and
NPS2)
Concurrent assertion of these signals indicates that
the CPU is performing an escape instruction and enables the M80C287 to execute that instruction. No
data transfer involving the M80C287 occurs unless
the device is selected by these lines.
14
SYSTEM POWER (VCC)
System power provides the a 5V g 5% DC supply
input. All VCC pins should be tied together on the
circuit board and local decoupling capacitors should
be used between VCC and VSS.
SYSTEM GROUND (VSS)
All VSS pins should be tied together on the circuit
board and local decoupling capacitors should be
used between VCC and VSS.
Processor Architecture
As shown by the block diagram on the front page,
the M80C287 NPX is internally divided into three
sections: the bus control logic (BCL), the data interface and control unit, and the floating point unit
(FPU). The FPU (with the support of the control unit
which contains the sequencer and other support
units) executes all numerics instructions. The data
interface and control unit is responsible for the data
flow to and from the FPU and the control registers,
for receiving the instructions, decoding them, and
sequencing the microinstructions, and for handling
some of the administrative instructions. The BCL is
responsible for CPU bus tracking and interface.
BUS CONTROL LOGIC
The BCL communicates solely with the CPU using I/
O bus cycles. The BCL appears to the CPU as a
special peripheral device. It is special in two respects: the CPU initiates I/O automatically when it
encounters ESC instructions, and the CPU uses reserved I/O addresses to communicate with the BCL.
The BCL does not communicate directly with memory. The CPU performs all memory access, transferring input operands from memory to the M80C287
and transferring outputs from the M80C287 to memory. A dedicated communication protocol makes
possible high-speed transfer of opcodes and operands between the M80C286 CPU and M80C287.
DATA INTERFACE AND CONTROL UNIT
The data interface and control unit latches the data
and, subject to BCL control, directs the data to the
FIFO or the instruction decoder. The instruction de-
M80C287
Table 11. Bus Cycles Definition
NPS1
NPS2
CMD0
CMD1
NPRD
NPWR
Bus Cycle Type
x
1
0
0
0
0
0
0
0
0
0
x
1
1
1
1
1
1
1
1
x
x
0
0
1
1
0
0
1
1
x
x
0
0
0
0
1
1
1
1
x
x
1
0
0
1
1
0
0
1
x
x
0
1
1
0
0
1
1
0
M80C287 not selected
M80C287 not selected
Opcode write to M80C287
CW or SW read from M80C287
Read data from M80C287
Write data to M80C287
Write exception pointers
Reserved
Reserved
Reserved
coder decodes the ESC instructions sent to it by the
CPU and generates controls that direct the data flow
in the FIFO. It also triggers the microinstruction sequencer that controls execution of each instruction.
If the ESC instruction is FINIT, FCLEX, FSTSW,
FSTSW AX, FSTCW, FSETPM, or FRSTPM, the
control executes it independently of the FPU and the
sequencer. The data interface and control unit is the
one that generates the BUSY, PEREQ, and ERROR
signals that synchronize M80C287 activities with the
CPU.
Table 12. I/O Address Decoding
M80C287 Select and
Command Inputs
I/O Address
(Hexadecimal)
00F8
00FA
00FC
NPS2
NPS1
CMD1
CMD0
1
1
1
0
0
0
0
0
1
0
1
0
CPU/NPX SYNCHRONIZATION
FLOATING-POINT UNIT
The FPU executes all instructions that involve the
register stack, including arithmetic, logical, transcendental, constant, and data transfer instructions. The
data path in the FPU is 84 bits wide (68 significant
bits, 15 exponent bits, and a sign bit) which allows
internal operand transfers to be performed at very
high speeds.
Bus Cycles
The pins NPS1, NPS2, CMD0, CMD1, NPRD, and
NPWR identify bus cycles for the NPX. Table 11 defines the types of M80C287 bus cycles.
M80C287 ADDRESSING
The NPS1, NPS2, CMD0, and CMD1 signals allow
the NPX to identify which bus cycles are intended for
the NPX. The NPX responds to I/O cycles when the
I/O address is 00F8H, 00FAH, 00FCH. The correspondence between I/O addresses and control signals is defined by Table 12. To guarantee correct
operation of the NPX, programs must not perform
any I/O operations to these reserved port addresses.
The pins BUSY, PEREQ, and ERROR are used for
various aspects of synchronization between the
CPU and the NPX.
BUSY is used to synchronize instruction transfer
from the M80C286 CPU to the M80C287. When the
M80C287 recognizes an ESC instruction, it asserts
BUSY. For most ESC instructions, the M80C286
CPU waits for the M80C287 to deassert BUSY before sending the new opcode.
The NPX uses the PEREQ pin of the CPU to signal
that the NPX is ready for data transfer to or from its
data FIFO. The NPX does not directly access memory; rather, the CPU provides memory access services for the NPX. Thus, memory access on behalf of
the NPX always obeys the rules applicable to the
mode of the CPU, whether the CPU be in real-address mode or protected mode.
Once the M80C286 CPU initiates an M80C287 instruction that has operands, the M80C286 CPU
waits for PEREQ signals that indicate when the
M80C287 is ready for operand transfer. Once all operands have been transferred (or if the instruction
has no operands) the CPU continues program execution while the M80C287 executes the ESC instruction.
15
M80C287
In M8086/M8087 systems, WAIT instructions may
be required to achieve synchronization of both commands and operands. In M80C287 systems, however, WAIT instructions are required only for operand
synchronization; namely, after NPX stores to memory (except FSTSW and FSTCW) or load from memory. (In M80C286/M80C287 systems, WAIT is required before FLDENV and FRSTOR; with other
CPU’s, WAIT is not required in these cases.) Used
this way, WAIT ensures that the value has already
been written or read by the NPX before the CPU
reads or changes the value.
Once it has started to execute a numerics instruction
and has transferred the operands from the CPU, the
M80C287 can process the instruction in parallel with
and independent of the host CPU. When the NPX
detects an exception, it asserts the ERROR signal,
which causes a CPU interrupt.
Bus Operation
With respect to bus interface, the M80C287 is fully
asynchronous with the CPU, even when it operates
from the same clock source as the CPU. The CPU
initiates a bus cycle for the NPX by activating both
NPS1 and NPS2, the NPX select signals. During the
CLK period in which NPS1 and NPS2 are activated,
the M80C287 also examines the NPRD and NPWR
input signals to determine whether the cycle is a
read or a write cycle and examines the CMD0 and
CMD1 inputs to determine whether an opcode, operand, or control/status register transfer is to occur.
The M80C287 activates its BUSY output some time
after the leading edge of the NPRD or NPWR signal.
Input and output data are referenced to the trailing
edges of the NPRD and NPWR signals.
The M80C287 activates the PEREQ signal when it is
ready for data transfer. In M80286/80C286 systems,
the CPU activates PEACK when no more data transfers are required, which causes the M80C287 to deactivate PEREQ, halting the data transfer.
16
M80287/M80C287 Socket
Compatibility and CPU Interfacing
In general, the M80C287 can fit in existing M80287
sockets, provided that the necessary connections to
VCC and VSS are made and that the clock requirements are met. The pinouts for the M80C287 are
identical to those of the M80287 except for the pins
marked by asterisk (*) in Figure 8. The pins marked
by asterisk are status lines for monitoring ESCAPE
instructions and bus cycles. These lines are not critical for proper operation of an M80287. Note that
when the clock is fed in directly (CKM e 1) the
M80C287 requires a 50% duty cycle clock signal,
whereas the M80287 requires a 33% duty cycle.
Also note that with CKM e 0, the M80C287 divides
the clock input by two, not by three as on the
M80287.
The interface between the M80C287 and the
M80286/M80C286 CPU (illustrated in Figure 9) has
these characteristics:
# The M80C287 resides on the local data bus of
the CPU.
# The CPU and M80C287 share the same RESET
signals. They may also share the same clock input; however, for greatest performance, an external oscillator may be needed.
# The corresponding BUSY, ERROR, PEREQ, and
PEACK pins are connected together.
# NPS2 is tied HIGH permanently, while NPS1,
CMD1, and CMD0 come from the latched address pins. The M80286 generates I/O addresses 00F8H, 00FAH, and 00FCH during NPX bus
cycles. Address 00FEH is reserved.
# The M80C287 NPRD and NPWR inputs are connected to I/O read and write signals from local
bus control logic.
M80C287
271092 – 7
Figure 9. M80C286/M80C287 System Configuration
17
M80C287
ELECTRICAL DATA
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS*
Case temperature (TC)
under bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 55§ C to a 125§ C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Storage temperature ÀÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C
Voltage on any pin
with respect to ground ÀÀÀÀÀÀÀ b 0.5 to VCC a 0.5V
Power dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5 Watt
When the frequency is reduced below the minumum
operating frequency specified in the AC Characteristics table, the internal states of the M80C287 may
become indeterminate. The M80C287 clock cannot
be stopped; otherwise, ICC would increase significantly beyond what the equation above indicates.
Power and Frequency Requirements
The typical relationship between ICC and the frequency of operation F is as follows:
ICCtyp e 55 a 5*F mA , where F is in MHz.
Operating Conditions
Symbol
Parameter
Min
Max
Units
TC
Case Temperature (Instant On)
b 55
a 125
§C
VCC
Digital Supply Voltage
4.75
5.25
V
DC CHARACTERISTICS (Over Specified Operating Conditions)
Min
Max
Units
VIL
Symbol
Input LOW Voltage
b 0.5
a 0.8
V
VIH
Input HIGH Voltage
2.2
VCC a 0.5
V
VICL
Clock Input LOW Voltage
b 0.5
a 0.8
V
VICH
Clock Input HIGH Voltage
2.2
VCC a 0.5
V
VOL
Output LOW Voltage
0.45
V
IOL e 3 mA
VOH
Output HIGH Voltage
V
IOH e b 800 mA
ICC
Power Supply Current
115
mA
CLK e 10 MHz
ILI
Input Leakage Current
g 10
mA
0V s VIN s VCC
ILO
I/O Leakage Current
g 10
mA
0.45V s VOUT s VCC b 0.45
CIN
Input Capacitance
10
pF
FC e 1 MHz
CO
I/O or Output Capacitance
20
pF
FC e 1 MHz
CCLK
Clock Capacitance
12
pF
FC e 1 MHz
18
Parameter
2.4
Comments
M80C287
AC CHARACTERISTICS (Over Specified Operating Conditions)
10 MHz
Symbol
Parameter
Min
(ns)
Max
(ns)
Comments
t6
t7
Data setup to NPWR
Data hold from NPWR
t8
t9
NPWR active time
NPRD active time
t10
t11
Command valid to NPRD
Command valid to NPWR
0
0
t12
Min delay from PEREQ active
to NPRD active
50
t33
t34
t35
PEACK active time
PEACK inactive time
PEACK inactive to
NPRD, NPWR inactive
PEACK active setup to
NPRD, NPWR active
61.5
76.5
40
t37
NPRD, NPWR inactive
to PEACK active
b 30
t38
PEACK Setup to RESET
Falling Edge
80
t39
PEACK Hold from RESET
Falling Edge
80
t18
t19
Command hold from NPWR
Command hold from NPRD
20
20
t20
NPRD, NPWR, RESET to
CLK setup time
NPRD, NPWR, RESET from
CLK hold time
RESET to CLK setup
RESET from CLK hold
54
Note 1
38
Note 1
22
20
Note 1
Note 1
t36
t21
t24
t25
t26
Command inactive time
Write to write
Read to read
Read to write
Write to read
50
18
91.5
91.5
40
76.5
76.5
76.5
76.5
NOTE:
1. This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK
edge (not tested).
19
M80C287
Timing Responses
10 MHz
Symbol
Parameter
t27
t28
NPRD inactive to data float
NPRD active to data valid
t29
ERROR active to BUSY inactive
t30
Min
(ns)
Max
(ns)
Comments
25
60
Note 1
Note 2
NPWR active to BUSY active
100
Note 3
t31
NPRD, NPWR or PEACK
active to PEREQ inactive
100
Note 4
t32
Data hold from NPRD inactive
100
Note 3
3
Note 2
NOTES:
1. The float condition occurs when the measured output current is less than IOL on D15 –D0.
2. D15 – D0 loading: CL e 100pf.
3. BUSYÝ loading: CL e 100pf.
4. On last data transfer of numeric instruction.
Clock Timings
10 MHz
Symbol
t1a
t1b
t2a
t2b
t3a
t3b
t4
t5
Parameter
CLK period
CLK low time
CLK high time
CKM e 1
CKM e 0
CKM e 1
CKM e 0
CKM e 1
CKM e 0
Min
(ns)
Max
(ns)
100
50
35
11
35
18
250
125
CLK fall time
CLK rise time
NOTES:
5. At 0.8V.
6. At 2.0V.
7. CKM e 1: 3.5V to 1.0V
8. CKM e 1: 1.0V to 3.5V
9. Proper operation can also be achieved by meeting the CPU specification
20
Comments
Note 5, 9
10
10
Note 6, 9
Note 7
Note 8
M80C287
271092 – 8
Figure 10. AC Drive and Measurement PointsÐCLK Input
271092 – 9
Figure 11. AC Setup, Hold, and Delay Time MeasurementsÐGeneral
RESET, NPWR, NPRD inputs are asynchronous to
CLK. Timing requirements in Figures 16 through 19
are given for testing purposes only, to assure recognition at a specific CLK edge.
271092 – 10
Figure 12. AC Test Loading on Outputs
21
M80C287
271092 – 11
Figure 13. Data Transfer Timing (Initiated by CPU)
271092 – 12
Figure 14. Data Channel Timing (Initiated by M80C287)
22
M80C287
271092 – 13
Figure 15. ERROR Output Timing
271092 – 14
Figure 16. CLK, RESET Timing (CKM e 1)
271092 – 15
Figure 17. CLK, NPRD, NPWR Timing (CKM e 1)
271092 – 16
NOTE:
RESET must meet timing shown to guarantee known phase of internal divide by 2 circuit.
Figure 18. CLK, RESET Timing (CKM e 0)
23
M80C287
271092 – 17
Figure 19. CLK, NPRD, NPWR Timing (CKM e 0)
271092 – 18
Figure 20. RESET, PEACK Setup and Hold Timing
24
M80C287
tions that have MOD and R/M fields. Its presence
depends on the values of MOD and R/M, as for instructions of the CPU.
M80C287 EXTENSIONS TO THE
CPU’S INSTRUCTION SET
Instructions for the M80C287 assume one of the five
forms shown in Table 13. In all cases, instructions
are at least two bytes long and begin with the bit
pattern 11011B, which identifies the ESCAPE class
of instruction. Instructions that refer to memory operands specify addresses using the CPU’s addressing
modes.
The instruction summaries that follow assume that
the instruction has been prefetched, decoded, and is
ready for execution; that bus cycles do not require
wait states; that there are no local bus HOLD requests delaying processor access to the bus; and
that no exceptions are detected during instruction
execution. Timings are given in internal M80C287
clocks and include the time for opcode and data
transfer between the CPU and the NPX. If the instruction has MOD and R/M fields that call for both
base and index registers, add one clock.
MOD (Mode field) and R/M (Register/Memory specifier) have the same interpretation as the corresponding fields of CPU instructions (refer to Programmer’s Reference Manual for the CPU). The
DISP (displacement) is optionally present in instruc-
Table 13. Instruction Formats
Instruction
First Byte
OPA
Optional
Field
Second Byte
1
11011
1
2
11011
3
11011
d
P
OPA
1
1
4
11011
0
0
1
1
1
1
OP
5
11011
0
1
1
1
1
1
OP
15–11
10
9
8
7
6
5
MF
MOD
OPA
1
MOD
OPB
R/M
DISP
OPB*
R/M
DISP
OPB*
ST(i)
4
3
2
1
0
OP e Instruction opcode, possibly split into two fields OPA and OPB
MF e Memory Format
00 – 32-bit real
01 – 32-bit integer
10 – 64-bit real
11 – 16-bit integer
d e Destination
0–Destination is ST(0)
1–Destination is ST(i)
R XOR d e 0-Destination (Op) Source
R XOR d e 1-Source (Op) Destination
*In FSUB and FDIV, the low-order bit of the OPB is the R (reversed) bit
P e Pop
0 – Do not pop stack
1 – Pop stack after operation
ESC e 11011
ST(i) e Register stack element i
000 e Stack top
001 e Second stack element
#
#
#
111 e Eighth stack element
25
M80C287
M80C287 Extension to the CPU’s Instruction Set
Byte
0
Encoding
Byte
1
Optional
Bytes 2 – 3
32-Bit
Real
DATA TRANSFER
FLD e Load1
Integer/real memory to ST(0)
ESC MF 1
MOD 000 R/M
SIB/DISP
36
Long integer memory to ST(0)
ESC 111
MOD 101 R/M
SIB/DISP
Extended real memory to ST(0)
ESC 011
MOD 101 R/M
SIB/DISP
48
BCD memory to ST(0)
ESC 111
MOD 100 R/M
SIB/DISP
270 – 279
ST(i) to ST(0)
ESC 001
11000 ST(i)
ST(0) to integer/real memory
ESC MF 1
MOD 010 R/M
ST(0) to ST(i)
ESC 101
11010 ST(i)
Instruction
Clock Count Range
32-Bit
64-Bit
Integer
Real
61 – 68
45
16-Bit
Integer
61 – 65
76 – 87
21
FST e Store
SIB/DISP
51
86 – 100
56
88 – 101
56
88 – 101
18
FSTP e Store and Pop
ST(0) to integer/real memory
ESC MF 1
MOD 011 R/M
SIB/DISP
ST(0) to long integer memory
ESC 111
MOD 111 R/M
SIB/DISP
51
86 – 100
91 – 108
ST(0) to extended real
ESC 011
MOD 111 R/M
SIB/DISP
61
ST(0) to BCD memory
ESC 111
MOD 110 R/M
SIB/DISP
520 – 542
ST(0) to ST(i)
ESC 101
11001 ST (i)
19
ESC 001
11001 ST(i)
25
Integer/real memory to ST(0)
ESC MF 0
MOD 010 R/M
ST(i) to ST(0)
ESC 000
11010 ST(i)
Integer/real memory to ST
ESC MF 0
MOD 011 R/M
ST(i) to ST(0)
ESC 000
11011 ST(i)
33
ESC 110
1101 1001
33
FXCH e Exchange
ST(i) and ST(0)
COMPARISON
FCOM e Compare
SIB/DISP
42
72 – 79
51
71 – 75
51
71 – 77
31
FCOMP e Compare and pop
SIB/DISP
42
72 – 79
FCOMPP e Compare and pop twice
ST(1) to ST(0)
FTST e Test ST(0)
ESC 001
1110 0100
35
FUCOM e Unordered compare
ESC 101
11100 ST(i)
31
33
FUCOMP e Unordered compare
ESC 101
11101 ST(i)
FUCOMPP e Unordered compare
and pop twice
and pop
ESC 010
1110 1001
33
FXAM e Examine ST(0)
ESC 001
11100101
37 – 45
FLDZ e Load a 0.0 into ST(0)
ESC 001
1110 1110
27
FLD1 e Load a 1.0 into ST(0)
ESC 001
1110 1000
31
FLDPI e Load pi into ST(0)
ESC 001
1110 1011
47
FLDL2T e Load log2(10) into ST(0)
ESC 001
1110 1001
47
CONSTANTS
Shaded areas indicate instructions not available in M8087/M80287.
NOTE:
1. When loading single- or double-precision zero from memory, add 5 clocks.
26
M80C287
M80C287 Extension to the CPU’s Instruction Set (Continued)
Encoding
Instruction
Byte
0
Byte
1
Clock Count Range
Optional
Bytes 2 – 3
32-Bit
Real
32-Bit
Integer
64-Bit
Real
16-Bit
Integer
49 – 79
71 – 85
CONSTANTS (Continued)
FLDL2E e Load log2(e) into ST(0)
ESC 001
1110 1010
47
FLDLG2 e Load log10(2) into ST(0)
ESC 001
1110 1100
48
FLDLN2 e Load loge(2) into ST(0)
ESC 001
1110 1101
48
Integer/real memory with ST(0)
ESC MF 0
MOD 000 R/M
ST(i) and ST(0)
ESC d P 0
11000 ST(9)
Integer/real memory with ST(0)
ESC MF 0
MOD 10 R R/M
ST(i) and ST(0)
ESC d P 0
1110 R R/M
ESC MF 0
MOD 001 R/M
ARITHMETIC
FADD e Add
SIB/DISP
40 – 48
73 – 78
30 – 382
FSUB e Subtract
SIB/DISP
40 – 48
73 – 98
49 – 77
71 – 833
33 – 414
FMUL e Multiply
Integer/real memory with ST(0)
ST(i) and ST(0)
ESC d P 0
1100 1 R/M
Integer/real memory with ST(0)
ESC MF 0
MOD 11 R R/M
ST(i) and ST(0)
SIB/DISP
43 – 51
77 – 88
52 – 77
76 – 87
25 – 535
FDIV e Divide
SIB/DISP
105
136 – 1436
114
ESC d P 0
1111 R R/M
958
FSQRTi e Square root
ESC 001
1111 1010
129 – 136
FSCALE e Scale ST(0) by ST(1)
ESC 001
1111 1101
74 – 93
FPREM e Partial remainder of
ST(0) d ST(1)
ESC 001
1111 1000
81 – 162
ESC 001
1111 0101
102 – 192
ESC 001
1111 1100
73 – 87
75 – 83
136 – 1407
FPREM1 e Partial remainder
(IEEE)
FRNDINT e Round ST(0)
to integer
FXTRACT e Extract components
of ST(0)
ESC 001
1111 0100
FABS e Absolute value of ST(0)
ESC 001
1110 0001
29
FCHS e Change sign of ST(0)
ESC 001
1110 0000
31 – 37
Shaded areas indicate instructions not available in M8087/M80287.
NOTES:
2. Add 3 clocks to the range when d e 1.
3. Add 1 clock to each range when R e 1.
4. Add 3 clocks to the range when d e 0.
5. Typical e 48 (When d e 0, 42–50, typical e 45).
6. Add 1 clock to the range when R e 1.
7. 135 – 141 when R e 1.
8. Add 3 clocks to the range when d e 1.
9. b0 s ST(0) s a % .
27
M80C287
M80C287 Extension to the CPU’s Instruction Set (Continued)
Encoding
Instruction
Optional
Bytes 2 – 3
Clock Count Range
Byte
0
Byte
1
FCOS e Cosine of ST(0)
ESC 001
1111 1111
130 – 77910
FPTAN11 e Partial tangent of ST(0)
ESC 001
1111 0010
198 – 504j
FPATAN e Partial arctangent
ESC 001
1111 0011
321 – 494
FSIN e Sine of ST(0)
ESC 001
1111 1110
129 – 77810
FSINCOS e Sine and cosine of ST(0)
ESC 001
1111 1011
201 – 81610
F2XM112 e 2ST(0) b 1
ESC 001
1111 0000
215 – 483
FYL2X13 e ST(1) * log2(ST(0))
ESC 001
1111 0001
127 – 545
FYL2XP114 e ST(1) * log2(ST(0) a 1.0)
ESC 001
1111 1001
264 – 554
TRANSCENDENTAL
PROCESSOR CONTROL
FINIT e Initialize NPX
ESC 011
1110 0011
25
FSETPM e Set protected mode
ESC 011
1110 0100
12
FRSTPM e Reset protected mode
ESC 011
1111 0100
12
FSTSW AX e Store status word
ESC 111
1110 0000
18
FLDCW e Load control word
ESC 001
MOD 101 R/M
SIB/DISP
33
FSTCW e Store control word
ESC 101
MOD 111 R/M
SIB/DISP
18
FSTSW e Store status word
ESC 101
MOD 111 R/M
SIB/DISP
18
FCLEX e Clear exceptions
ESC 011
1110 0010
FSTENV e Store environment
ESC 001
MOD 110 R/M
SIB/DISP
192 – 193
FLDENV e Load environment
ESC 001
MOD 100 R/M
SIB/DISP
85
FSAVE e Save state
ESC 101
MOD 110 R/M
SIB/DISP
521 – 522
FRSTOR e Restore state
ESC 101
MOD 100 R/M
SIB/DISP
396
FINCSTP e Increment stack pointer
ESC 001
1111 0111
FDECSTP e Decrement stack pointer
ESC 001
1111 0110
29
FFREE e Free ST(12)
ESC 101
1100 0 ST(12)
25
FNOP e No operations
ESC 001
1101 0000
19
8
28
Shaded areas indicate instructions not available in M8087/M80287.
NOTES:
10. These timings hold for operands in the range lxl k q/4. For operands not in this range, up to 78 additional clocks may
be needed to reduce the operand.
11. 0 s l ST(0) l k 263.
12. b1.0 s ST(0) s 1.0.
13. 0 s ST(0) k % , b % k ST(1) k a % .
14. 0 s lST(0)l k (2 b SQRT(2))/2, b % k ST(1) k a % .
28
M80C287
APPENDIX A
COMPATIBILITY BETWEEN
THE M80287 AND THE M8087
The M80286/M80287 operating in Real-Address
mode will execute M8086/M8087 programs without
major modification. However, because of differences
in the handling of numeric exceptions by the
M80287 NPX and the M8087 NPX, exception-handling routines may need to be changed.
This appendix summarizes the differences between
the M80287 NPX and the M8087 NPX, and provides
details showing how M8086/M8087 programs can
be ported to the M80286/M80287.
1. The NPX signals exceptions through a dedicated
ERROR line to the M80286. The NPX error signal
does not pass through an interrupt controller (the
M8087 INT signal does). Therefore, any interruptcontroller-oriented instructions in numeric exception handlers for the M8086/M8087 should be deleted.
2. The M8087 instructions FEN/FNENI and FDISI/
FNDISI perform no useful function in the M80287.
If the M80287 encounters one of these opcodes
in its instruction stream, the instruction will effectively be ignoredÐnone of the M80287 internal
states will be updated. While M8086/M8087 containing these instructions may be executed on the
M80286/M80287, it is unlikely that the exceptionhandling routines containing these instructions
will be completely portable to the M80287.
3. Interrupt vector 16 must point to the numeric exception handling routine.
4. The ESC instruction address saved in the
M80287 includes any leading prefixes before the
ESC opcode. The corresponding address saved
in the M8087 does not include leading prefixes.
5. In Protected-Address mode, the format of the
M80287’s saved instruction and address pointers
is different than for the M8087. The instruction
opcode is not saved in Protected modeÐexception handlers will have to retrieve the opcode from
memory if needed.
6. Interrupt 7 will occur in the M80286 when executing ESC instructions with either TS (task
switched) or EM (emulation) of the M80286 MSW
set (TS e 1 or EM e 1). If TS is set, then a WAIT
instruction will also cause interrupt 7. An exception handler should be included in M80286/
M80287 code to handle these situations.
7. Interrupt 9 will occur if the second or subsequent
words of a floating-point operand fall outside a
segment’s size. Interrupt 13 will occur if the starting address of a numeric operand falls outside a
segment’s size. An exception handler should be
included in M80286/M80287 code to report these
programming errors.
8. Except for the processor control instructions, all
of the M80287 numeric instructions are automatically synchronized by the M80286 CPUÐthe
M80286 automatically tests the BUSY line from
the M80287 to ensure that the M80287 has completed its previous instruction before executing
the next ESC instruction. No explicit WAIT instructions are required to assure this synchronization.
For the M8087 used with M8086 and M8088 processors, explicit WAITs are required before each
numeric instruction to ensure synchronization. Although M8086/M8087 programs having explicit
WAIT instructions will execute perfectly on the
M80286/M80287 without reassembly, these
WAIT instructions are unnecessary.
9. Since the M80287 does not require WAIT instructions before each numeric instruction, the
ASM286 assembler does not automatically generate these WAIT instructions. The ASM86 assembler, however, automatically precedes every ESC
instruction with a WAIT instruction. Although numeric routines generated using the ASM86 assembler will generally execute correctly on the
M80286/M80287, reassembly using ASM286
may result in a more compact code image.
The processor control instructions for the M80287
may be coded using either a WAIT or No-WAIT
form of mnemonic. The WAIT forms of these instructions cause ASM286 to precede the ESC instruction with a CPU WAIT instruction, in the identical manner as does ASM86.
A-1